embassy/embassy-stm32/src/rcc/g4.rs, branch fix-input-sync-bypass

stm32: disable HSI48 if not in use

2025-12-19T03:15:57+00:00

fixup! feat(stm32-g4): provide a `const` constructor on `rcc::Config`

2025-05-26T12:43:29+00:00

feat(stm32-g4): provide a `const` constructor on `rcc::Config`

2025-05-21T12:19:12+00:00

stm32: update metapac, cleanup clocks a bit.

2025-04-18T18:32:15+00:00

Add missing clock check

2024-11-27T09:44:03+00:00

Add new

2024-11-27T04:23:13+00:00

Add new feature to enable overclocking

2024-11-26T04:46:20+00:00

Fix dma nvic issues on dual core lines

2024-08-17T13:54:41+00:00

This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup.
Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration.
This ensures that each core will only handle the interrupts of the DMA channels that it uses.

stm32: ensure the core runs on HSI clock while setting up rcc

2024-05-27T15:31:29+00:00

stm32/rcc: g4: consistent PllSource, add pll pqr limits, simplify a bit.

2024-03-03T23:04:06+00:00