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<title>embassy/examples/stm32h5/src/bin/adc_dma.rs, branch main</title>
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<title>adc: type-erase regs instance</title>
<updated>2025-12-06T18:17:00+00:00</updated>
<author>
<name>xoviat</name>
<email>xoviat@users.noreply.github.com</email>
</author>
<published>2025-12-06T18:17:00+00:00</published>
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<entry>
<title>fix async adc for h5 and others</title>
<updated>2025-11-13T23:41:20+00:00</updated>
<author>
<name>xoviat</name>
<email>xoviat@users.noreply.github.com</email>
</author>
<published>2025-11-13T23:41:20+00:00</published>
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closes #4882.
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closes #4882.
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<entry>
<title>Fix examples</title>
<updated>2025-08-29T11:24:53+00:00</updated>
<author>
<name>diondokter</name>
<email>diondokter@gmail.com</email>
</author>
<published>2025-08-29T10:36:17+00:00</published>
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<entry>
<title>stm32/adc/v3: allow DMA reads to loop through enabled channels</title>
<updated>2025-08-22T18:56:19+00:00</updated>
<author>
<name>Gabriel Smith</name>
<email>ga29smith@gmail.com</email>
</author>
<published>2025-06-13T12:59:56+00:00</published>
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Tested on an STM32H533RE. Documentation of other chips has been
reviewed, but not extensively.
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Tested on an STM32H533RE. Documentation of other chips has been
reviewed, but not extensively.
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