120 files changed, 4010 insertions, 999 deletions

diff --git a/.github/ci/build-xtensa.sh b/.github/ci/build-xtensa.sh
index f07816861..cc56adb26 100755
--- a/.github/ci/build-xtensa.sh
+++ b/.github/ci/build-xtensa.sh
@@ -14,7 +14,7 @@ export PATH=$CARGO_HOME/bin:$PATH
 export CARGO_NET_GIT_FETCH_WITH_CLI=true
 
 cargo install espup --locked
-espup install --toolchain-version 1.88.0.0
+espup install --toolchain-version 1.90.0.0
 
 # Restore lockfiles
 if [ -f /ci/cache/lockfiles.tar ]; then
diff --git a/.vscode/settings.json b/.vscode/settings.json
index 73dfa53a4..2b99a313d 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -34,6 +34,7 @@
     // "examples/mspm0c1104/Cargo.toml",
     // "examples/mspm0g3507/Cargo.toml",
     // "examples/mspm0g3519/Cargo.toml",
+    // "examples/mspm0g5187/Cargo.toml",
     // "examples/mspm0l1306/Cargo.toml",
     // "examples/mspm0l2228/Cargo.toml",
     // "examples/nrf52840-rtic/Cargo.toml",
diff --git a/ci.sh b/ci.sh
index 4f78f70cf..1eecd158f 100755
--- a/ci.sh
+++ b/ci.sh
@@ -35,7 +35,7 @@ rm -rf out/tests/nrf5340-dk
 # disabled because these boards are not on the shelf
 rm -rf out/tests/mspm0g3507
 
-# rm out/tests/stm32wb55rg/wpan_mac
+rm out/tests/stm32wb55rg/wpan_mac
 rm out/tests/stm32wb55rg/wpan_ble
 
 # unstable, I think it's running out of RAM?
diff --git a/docs/examples/basic/Cargo.toml b/docs/examples/basic/Cargo.toml
index fadda102b..495e484f8 100644
--- a/docs/examples/basic/Cargo.toml
+++ b/docs/examples/basic/Cargo.toml
@@ -9,7 +9,7 @@ publish = false
 [dependencies]
 embassy-executor = { version = "0.9.0", path = "../../../embassy-executor", features = ["defmt", "arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.5.0", path = "../../../embassy-time", features = ["defmt"] }
-embassy-nrf = { version = "0.8.0", path = "../../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote"] }
+embassy-nrf = { version = "0.9.0", path = "../../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/embassy-boot-nrf/CHANGELOG.md b/embassy-boot-nrf/CHANGELOG.md
index 54b7c8067..5bf8cf4b0 100644
--- a/embassy-boot-nrf/CHANGELOG.md
+++ b/embassy-boot-nrf/CHANGELOG.md
@@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+## 0.10.0 - 2025-12-15
+
+- Bumped embassy-nrf to 0.9.0
+
 ## 0.9.0 - 2025-09-30
 
 - Bumped embassy-nrf to 0.8.0
diff --git a/embassy-boot-nrf/Cargo.toml b/embassy-boot-nrf/Cargo.toml
index 787a28d70..4f6d9ed2e 100644
--- a/embassy-boot-nrf/Cargo.toml
+++ b/embassy-boot-nrf/Cargo.toml
@@ -1,7 +1,7 @@
 [package]
 edition = "2024"
 name = "embassy-boot-nrf"
-version = "0.9.0"
+version = "0.10.0"
 description = "Bootloader lib for nRF chips"
 license = "MIT OR Apache-2.0"
 repository = "https://github.com/embassy-rs/embassy"
@@ -36,7 +36,7 @@ defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.17", optional = true }
 
 embassy-sync = { version = "0.7.2", path = "../embassy-sync" }
-embassy-nrf = { version = "0.8.0", path = "../embassy-nrf", default-features = false }
+embassy-nrf = { version = "0.9.0", path = "../embassy-nrf", default-features = false }
 embassy-boot = { version = "0.6.1", path = "../embassy-boot" }
 cortex-m = { version = "0.7.6" }
 cortex-m-rt = { version = "0.7" }
diff --git a/embassy-executor/CHANGELOG.md b/embassy-executor/CHANGELOG.md
index 5fbb8cf13..8f1db7de7 100644
--- a/embassy-executor/CHANGELOG.md
+++ b/embassy-executor/CHANGELOG.md
@@ -15,6 +15,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Added optional "earliest deadline first" EDF scheduling
 - Migrate `cortex-ar` to `aarch32-cpu`. The feature name `arch-cortex-ar` remains the same and
   legacy ARM architectures are not supported.
+- Added `run_until` to `arch-std` variant of `Executor`.
 
 ## 0.9.1 - 2025-08-31
 
diff --git a/embassy-executor/src/arch/std.rs b/embassy-executor/src/arch/std.rs
index c62ab723b..d4057144e 100644
--- a/embassy-executor/src/arch/std.rs
+++ b/embassy-executor/src/arch/std.rs
@@ -55,11 +55,24 @@ mod thread {
         ///
         /// This function never returns.
         pub fn run(&'static mut self, init: impl FnOnce(Spawner)) -> ! {
+            self.run_until(init, || false);
+            unreachable!()
+        }
+
+        /// Run the executor until a flag is raised.
+        ///
+        /// This function is identical to `Executor::run()` apart from offering a `done` flag to stop execution.
+        pub fn run_until(&'static mut self, init: impl FnOnce(Spawner), mut done: impl FnMut() -> bool) {
             init(self.inner.spawner());
 
             loop {
                 unsafe { self.inner.poll() };
-                self.signaler.wait()
+
+                if done() {
+                    break;
+                }
+
+                self.signaler.wait();
             }
         }
     }
diff --git a/embassy-executor/tests/ui/bad_return_impl_future_nightly.stderr b/embassy-executor/tests/ui/bad_return_impl_future_nightly.stderr
index 3c3c9503b..e5e069ade 100644
--- a/embassy-executor/tests/ui/bad_return_impl_future_nightly.stderr
+++ b/embassy-executor/tests/ui/bad_return_impl_future_nightly.stderr
@@ -5,6 +5,10 @@ error[E0277]: task futures must resolve to `()` or `!`
   | ^^^^^^^^^^^^^^^^^^^^^^^^^ the trait `TaskReturnValue` is not implemented for `u32`
   |
   = note: use `async fn` or change the return type to `impl Future<Output = ()>`
-  = help: the following other types implement trait `TaskReturnValue`:
-            ()
-            <fn() -> ! as HasOutput>::Output
+help: the following other types implement trait `TaskReturnValue`
+ --> src/lib.rs
+  |
+  |     impl TaskReturnValue for () {}
+  |     ^^^^^^^^^^^^^^^^^^^^^^^^^^^ `()`
+  |     impl TaskReturnValue for Never {}
+  |     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ `<fn() -> ! as HasOutput>::Output`
diff --git a/embassy-imxrt/Cargo.toml b/embassy-imxrt/Cargo.toml
index c47756f10..81377579b 100644
--- a/embassy-imxrt/Cargo.toml
+++ b/embassy-imxrt/Cargo.toml
@@ -103,5 +103,5 @@ document-features = "0.2.7"
 paste = "1.0"
 
 # PACs
-mimxrt685s-pac = { version = "0.4.0", optional = true, features = ["rt", "critical-section"] }
-mimxrt633s-pac = { version = "0.4.0", optional = true, features = ["rt", "critical-section"] }
+mimxrt685s-pac = { version = "0.5.0", optional = true, features = ["rt", "critical-section"] }
+mimxrt633s-pac = { version = "0.5.0", optional = true, features = ["rt", "critical-section"] }
diff --git a/embassy-imxrt/src/dma.rs b/embassy-imxrt/src/dma.rs
index e71a27e0e..eaa09870d 100644
--- a/embassy-imxrt/src/dma.rs
+++ b/embassy-imxrt/src/dma.rs
@@ -16,6 +16,8 @@ use crate::peripherals::DMA0;
 use crate::sealed::Sealed;
 use crate::{BitIter, interrupt, pac, peripherals};
 
+pub(crate) const MAX_CHUNK_SIZE: usize = 1024;
+
 #[cfg(feature = "rt")]
 #[interrupt]
 fn DMA0() {
@@ -69,7 +71,7 @@ pub(crate) unsafe fn init() {
 ///
 /// SAFETY: Slice must point to a valid location reachable by DMA.
 pub unsafe fn read<'a, C: Channel, W: Word>(ch: Peri<'a, C>, from: *const W, to: *mut [W]) -> Transfer<'a, C> {
-    let count = ((to.len() / W::size() as usize) - 1) as isize;
+    let count = (to.len().div_ceil(W::size() as usize) - 1) as isize;
 
     copy_inner(
         ch,
@@ -87,7 +89,7 @@ pub unsafe fn read<'a, C: Channel, W: Word>(ch: Peri<'a, C>, from: *const W, to:
 ///
 /// SAFETY: Slice must point to a valid location reachable by DMA.
 pub unsafe fn write<'a, C: Channel, W: Word>(ch: Peri<'a, C>, from: *const [W], to: *mut W) -> Transfer<'a, C> {
-    let count = ((from.len() / W::size() as usize) - 1) as isize;
+    let count = (from.len().div_ceil(W::size() as usize) - 1) as isize;
 
     copy_inner(
         ch,
@@ -109,7 +111,7 @@ pub unsafe fn copy<'a, C: Channel, W: Word>(ch: Peri<'a, C>, from: &[W], to: &mu
     let to_len = to.len();
     assert_eq!(from_len, to_len);
 
-    let count = ((from_len / W::size() as usize) - 1) as isize;
+    let count = (from_len.div_ceil(W::size() as usize) - 1) as isize;
 
     copy_inner(
         ch,
diff --git a/embassy-imxrt/src/flexcomm/mod.rs b/embassy-imxrt/src/flexcomm/mod.rs
index 27794042b..ed87c7fb4 100644
--- a/embassy-imxrt/src/flexcomm/mod.rs
+++ b/embassy-imxrt/src/flexcomm/mod.rs
@@ -1,5 +1,6 @@
 //! Implements Flexcomm interface wrapper for easier usage across modules
 
+pub mod spi;
 pub mod uart;
 
 use paste::paste;
diff --git a/embassy-imxrt/src/flexcomm/spi.rs b/embassy-imxrt/src/flexcomm/spi.rs
new file mode 100644
index 000000000..9dd776ac7
--- /dev/null
+++ b/embassy-imxrt/src/flexcomm/spi.rs
@@ -0,0 +1,1011 @@
+//! Serial Peripheral Interface (SPI) driver.
+
+use core::future::{Future, poll_fn};
+use core::marker::PhantomData;
+use core::task::Poll;
+
+use embassy_embedded_hal::SetConfig;
+use embassy_hal_internal::{Peri, PeripheralType};
+use embassy_sync::waitqueue::AtomicWaker;
+pub use embedded_hal_1::spi::{MODE_0, MODE_1, MODE_2, MODE_3, Mode, Phase, Polarity};
+use paste::paste;
+
+use crate::flexcomm::Clock;
+use crate::gpio::{AnyPin, GpioPin as Pin};
+use crate::interrupt;
+use crate::interrupt::typelevel::Interrupt;
+use crate::iopctl::{DriveMode, DriveStrength, Inverter, IopctlPin, Pull, SlewRate};
+use crate::pac::spi0::cfg::{Cpha, Cpol};
+
+/// Driver move trait.
+#[allow(private_bounds)]
+pub trait IoMode: sealed::Sealed {}
+
+/// Blocking mode.
+pub struct Blocking;
+impl sealed::Sealed for Blocking {}
+impl IoMode for Blocking {}
+
+/// Async mode.
+pub struct Async;
+impl sealed::Sealed for Async {}
+impl IoMode for Async {}
+
+/// Spi errors.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+    // No errors for now.
+}
+
+/// Spi driver.
+pub struct Spi<'a, M: IoMode> {
+    info: Info,
+    _phantom: PhantomData<&'a M>,
+}
+
+impl<'a> Spi<'a, Blocking> {
+    /// Create a SPI driver in blocking mode.
+    pub fn new_blocking<T: Instance>(
+        _inner: Peri<'a, T>,
+        sck: Peri<'a, impl SckPin<T> + 'a>,
+        mosi: Peri<'a, impl MosiPin<T> + 'a>,
+        miso: Peri<'a, impl MisoPin<T> + 'a>,
+        config: Config,
+    ) -> Self {
+        sck.as_sck();
+        mosi.as_mosi();
+        miso.as_miso();
+
+        Self::new_inner(_inner, Some(sck.into()), Some(mosi.into()), Some(miso.into()), config)
+    }
+
+    /// Create a TX-only SPI driver in blocking mode.
+    pub fn new_blocking_txonly<T: Instance>(
+        _inner: Peri<'a, T>,
+        sck: Peri<'a, impl SckPin<T> + 'a>,
+        mosi: Peri<'a, impl MosiPin<T> + 'a>,
+        config: Config,
+    ) -> Self {
+        sck.as_sck();
+        mosi.as_mosi();
+
+        Self::new_inner(_inner, Some(sck.into()), Some(mosi.into()), None, config)
+    }
+
+    /// Create an RX-only SPI driver in blocking mode.
+    pub fn new_blocking_rxonly<T: Instance>(
+        _inner: Peri<'a, T>,
+        sck: Peri<'a, impl SckPin<T> + 'a>,
+        miso: Peri<'a, impl MisoPin<T> + 'a>,
+        config: Config,
+    ) -> Self {
+        sck.as_sck();
+        miso.as_miso();
+
+        Self::new_inner(_inner, Some(sck.into()), None, Some(miso.into()), config)
+    }
+
+    /// Create an internal-loopback SPI driver in blocking mode.
+    ///
+    /// WARNING: This is only useful for testing as it doesn't use any
+    /// external pins.
+    pub fn new_blocking_loopback<T: Instance>(_inner: Peri<'a, T>, config: Config) -> Self {
+        Self::new_inner(_inner, None, None, None, config)
+    }
+}
+
+impl<'a, M: IoMode> Spi<'a, M> {
+    /// Read data from Spi blocking execution until done.
+    pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<(), Error> {
+        critical_section::with(|_| {
+            self.info
+                .regs
+                .fifostat()
+                .modify(|_, w| w.txerr().set_bit().rxerr().set_bit());
+
+            for word in data.iter_mut() {
+                // wait until we have data in the RxFIFO.
+                while self.info.regs.fifostat().read().rxnotempty().bit_is_clear() {}
+
+                self.info
+                    .regs
+                    .fifowr()
+                    .write(|w| unsafe { w.txdata().bits(*word as u16).len().bits(7) });
+
+                *word = self.info.regs.fiford().read().rxdata().bits() as u8;
+            }
+        });
+
+        self.flush()
+    }
+
+    /// Write data to Spi blocking execution until done.
+    pub fn blocking_write(&mut self, data: &[u8]) -> Result<(), Error> {
+        critical_section::with(|_| {
+            self.info
+                .regs
+                .fifostat()
+                .modify(|_, w| w.txerr().set_bit().rxerr().set_bit());
+
+            for (i, word) in data.iter().enumerate() {
+                // wait until we have space in the TxFIFO.
+                while self.info.regs.fifostat().read().txnotfull().bit_is_clear() {}
+
+                self.info.regs.fifowr().write(|w| {
+                    unsafe { w.txdata().bits(*word as u16).len().bits(7) }
+                        .rxignore()
+                        .set_bit();
+
+                    if i == data.len() - 1 {
+                        w.eot().set_bit();
+                    }
+
+                    w
+                });
+            }
+        });
+
+        self.flush()
+    }
+
+    /// Transfer data to SPI blocking execution until done.
+    pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
+        let len = read.len().max(write.len());
+
+        critical_section::with(|_| {
+            self.info
+                .regs
+                .fifostat()
+                .modify(|_, w| w.txerr().set_bit().rxerr().set_bit());
+
+            for i in 0..len {
+                let wb = write.get(i).copied().unwrap_or(0);
+
+                // wait until we have space in the TxFIFO.
+                while self.info.regs.fifostat().read().txnotfull().bit_is_clear() {}
+
+                self.info.regs.fifowr().write(|w| {
+                    unsafe { w.txdata().bits(wb as u16).len().bits(7) };
+
+                    if i == len - 1 {
+                        w.eot().set_bit();
+                    }
+
+                    w
+                });
+
+                // wait until we have data in the RxFIFO.
+                while self.info.regs.fifostat().read().rxnotempty().bit_is_clear() {}
+
+                let rb = self.info.regs.fiford().read().rxdata().bits() as u8;
+
+                if let Some(r) = read.get_mut(i) {
+                    *r = rb;
+                }
+            }
+        });
+
+        self.flush()
+    }
+
+    /// Transfer data in place to SPI blocking execution until done.
+    pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
+        critical_section::with(|_| {
+            self.info
+                .regs
+                .fifostat()
+                .modify(|_, w| w.txerr().set_bit().rxerr().set_bit());
+
+            for word in data {
+                // wait until we have space in the TxFIFO.
+                while self.info.regs.fifostat().read().txnotfull().bit_is_clear() {}
+                self.info
+                    .regs
+                    .fifowr()
+                    .write(|w| unsafe { w.txdata().bits(*word as u16) });
+
+                // wait until we have data in the RxFIFO.
+                while self.info.regs.fifostat().read().rxnotempty().bit_is_clear() {}
+                *word = self.info.regs.fiford().read().rxdata().bits() as u8;
+            }
+        });
+
+        self.flush()
+    }
+
+    /// Block execution until Spi is done.
+    pub fn flush(&mut self) -> Result<(), Error> {
+        let regs = self.info.regs;
+        while regs.stat().read().mstidle().bit_is_clear() {}
+        Ok(())
+    }
+}
+
+impl<'a> Spi<'a, Async> {
+    /// Create a SPI driver in async mode.
+    pub fn new_async<T: Instance>(
+        _inner: Peri<'a, T>,
+        sck: Peri<'a, impl SckPin<T> + 'a>,
+        mosi: Peri<'a, impl MosiPin<T> + 'a>,
+        miso: Peri<'a, impl MisoPin<T> + 'a>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'a,
+        config: Config,
+    ) -> Self {
+        sck.as_sck();
+        mosi.as_mosi();
+        miso.as_miso();
+
+        T::Interrupt::unpend();
+        unsafe { T::Interrupt::enable() };
+
+        Self::new_inner(_inner, Some(sck.into()), Some(mosi.into()), Some(miso.into()), config)
+    }
+
+    /// Create a TX-only SPI driver in async mode.
+    pub fn new_async_txonly<T: Instance>(
+        _inner: Peri<'a, T>,
+        sck: Peri<'a, impl SckPin<T> + 'a>,
+        mosi: Peri<'a, impl MosiPin<T> + 'a>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'a,
+        config: Config,
+    ) -> Self {
+        sck.as_sck();
+        mosi.as_mosi();
+
+        T::Interrupt::unpend();
+        unsafe { T::Interrupt::enable() };
+
+        Self::new_inner(_inner, Some(sck.into()), Some(mosi.into()), None, config)
+    }
+
+    /// Create an RX-only SPI driver in async mode.
+    pub fn new_async_rxonly<T: Instance>(
+        _inner: Peri<'a, T>,
+        sck: Peri<'a, impl SckPin<T> + 'a>,
+        miso: Peri<'a, impl MisoPin<T> + 'a>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'a,
+        config: Config,
+    ) -> Self {
+        sck.as_sck();
+        miso.as_miso();
+
+        T::Interrupt::unpend();
+        unsafe { T::Interrupt::enable() };
+
+        Self::new_inner(_inner, Some(sck.into()), None, Some(miso.into()), config)
+    }
+
+    /// Create an internal-loopback SPI driver in async mode.
+    ///
+    /// WARNING: This is only useful for testing as it doesn't use any
+    /// external pins.
+    pub fn new_async_loopback<T: Instance>(
+        _inner: Peri<'a, T>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'a,
+        config: Config,
+    ) -> Self {
+        T::Interrupt::unpend();
+        unsafe { T::Interrupt::enable() };
+
+        Self::new_inner(_inner, None, None, None, config)
+    }
+
+    /// Read data from Spi async execution until done.
+    pub async fn async_read(&mut self, data: &mut [u8]) -> Result<(), Error> {
+        critical_section::with(|_| {
+            self.info
+                .regs
+                .fifostat()
+                .modify(|_, w| w.txerr().set_bit().rxerr().set_bit());
+        });
+
+        for word in data.iter_mut() {
+            // wait until we have data in the RxFIFO.
+            self.wait_for(
+                |me| {
+                    if me.info.regs.fifostat().read().rxnotempty().bit_is_set() {
+                        Poll::Ready(())
+                    } else {
+                        Poll::Pending
+                    }
+                },
+                |me| {
+                    me.info
+                        .regs
+                        .fifointenset()
+                        .write(|w| w.rxlvl().set_bit().rxerr().set_bit());
+                },
+            )
+            .await;
+
+            self.info
+                .regs
+                .fifowr()
+                .write(|w| unsafe { w.txdata().bits(*word as u16).len().bits(7) });
+
+            *word = self.info.regs.fiford().read().rxdata().bits() as u8;
+        }
+
+        self.async_flush().await;
+
+        Ok(())
+    }
+
+    /// Write data to Spi async execution until done.
+    pub async fn async_write(&mut self, data: &[u8]) -> Result<(), Error> {
+        critical_section::with(|_| {
+            self.info
+                .regs
+                .fifostat()
+                .modify(|_, w| w.txerr().set_bit().rxerr().set_bit());
+        });
+
+        for (i, word) in data.iter().enumerate() {
+            // wait until we have space in the TxFIFO.
+            self.wait_for(
+                |me| {
+                    if me.info.regs.fifostat().read().txnotfull().bit_is_set() {
+                        Poll::Ready(())
+                    } else {
+                        Poll::Pending
+                    }
+                },
+                |me| {
+                    me.info
+                        .regs
+                        .fifointenset()
+                        .write(|w| w.txlvl().set_bit().txerr().set_bit());
+                },
+            )
+            .await;
+
+            self.info.regs.fifowr().write(|w| {
+                unsafe { w.txdata().bits(*word as u16).len().bits(7) }
+                    .rxignore()
+                    .set_bit();
+
+                if i == data.len() - 1 {
+                    w.eot().set_bit();
+                }
+
+                w
+            });
+        }
+
+        self.async_flush().await;
+
+        Ok(())
+    }
+
+    /// Transfer data to SPI async execution until done.
+    pub async fn async_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
+        let len = read.len().max(write.len());
+
+        critical_section::with(|_| {
+            self.info
+                .regs
+                .fifostat()
+                .modify(|_, w| w.txerr().set_bit().rxerr().set_bit());
+        });
+
+        for i in 0..len {
+            let wb = write.get(i).copied().unwrap_or(0);
+
+            // wait until we have space in the TxFIFO.
+            self.wait_for(
+                |me| {
+                    if me.info.regs.fifostat().read().txnotfull().bit_is_set() {
+                        Poll::Ready(())
+                    } else {
+                        Poll::Pending
+                    }
+                },
+                |me| {
+                    me.info.regs.fifotrig().write(|w| w.txlvlena().set_bit());
+                    me.info
+                        .regs
+                        .fifointenset()
+                        .write(|w| w.txlvl().set_bit().txerr().set_bit());
+                },
+            )
+            .await;
+
+            self.info.regs.fifowr().write(|w| {
+                unsafe { w.txdata().bits(wb as u16).len().bits(7) };
+
+                if i == len - 1 {
+                    w.eot().set_bit();
+                }
+
+                w
+            });
+
+            // wait until we have data in the RxFIFO.
+            self.wait_for(
+                |me| {
+                    if me.info.regs.fifostat().read().rxnotempty().bit_is_set() {
+                        Poll::Ready(())
+                    } else {
+                        Poll::Pending
+                    }
+                },
+                |me| {
+                    me.info.regs.fifotrig().write(|w| w.rxlvlena().set_bit());
+                    me.info
+                        .regs
+                        .fifointenset()
+                        .write(|w| w.rxlvl().set_bit().rxerr().set_bit());
+                },
+            )
+            .await;
+
+            let rb = self.info.regs.fiford().read().rxdata().bits() as u8;
+
+            if let Some(r) = read.get_mut(i) {
+                *r = rb;
+            }
+        }
+
+        self.async_flush().await;
+
+        Ok(())
+    }
+
+    /// Transfer data in place to SPI async execution until done.
+    pub async fn async_transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
+        critical_section::with(|_| {
+            self.info
+                .regs
+                .fifostat()
+                .modify(|_, w| w.txerr().set_bit().rxerr().set_bit());
+        });
+
+        for word in data {
+            // wait until we have space in the TxFIFO.
+            self.wait_for(
+                |me| {
+                    if me.info.regs.fifostat().read().txnotfull().bit_is_set() {
+                        Poll::Ready(())
+                    } else {
+                        Poll::Pending
+                    }
+                },
+                |me| {
+                    me.info
+                        .regs
+                        .fifointenset()
+                        .write(|w| w.txlvl().set_bit().txerr().set_bit());
+                },
+            )
+            .await;
+
+            self.info
+                .regs
+                .fifowr()
+                .write(|w| unsafe { w.txdata().bits(*word as u16) });
+
+            // wait until we have data in the RxFIFO.
+            self.wait_for(
+                |me| {
+                    if me.info.regs.fifostat().read().rxnotempty().bit_is_set() {
+                        Poll::Ready(())
+                    } else {
+                        Poll::Pending
+                    }
+                },
+                |me| {
+                    me.info
+                        .regs
+                        .fifointenset()
+                        .write(|w| w.rxlvl().set_bit().rxerr().set_bit());
+                },
+            )
+            .await;
+
+            *word = self.info.regs.fiford().read().rxdata().bits() as u8;
+        }
+
+        self.async_flush().await;
+
+        Ok(())
+    }
+
+    /// Async flush.
+    pub fn async_flush(&mut self) -> impl Future<Output = ()> + use<'_, 'a> {
+        self.wait_for(
+            |me| {
+                if me.info.regs.stat().read().mstidle().bit_is_set() {
+                    Poll::Ready(())
+                } else {
+                    Poll::Pending
+                }
+            },
+            |me| {
+                me.info.regs.intenset().write(|w| w.mstidleen().set_bit());
+            },
+        )
+    }
+
+    /// Calls `f` to check if we are ready or not.
+    /// If not, `g` is called once the waker is set (to eg enable the required interrupts).
+    fn wait_for<F, U, G>(&mut self, mut f: F, mut g: G) -> impl Future<Output = U> + use<'_, 'a, F, U, G>
+    where
+        F: FnMut(&mut Self) -> Poll<U>,
+        G: FnMut(&mut Self),
+    {
+        poll_fn(move |cx| {
+            // Register waker before checking condition, to ensure that wakes/interrupts
+            // aren't lost between f() and g()
+            self.info.waker.register(cx.waker());
+            let r = f(self);
+
+            if r.is_pending() {
+                g(self);
+            }
+
+            r
+        })
+    }
+}
+
+impl<'a, M: IoMode> Spi<'a, M> {
+    fn new_inner<T: Instance>(
+        _inner: Peri<'a, T>,
+        sck: Option<Peri<'a, AnyPin>>,
+        mosi: Option<Peri<'a, AnyPin>>,
+        miso: Option<Peri<'a, AnyPin>>,
+        config: Config,
+    ) -> Self {
+        // REVISIT: allow selecting from multiple clocks.
+        let clk = Self::clock(&config);
+
+        T::enable(clk);
+        T::into_spi();
+
+        Self::apply_config(T::info().regs, &config);
+
+        let info = T::info();
+        let regs = info.regs;
+
+        critical_section::with(|_| match (sck.is_some(), mosi.is_some(), miso.is_some()) {
+            (true, true, true) => {
+                regs.fifocfg().modify(|_, w| {
+                    w.enabletx()
+                        .set_bit()
+                        .emptytx()
+                        .set_bit()
+                        .enablerx()
+                        .set_bit()
+                        .emptyrx()
+                        .set_bit()
+                });
+            }
+            (true, false, true) => {
+                regs.fifocfg().modify(|_, w| {
+                    w.enabletx()
+                        .set_bit()
+                        .emptytx()
+                        .clear_bit()
+                        .enablerx()
+                        .set_bit()
+                        .emptyrx()
+                        .set_bit()
+                });
+            }
+            (true, true, false) => {
+                regs.fifocfg().modify(|_, w| {
+                    w.enabletx()
+                        .set_bit()
+                        .emptytx()
+                        .set_bit()
+                        .enablerx()
+                        .clear_bit()
+                        .emptyrx()
+                        .set_bit()
+                });
+            }
+            (false, _, _) => {
+                regs.fifocfg().modify(|_, w| {
+                    w.enabletx()
+                        .set_bit()
+                        .emptytx()
+                        .set_bit()
+                        .enablerx()
+                        .set_bit()
+                        .emptyrx()
+                        .set_bit()
+                });
+                regs.cfg().modify(|_, w| w.loop_().enabled());
+            }
+            _ => {}
+        });
+
+        Self {
+            info,
+            _phantom: PhantomData,
+        }
+    }
+
+    fn set_config(&mut self, config: &Config) {
+        Self::apply_config(self.info.regs, config);
+    }
+
+    fn clock(config: &Config) -> Clock {
+        const SFRO_CLOCK_SPEED_HZ: u32 = 16_000_000;
+
+        if config.frequency > SFRO_CLOCK_SPEED_HZ {
+            Clock::Ffro
+        } else {
+            Clock::Sfro
+        }
+    }
+
+    fn clock_frequency(clock: Clock) -> u32 {
+        match clock {
+            Clock::Sfro => 16_000_000,
+            Clock::Ffro => 48_000_000,
+            _ => unreachable!(),
+        }
+    }
+
+    fn apply_config(regs: &'static crate::pac::spi0::RegisterBlock, config: &Config) {
+        let polarity = if config.mode.polarity == Polarity::IdleLow {
+            Cpol::Low
+        } else {
+            Cpol::High
+        };
+
+        let phase = if config.mode.phase == Phase::CaptureOnFirstTransition {
+            Cpha::Change
+        } else {
+            Cpha::Capture
+        };
+
+        let clk = Self::clock(config);
+        let div = Self::clock_frequency(clk) / config.frequency - 1;
+
+        critical_section::with(|_| {
+            // disable SPI every time we need to modify configuration.
+            regs.cfg().modify(|_, w| w.enable().disabled());
+
+            regs.cfg().modify(|_, w| {
+                w.cpha()
+                    .variant(phase)
+                    .cpol()
+                    .variant(polarity)
+                    .loop_()
+                    .disabled()
+                    .master()
+                    .master_mode()
+            });
+
+            regs.div().write(|w| unsafe { w.divval().bits(div as u16) });
+
+            regs.cfg().modify(|_, w| w.enable().enabled());
+        });
+    }
+}
+
+/// Spi config.
+#[derive(Clone)]
+pub struct Config {
+    /// Frequency in Hertz.
+    pub frequency: u32,
+    /// SPI operating mode.
+    pub mode: Mode,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            frequency: 1_000_000,
+            mode: MODE_0,
+        }
+    }
+}
+
+struct Info {
+    regs: &'static crate::pac::spi0::RegisterBlock,
+    waker: &'static AtomicWaker,
+}
+
+// SAFETY: safety for Send here is the same as the other accessors to
+// unsafe blocks: it must be done from a single executor context.
+//
+// This is a temporary workaround -- a better solution might be to
+// refactor Info to no longer maintain a reference to regs, but
+// instead look up the correct register set and then perform
+// operations within an unsafe block as we do for other peripherals
+unsafe impl Send for Info {}
+
+trait SealedInstance {
+    fn info() -> Info;
+}
+
+/// Spi interrupt handler.
+pub struct InterruptHandler<T: Instance> {
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        let waker = T::info().waker;
+        let stat = T::info().regs.fifointstat().read();
+
+        if stat.perint().bit_is_set() {
+            T::info().regs.intenclr().write(|w| w.mstidle().clear_bit_by_one());
+        }
+
+        if stat.txlvl().bit_is_set() {
+            T::info().regs.fifointenclr().write(|w| w.txlvl().set_bit());
+        }
+
+        if stat.txerr().bit_is_set() {
+            T::info().regs.fifointenclr().write(|w| w.txerr().set_bit());
+        }
+
+        if stat.rxlvl().bit_is_set() {
+            T::info().regs.fifointenclr().write(|w| w.rxlvl().set_bit());
+        }
+
+        if stat.rxerr().bit_is_set() {
+            T::info().regs.fifointenclr().write(|w| w.rxerr().set_bit());
+        }
+
+        waker.wake();
+    }
+}
+
+/// Spi instance trait.
+#[allow(private_bounds)]
+pub trait Instance: crate::flexcomm::IntoSpi + SealedInstance + PeripheralType + 'static + Send {
+    /// Interrupt for this Spi instance.
+    type Interrupt: interrupt::typelevel::Interrupt;
+}
+
+macro_rules! impl_instance {
+    ($($n:expr),*) => {
+        $(
+            paste!{
+                impl SealedInstance for crate::peripherals::[<FLEXCOMM $n>] {
+                    #[inline]
+                    fn info() -> Info {
+                        static WAKER: AtomicWaker = AtomicWaker::new();
+
+                        Info {
+                            regs: unsafe { &*crate::pac::[<Spi $n>]::ptr() },
+                            waker: &WAKER,
+                        }
+                    }
+                }
+
+                impl Instance for crate::peripherals::[<FLEXCOMM $n>] {
+                    type Interrupt = crate::interrupt::typelevel::[<FLEXCOMM $n>];
+                }
+            }
+        )*
+    }
+}
+
+impl_instance!(0, 1, 2, 3, 4, 5, 6, 7, 14);
+
+mod sealed {
+    /// Seal a trait
+    pub trait Sealed {}
+}
+
+impl<T: Pin> sealed::Sealed for T {}
+
+/// IO configuration trait for Spi clk
+pub trait SckPin<T: Instance>: Pin + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Spi clk usage.
+    fn as_sck(&self);
+}
+
+/// IO configuration trait for Spi mosi
+pub trait MosiPin<T: Instance>: Pin + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Spi mosi usage.
+    fn as_mosi(&self);
+}
+
+/// IO configuration trait for Spi miso
+pub trait MisoPin<T: Instance>: Pin + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Spi miso usage.
+    fn as_miso(&self);
+}
+
+macro_rules! impl_pin_trait {
+    ($fcn:ident, $mode:ident, $($pin:ident, $fn:ident),*) => {
+        paste! {
+            $(
+                impl [<$mode:camel Pin>]<crate::peripherals::$fcn> for crate::peripherals::$pin {
+                    fn [<as_ $mode>](&self) {
+                        // UM11147 table 530 pg 518
+                        self.set_function(crate::iopctl::Function::$fn)
+                            .set_pull(Pull::None)
+                            .enable_input_buffer()
+                            .set_slew_rate(SlewRate::Standard)
+                            .set_drive_strength(DriveStrength::Normal)
+                            .disable_analog_multiplex()
+                            .set_drive_mode(DriveMode::PushPull)
+                            .set_input_inverter(Inverter::Disabled);
+                    }
+                }
+            )*
+        }
+    }
+}
+
+// FLEXCOMM0
+impl_pin_trait!(FLEXCOMM0, sck, PIO0_0, F1, PIO3_0, F5);
+impl_pin_trait!(FLEXCOMM0, miso, PIO0_1, F1, PIO3_1, F5);
+impl_pin_trait!(FLEXCOMM0, mosi, PIO0_2, F1, PIO3_2, F5);
+
+// FLEXCOMM1
+impl_pin_trait!(FLEXCOMM1, sck, PIO0_7, F1, PIO7_25, F1);
+impl_pin_trait!(FLEXCOMM1, miso, PIO0_8, F1, PIO7_26, F1);
+impl_pin_trait!(FLEXCOMM1, mosi, PIO0_9, F1, PIO7_28, F1);
+
+// FLEXCOMM2
+impl_pin_trait!(FLEXCOMM2, sck, PIO0_14, F1, PIO7_29, F5);
+impl_pin_trait!(FLEXCOMM2, miso, PIO0_15, F1, PIO7_30, F5);
+impl_pin_trait!(FLEXCOMM2, mosi, PIO0_16, F1, PIO7_31, F5);
+
+// FLEXCOMM3
+impl_pin_trait!(FLEXCOMM3, sck, PIO0_21, F1);
+impl_pin_trait!(FLEXCOMM3, miso, PIO0_22, F1);
+impl_pin_trait!(FLEXCOMM3, mosi, PIO0_23, F1);
+
+// FLEXCOMM4
+impl_pin_trait!(FLEXCOMM4, sck, PIO0_28, F1);
+impl_pin_trait!(FLEXCOMM4, miso, PIO0_29, F1);
+impl_pin_trait!(FLEXCOMM4, mosi, PIO0_30, F1);
+
+// FLEXCOMM5
+impl_pin_trait!(FLEXCOMM5, sck, PIO1_3, F1, PIO3_15, F5);
+impl_pin_trait!(FLEXCOMM5, miso, PIO1_4, F1, PIO3_16, F5);
+impl_pin_trait!(FLEXCOMM5, mosi, PIO1_5, F1, PIO3_17, F5);
+
+// FLEXCOMM6
+impl_pin_trait!(FLEXCOMM6, sck, PIO3_25, F1);
+impl_pin_trait!(FLEXCOMM6, miso, PIO3_26, F1);
+impl_pin_trait!(FLEXCOMM6, mosi, PIO3_27, F1);
+
+// FLEXCOMM7
+impl_pin_trait!(FLEXCOMM7, sck, PIO4_0, F1);
+impl_pin_trait!(FLEXCOMM7, miso, PIO4_1, F1);
+impl_pin_trait!(FLEXCOMM7, mosi, PIO4_2, F1);
+
+// FLEXCOMM14
+impl_pin_trait!(FLEXCOMM14, sck, PIO1_11, F1);
+impl_pin_trait!(FLEXCOMM14, miso, PIO1_12, F1);
+impl_pin_trait!(FLEXCOMM14, mosi, PIO1_13, F1);
+
+/// Spi Tx DMA trait.
+#[allow(private_bounds)]
+pub trait TxDma<T: Instance>: crate::dma::Channel {}
+
+/// Spi Rx DMA trait.
+#[allow(private_bounds)]
+pub trait RxDma<T: Instance>: crate::dma::Channel {}
+
+macro_rules! impl_dma {
+    ($fcn:ident, $mode:ident, $dma:ident) => {
+        paste! {
+            impl [<$mode Dma>]<crate::peripherals::$fcn> for crate::peripherals::$dma {}
+        }
+    };
+}
+
+impl_dma!(FLEXCOMM0, Rx, DMA0_CH0);
+impl_dma!(FLEXCOMM0, Tx, DMA0_CH1);
+
+impl_dma!(FLEXCOMM1, Rx, DMA0_CH2);
+impl_dma!(FLEXCOMM1, Tx, DMA0_CH3);
+
+impl_dma!(FLEXCOMM2, Rx, DMA0_CH4);
+impl_dma!(FLEXCOMM2, Tx, DMA0_CH5);
+
+impl_dma!(FLEXCOMM3, Rx, DMA0_CH6);
+impl_dma!(FLEXCOMM3, Tx, DMA0_CH7);
+
+impl_dma!(FLEXCOMM4, Rx, DMA0_CH8);
+impl_dma!(FLEXCOMM4, Tx, DMA0_CH9);
+
+impl_dma!(FLEXCOMM5, Rx, DMA0_CH10);
+impl_dma!(FLEXCOMM5, Tx, DMA0_CH11);
+
+impl_dma!(FLEXCOMM6, Rx, DMA0_CH12);
+impl_dma!(FLEXCOMM6, Tx, DMA0_CH13);
+
+impl_dma!(FLEXCOMM7, Rx, DMA0_CH14);
+impl_dma!(FLEXCOMM7, Tx, DMA0_CH15);
+
+impl_dma!(FLEXCOMM14, Rx, DMA0_CH16);
+impl_dma!(FLEXCOMM14, Tx, DMA0_CH17);
+
+// ==============================
+
+impl<'d, M: IoMode> embedded_hal_02::blocking::spi::Transfer<u8> for Spi<'d, M> {
+    type Error = Error;
+    fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
+        self.blocking_transfer_in_place(words)?;
+        Ok(words)
+    }
+}
+
+impl<'d, M: IoMode> embedded_hal_02::blocking::spi::Write<u8> for Spi<'d, M> {
+    type Error = Error;
+
+    fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_write(words)
+    }
+}
+
+impl embedded_hal_1::spi::Error for Error {
+    fn kind(&self) -> embedded_hal_1::spi::ErrorKind {
+        match *self {}
+    }
+}
+
+impl<'d, M: IoMode> embedded_hal_1::spi::ErrorType for Spi<'d, M> {
+    type Error = Error;
+}
+
+impl<'d, M: IoMode> embedded_hal_1::spi::SpiBus<u8> for Spi<'d, M> {
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        self.flush()
+    }
+
+    fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.blocking_read(words)
+    }
+
+    fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_write(words)
+    }
+
+    fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_transfer(read, write)
+    }
+
+    fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.blocking_transfer_in_place(words)
+    }
+}
+
+impl<'d> embedded_hal_async::spi::SpiBus<u8> for Spi<'d, Async> {
+    async fn flush(&mut self) -> Result<(), Self::Error> {
+        self.async_flush().await;
+
+        Ok(())
+    }
+
+    async fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+        self.async_write(words).await
+    }
+
+    async fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.async_read(words).await
+    }
+
+    async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
+        self.async_transfer(read, write).await
+    }
+
+    async fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.async_transfer_in_place(words).await
+    }
+}
+
+impl<'d, M: IoMode> SetConfig for Spi<'d, M> {
+    type Config = Config;
+    type ConfigError = ();
+    fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
+        self.set_config(config);
+
+        Ok(())
+    }
+}
diff --git a/embassy-imxrt/src/flexcomm/uart.rs b/embassy-imxrt/src/flexcomm/uart.rs
index 2b759ba84..d13b32e93 100644
--- a/embassy-imxrt/src/flexcomm/uart.rs
+++ b/embassy-imxrt/src/flexcomm/uart.rs
@@ -598,7 +598,7 @@ impl<'a> UartTx<'a, Async> {
             regs.fifocfg().modify(|_, w| w.dmatx().disabled());
         });
 
-        for chunk in buf.chunks(1024) {
+        for chunk in buf.chunks(dma::MAX_CHUNK_SIZE) {
             regs.fifocfg().modify(|_, w| w.dmatx().enabled());
 
             let ch = self.tx_dma.as_mut().unwrap().reborrow();
@@ -726,7 +726,7 @@ impl<'a> UartRx<'a, Async> {
             regs.fifocfg().modify(|_, w| w.dmarx().disabled());
         });
 
-        for chunk in buf.chunks_mut(1024) {
+        for chunk in buf.chunks_mut(dma::MAX_CHUNK_SIZE) {
             regs.fifocfg().modify(|_, w| w.dmarx().enabled());
 
             let ch = self.rx_dma.as_mut().unwrap().reborrow();
diff --git a/embassy-mcxa/Cargo.toml b/embassy-mcxa/Cargo.toml
index cb985a2e9..76ce59f5a 100644
--- a/embassy-mcxa/Cargo.toml
+++ b/embassy-mcxa/Cargo.toml
@@ -39,7 +39,7 @@ embedded-hal-nb = { version = "1.0" }
 embedded-io = "0.6"
 embedded-io-async = { version = "0.6.1" }
 heapless = "0.8"
-mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt", "critical-section"], version = "0.1.0", rev = "02bd04a21ef8f8f67f88239ff5df765bb7e60fd8" }
+mcxa-pac = { version = "0.1.0", features = ["rt", "critical-section"] }
 nb = "1.1.0"
 paste = "1.0.15"
 maitake-sync = { version = "0.2.2", default-features = false, features = ["critical-section", "no-cache-pad"] }
@@ -48,6 +48,9 @@ maitake-sync = { version = "0.2.2", default-features = false, features = ["criti
 embassy-time = { version = "0.5.0", optional = true }
 embassy-time-driver = { version = "0.2.1", optional = true }
 
+rand-core-06 = { package = "rand_core", version = "0.6" }
+rand-core-09 = { package = "rand_core", version = "0.9" }
+
 [features]
 default = ["rt"]
 
diff --git a/embassy-mcxa/src/clocks/mod.rs b/embassy-mcxa/src/clocks/mod.rs
index ceb1e2a50..b41a1ba46 100644
--- a/embassy-mcxa/src/clocks/mod.rs
+++ b/embassy-mcxa/src/clocks/mod.rs
@@ -1076,4 +1076,6 @@ pub(crate) mod gate {
 
     // DMA0 peripheral - uses NoConfig since it has no selectable clock source
     impl_cc_gate!(DMA0, mrcc_glb_cc0, mrcc_glb_rst0, dma0, NoConfig);
+    // TRNG peripheral - uses NoConfig since it has no selectable clock source
+    impl_cc_gate!(TRNG0, mrcc_glb_cc1, mrcc_glb_rst1, trng0, NoConfig);
 }
diff --git a/embassy-mcxa/src/interrupt.rs b/embassy-mcxa/src/interrupt.rs
index 725f8d499..b662f7ee0 100644
--- a/embassy-mcxa/src/interrupt.rs
+++ b/embassy-mcxa/src/interrupt.rs
@@ -38,6 +38,7 @@ mod generated {
         LPUART5,
         OS_EVENT,
         RTC,
+        TRNG0
     );
 }
 
diff --git a/embassy-mcxa/src/lib.rs b/embassy-mcxa/src/lib.rs
index 8d39728a7..76fd58210 100644
--- a/embassy-mcxa/src/lib.rs
+++ b/embassy-mcxa/src/lib.rs
@@ -19,6 +19,7 @@ pub mod lpuart;
 pub mod ostimer;
 pub mod reset_reason;
 pub mod rtc;
+pub mod trng;
 
 use crate::interrupt::InterruptExt;
 pub use crate::pac::NVIC_PRIO_BITS;
diff --git a/embassy-mcxa/src/trng.rs b/embassy-mcxa/src/trng.rs
new file mode 100644
index 000000000..ce37e4b2a
--- /dev/null
+++ b/embassy-mcxa/src/trng.rs
@@ -0,0 +1,678 @@
+//! True Random Number Generator
+
+use core::marker::PhantomData;
+
+use embassy_hal_internal::Peri;
+use embassy_hal_internal::interrupt::InterruptExt;
+use maitake_sync::WaitCell;
+use mcxa_pac::trng0::osc2_ctl::TrngEntCtl;
+
+use crate::clocks::enable_and_reset;
+use crate::clocks::periph_helpers::NoConfig;
+use crate::interrupt::typelevel;
+use crate::interrupt::typelevel::Handler;
+use crate::peripherals::TRNG0;
+
+static WAIT_CELL: WaitCell = WaitCell::new();
+
+#[allow(private_bounds)]
+pub trait Mode: sealed::SealedMode {}
+
+mod sealed {
+    pub trait SealedMode {}
+}
+
+macro_rules! define_mode {
+    ($mode:ident) => {
+        pub struct $mode;
+        impl sealed::SealedMode for $mode {}
+        impl Mode for $mode {}
+    };
+}
+
+define_mode!(Blocking);
+define_mode!(Async);
+
+/// TRNG Driver
+pub struct Trng<'d, M: Mode> {
+    _peri: Peri<'d, TRNG0>,
+    _phantom: PhantomData<M>,
+}
+
+impl<'d, M: Mode> Trng<'d, M> {
+    fn new_inner(_peri: Peri<'d, TRNG0>, config: Config) -> Self {
+        _ = unsafe { enable_and_reset::<TRNG0>(&NoConfig) };
+
+        Self::configure(config);
+        Self {
+            _peri,
+            _phantom: PhantomData,
+        }
+    }
+
+    fn configure(config: Config) {
+        regs()
+            .mctl()
+            .modify(|_, w| w.rst_def().set_bit().prgm().enable().err().clear_bit_by_one());
+
+        regs().scml().write(|w| unsafe {
+            w.mono_max()
+                .bits(config.monobit_limit_max)
+                .mono_rng()
+                .bits(config.monobit_limit_range)
+        });
+
+        regs().scr1l().write(|w| unsafe {
+            w.run1_max()
+                .bits(config.run_length1_limit_max)
+                .run1_rng()
+                .bits(config.run_length1_limit_range)
+        });
+
+        regs().scr2l().write(|w| unsafe {
+            w.run2_max()
+                .bits(config.run_length2_limit_max)
+                .run2_rng()
+                .bits(config.run_length2_limit_range)
+        });
+
+        regs().scr3l().write(|w| unsafe {
+            w.run3_max()
+                .bits(config.run_length3_limit_max)
+                .run3_rng()
+                .bits(config.run_length3_limit_range)
+        });
+
+        regs().scr4l().write(|w| unsafe {
+            w.run4_max()
+                .bits(config.run_length4_limit_max)
+                .run4_rng()
+                .bits(config.run_length4_limit_range)
+        });
+
+        regs().scr5l().write(|w| unsafe {
+            w.run5_max()
+                .bits(config.run_length5_limit_max)
+                .run5_rng()
+                .bits(config.run_length5_limit_range)
+        });
+
+        regs().scr6pl().write(|w| unsafe {
+            w.run6p_max()
+                .bits(config.run_length6_limit_max)
+                .run6p_rng()
+                .bits(config.run_length6_limit_range)
+        });
+
+        regs()
+            .pkrmax()
+            .write(|w| unsafe { w.pkr_max().bits(config.poker_limit_max) });
+
+        regs()
+            .frqmax()
+            .write(|w| unsafe { w.frq_max().bits(config.freq_counter_max) });
+
+        regs()
+            .frqmin()
+            .write(|w| unsafe { w.frq_min().bits(config.freq_counter_min) });
+
+        regs()
+            .sblim()
+            .write(|w| unsafe { w.sb_lim().bits(config.sparse_bit_limit) });
+
+        regs().scmisc().write(|w| unsafe {
+            w.lrun_max()
+                .bits(config.long_run_limit_max)
+                .rty_ct()
+                .bits(config.retry_count)
+        });
+
+        regs()
+            .mctl()
+            .modify(|_, w| w.dis_slf_tst().variant(config.self_test.into()));
+
+        regs().sdctl().write(|w| unsafe {
+            w.samp_size()
+                .bits(config.sample_size)
+                .ent_dly()
+                .bits(config.entropy_delay)
+        });
+
+        regs()
+            .osc2_ctl()
+            .modify(|_, w| w.trng_ent_ctl().variant(config.osc_mode.into()));
+
+        regs().mctl().modify(|_, w| w.prgm().disable());
+
+        let _ = regs().ent(7).read().bits();
+
+        Self::start();
+    }
+
+    fn start() {
+        regs().mctl().modify(|_, w| w.trng_acc().set_bit());
+    }
+
+    fn stop() {
+        regs().mctl().modify(|_, w| w.trng_acc().clear_bit());
+    }
+
+    fn blocking_wait_for_generation() {
+        while regs().mctl().read().ent_val().bit_is_clear() {
+            if regs().mctl().read().err().bit_is_set() {
+                regs().mctl().modify(|_, w| w.err().clear_bit_by_one());
+            }
+        }
+    }
+
+    fn fill_chunk(chunk: &mut [u8]) {
+        let mut entropy = [0u32; 8];
+
+        for (i, item) in entropy.iter_mut().enumerate() {
+            *item = regs().ent(i).read().bits();
+        }
+
+        let entropy: [u8; 32] = unsafe { core::mem::transmute(entropy) };
+
+        chunk.copy_from_slice(&entropy[..chunk.len()]);
+    }
+
+    // Blocking API
+
+    /// Fill the buffer with random bytes, blocking version.
+    pub fn blocking_fill_bytes(&mut self, buf: &mut [u8]) {
+        if buf.is_empty() {
+            return; // nothing to fill
+        }
+
+        for chunk in buf.chunks_mut(32) {
+            Self::blocking_wait_for_generation();
+            Self::fill_chunk(chunk);
+        }
+    }
+
+    /// Return a random u32, blocking version.
+    pub fn blocking_next_u32(&mut self) -> u32 {
+        Self::blocking_wait_for_generation();
+        // New random bytes are generated only after reading ENT7
+        regs().ent(7).read().bits()
+    }
+
+    /// Return a random u64, blocking version.
+    pub fn blocking_next_u64(&mut self) -> u64 {
+        Self::blocking_wait_for_generation();
+
+        let mut result = u64::from(regs().ent(6).read().bits()) << 32;
+        // New random bytes are generated only after reading ENT7
+        result |= u64::from(regs().ent(7).read().bits());
+        result
+    }
+}
+
+impl<'d> Trng<'d, Blocking> {
+    /// Instantiates a new TRNG peripheral driver with 128 samples of entropy.
+    pub fn new_blocking_128(_peri: Peri<'d, TRNG0>) -> Self {
+        Self::new_inner(
+            _peri,
+            Config {
+                sample_size: 128,
+                retry_count: 1,
+                long_run_limit_max: 29,
+                monobit_limit_max: 94,
+                monobit_limit_range: 61,
+                run_length1_limit_max: 39,
+                run_length1_limit_range: 39,
+                run_length2_limit_max: 24,
+                run_length2_limit_range: 25,
+                run_length3_limit_max: 17,
+                run_length3_limit_range: 18,
+                ..Default::default()
+            },
+        )
+    }
+
+    /// Instantiates a new TRNG peripheral driver with  256 samples of entropy.
+    pub fn new_blocking_256(_peri: Peri<'d, TRNG0>) -> Self {
+        Self::new_inner(
+            _peri,
+            Config {
+                sample_size: 256,
+                retry_count: 1,
+                long_run_limit_max: 31,
+                monobit_limit_max: 171,
+                monobit_limit_range: 86,
+                run_length1_limit_max: 63,
+                run_length1_limit_range: 56,
+                run_length2_limit_max: 38,
+                run_length2_limit_range: 38,
+                run_length3_limit_max: 25,
+                run_length3_limit_range: 26,
+                ..Default::default()
+            },
+        )
+    }
+
+    /// Instantiates a new TRNG peripheral driver with 512 samples of entropy.
+    pub fn new_blocking_512(_peri: Peri<'d, TRNG0>) -> Self {
+        Self::new_inner(_peri, Default::default())
+    }
+
+    /// Instantiates a new TRNG peripheral driver.
+    ///
+    /// NOTE: this constructor makes no attempt at validating the
+    /// parameters. If you get this wrong, the security guarantees of
+    /// the TRNG with regards to entropy may be violated
+    pub fn new_blocking_with_custom_config(_peri: Peri<'d, TRNG0>, config: Config) -> Self {
+        Self::new_inner(_peri, config)
+    }
+}
+
+impl<'d> Trng<'d, Async> {
+    /// Instantiates a new TRNG peripheral driver with 128 samples of entropy.
+    pub fn new_128(
+        _peri: Peri<'d, TRNG0>,
+        _irq: impl crate::interrupt::typelevel::Binding<typelevel::TRNG0, InterruptHandler> + 'd,
+    ) -> Self {
+        let inst = Self::new_inner(
+            _peri,
+            Config {
+                sample_size: 128,
+                retry_count: 1,
+                long_run_limit_max: 29,
+                monobit_limit_max: 94,
+                monobit_limit_range: 61,
+                run_length1_limit_max: 39,
+                run_length1_limit_range: 39,
+                run_length2_limit_max: 24,
+                run_length2_limit_range: 25,
+                run_length3_limit_max: 17,
+                run_length3_limit_range: 18,
+                ..Default::default()
+            },
+        );
+        crate::pac::Interrupt::TRNG0.unpend();
+        unsafe {
+            crate::pac::Interrupt::TRNG0.enable();
+        }
+        inst
+    }
+
+    /// Instantiates a new TRNG peripheral driver with 256 samples of entropy.
+    pub fn new_256(
+        _peri: Peri<'d, TRNG0>,
+        _irq: impl crate::interrupt::typelevel::Binding<typelevel::TRNG0, InterruptHandler> + 'd,
+    ) -> Self {
+        let inst = Self::new_inner(
+            _peri,
+            Config {
+                sample_size: 256,
+                retry_count: 1,
+                long_run_limit_max: 31,
+                monobit_limit_max: 171,
+                monobit_limit_range: 86,
+                run_length1_limit_max: 63,
+                run_length1_limit_range: 56,
+                run_length2_limit_max: 38,
+                run_length2_limit_range: 38,
+                run_length3_limit_max: 25,
+                run_length3_limit_range: 26,
+                ..Default::default()
+            },
+        );
+        crate::pac::Interrupt::TRNG0.unpend();
+        unsafe {
+            crate::pac::Interrupt::TRNG0.enable();
+        }
+        inst
+    }
+
+    /// Instantiates a new TRNG peripheral driver with 512 samples of entropy.
+    pub fn new_512(
+        _peri: Peri<'d, TRNG0>,
+        _irq: impl crate::interrupt::typelevel::Binding<typelevel::TRNG0, InterruptHandler> + 'd,
+    ) -> Self {
+        let inst = Self::new_inner(_peri, Default::default());
+        crate::pac::Interrupt::TRNG0.unpend();
+        unsafe {
+            crate::pac::Interrupt::TRNG0.enable();
+        }
+        inst
+    }
+
+    /// Instantiates a new TRNG peripheral driver.
+    ///
+    /// NOTE: this constructor makes no attempt at validating the
+    /// parameters. If you get this wrong, the security guarantees of
+    /// the TRNG with regards to entropy may be violated
+    pub fn new_with_custom_config(
+        _peri: Peri<'d, TRNG0>,
+        _irq: impl crate::interrupt::typelevel::Binding<typelevel::TRNG0, InterruptHandler> + 'd,
+        config: Config,
+    ) -> Self {
+        let inst = Self::new_inner(_peri, config);
+        crate::pac::Interrupt::TRNG0.unpend();
+        unsafe {
+            crate::pac::Interrupt::TRNG0.enable();
+        }
+        inst
+    }
+
+    fn enable_ints() {
+        regs().int_mask().write(|w| {
+            w.hw_err()
+                .set_bit()
+                .ent_val()
+                .set_bit()
+                .frq_ct_fail()
+                .set_bit()
+                .intg_flt()
+                .set_bit()
+        });
+    }
+
+    async fn wait_for_generation() -> Result<(), Error> {
+        WAIT_CELL
+            .wait_for(|| {
+                Self::enable_ints();
+                regs().mctl().read().ent_val().bit_is_set()
+            })
+            .await
+            .map_err(|_| Error::ErrorStatus)
+    }
+
+    // Async API
+
+    /// Fill the buffer with random bytes, async version.
+    pub async fn async_fill_bytes(&mut self, buf: &mut [u8]) -> Result<(), Error> {
+        if buf.is_empty() {
+            return Ok(()); // nothing to fill
+        }
+
+        for chunk in buf.chunks_mut(32) {
+            Self::wait_for_generation().await?;
+            Self::fill_chunk(chunk);
+        }
+
+        Ok(())
+    }
+
+    /// Return a random u32, async version.
+    pub async fn async_next_u32(&mut self) -> Result<u32, Error> {
+        Self::wait_for_generation().await?;
+        // New random bytes are generated only after reading ENT7
+        Ok(regs().ent(7).read().bits())
+    }
+
+    /// Return a random u64, async version.
+    pub async fn async_next_u64(&mut self) -> Result<u64, Error> {
+        Self::wait_for_generation().await?;
+
+        let mut result = u64::from(regs().ent(6).read().bits()) << 32;
+        // New random bytes are generated only after reading ENT7
+        result |= u64::from(regs().ent(7).read().bits());
+
+        Ok(result)
+    }
+}
+
+impl<M: Mode> Drop for Trng<'_, M> {
+    fn drop(&mut self) {
+        // wait until allowed to stop
+        while regs().mctl().read().tstop_ok().bit_is_clear() {}
+        // stop
+        Self::stop();
+        // reset the TRNG
+        regs().mctl().write(|w| w.rst_def().set_bit());
+    }
+}
+
+fn regs() -> &'static crate::pac::trng0::RegisterBlock {
+    unsafe { &*crate::pac::Trng0::ptr() }
+}
+
+/// Trng errors
+#[derive(Clone, Copy, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+    /// Integrity error.
+    IntegrityError,
+
+    /// Frequency counter fail
+    FrequencyCountFail,
+
+    /// Error status
+    ErrorStatus,
+
+    /// Buffer argument is invalid
+    InvalidBuffer,
+}
+
+/// TRNG interrupt handler.
+pub struct InterruptHandler;
+
+impl Handler<typelevel::TRNG0> for InterruptHandler {
+    unsafe fn on_interrupt() {
+        if regs().int_status().read().bits() != 0 {
+            regs().int_ctrl().write(|w| {
+                w.hw_err()
+                    .clear_bit()
+                    .ent_val()
+                    .clear_bit()
+                    .frq_ct_fail()
+                    .clear_bit()
+                    .intg_flt()
+                    .clear_bit()
+            });
+            WAIT_CELL.wake();
+        }
+    }
+}
+
+/// True random number generator configuration parameters.
+#[derive(Clone, Copy, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub struct Config {
+    /// Total number of Entropy samples that will be taken during
+    /// Entropy generation.
+    pub sample_size: u16,
+
+    /// Length (in system clocks) of each Entropy sample taken.
+    pub entropy_delay: u16,
+
+    /// Enable or disable internal self-tests.
+    pub self_test: SelfTest,
+
+    /// Frequency Counter Maximum Limit
+    pub freq_counter_max: u32,
+
+    /// Frequency Counter Minimum Limit
+    pub freq_counter_min: u32,
+
+    /// Statistical check monobit max limit
+    pub monobit_limit_max: u16,
+
+    /// Statistical check monobit range
+    pub monobit_limit_range: u16,
+
+    /// Statistical check run length 1 limit max
+    pub run_length1_limit_max: u16,
+
+    /// Statistical check run length 1 limit range
+    pub run_length1_limit_range: u16,
+
+    /// Statistical check run length 2 limit max
+    pub run_length2_limit_max: u16,
+
+    /// Statistical check run length 2 limit range
+    pub run_length2_limit_range: u16,
+
+    /// Statistical check run length 3 limit max
+    pub run_length3_limit_max: u16,
+
+    /// Statistical check run length 3 limit range
+    pub run_length3_limit_range: u16,
+
+    /// Statistical check run length 4 limit max
+    pub run_length4_limit_max: u16,
+
+    /// Statistical check run length 4 limit range
+    pub run_length4_limit_range: u16,
+
+    /// Statistical check run length 5 limit max
+    pub run_length5_limit_max: u16,
+
+    /// Statistical check run length 5 limit range
+    pub run_length5_limit_range: u16,
+
+    /// Statistical check run length 6 limit max
+    pub run_length6_limit_max: u16,
+
+    /// Statistical check run length 6 limit range
+    pub run_length6_limit_range: u16,
+
+    /// Retry count
+    pub retry_count: u8,
+
+    /// Long run limit max
+    pub long_run_limit_max: u8,
+
+    /// Sparse bit limit
+    pub sparse_bit_limit: u16,
+
+    /// Poker limit max
+    pub poker_limit_max: u32,
+
+    /// Oscillator mode
+    pub osc_mode: OscMode,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            sample_size: 512,
+            entropy_delay: 32_000,
+            self_test: SelfTest::Enabled,
+            freq_counter_max: 75_000,
+            freq_counter_min: 30_000,
+            monobit_limit_max: 317,
+            monobit_limit_range: 122,
+            run_length1_limit_max: 107,
+            run_length1_limit_range: 80,
+            run_length2_limit_max: 62,
+            run_length2_limit_range: 55,
+            run_length3_limit_max: 39,
+            run_length3_limit_range: 39,
+            run_length4_limit_max: 0,
+            run_length4_limit_range: 0,
+            run_length5_limit_max: 0,
+            run_length5_limit_range: 0,
+            run_length6_limit_max: 0,
+            run_length6_limit_range: 0,
+            retry_count: 1,
+            long_run_limit_max: 32,
+            sparse_bit_limit: 0,
+            poker_limit_max: 0,
+            osc_mode: OscMode::DualOscs,
+        }
+    }
+}
+
+/// Sample size.
+#[derive(Clone, Copy, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum SampleSize {
+    /// 128 bits
+    _128,
+
+    /// 256 bits
+    _256,
+
+    /// 512 bits
+    _512,
+}
+
+/// Enable or disable internal self-tests.
+#[derive(Clone, Copy, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum SelfTest {
+    /// Disabled.
+    Disabled,
+
+    /// Enabled.
+    Enabled,
+}
+
+impl From<SelfTest> for bool {
+    fn from(value: SelfTest) -> Self {
+        match value {
+            SelfTest::Disabled => true,
+            SelfTest::Enabled => false,
+        }
+    }
+}
+
+/// Oscillator mode.
+#[derive(Clone, Copy, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum OscMode {
+    /// Single oscillator using OSC1.
+    SingleOsc1,
+
+    /// Dual oscillator.
+    DualOscs,
+
+    /// Single oscillator using OSC2.
+    SingleOsc2,
+}
+
+impl From<OscMode> for TrngEntCtl {
+    fn from(value: OscMode) -> Self {
+        match value {
+            OscMode::SingleOsc1 => Self::TrngEntCtlSingleOsc1,
+            OscMode::DualOscs => Self::TrngEntCtlDualOscs,
+            OscMode::SingleOsc2 => Self::TrngEntCtlSingleOsc2,
+        }
+    }
+}
+
+impl<'d, M: Mode> rand_core_06::RngCore for Trng<'d, M> {
+    fn next_u32(&mut self) -> u32 {
+        self.blocking_next_u32()
+    }
+
+    fn next_u64(&mut self) -> u64 {
+        self.blocking_next_u64()
+    }
+
+    fn fill_bytes(&mut self, dest: &mut [u8]) {
+        self.blocking_fill_bytes(dest);
+    }
+
+    fn try_fill_bytes(&mut self, dest: &mut [u8]) -> Result<(), rand_core_06::Error> {
+        self.blocking_fill_bytes(dest);
+        Ok(())
+    }
+}
+
+impl<'d, M: Mode> rand_core_06::CryptoRng for Trng<'d, M> {}
+
+impl<'d, M: Mode> rand_core_09::RngCore for Trng<'d, M> {
+    fn next_u32(&mut self) -> u32 {
+        self.blocking_next_u32()
+    }
+
+    fn next_u64(&mut self) -> u64 {
+        self.blocking_next_u64()
+    }
+
+    fn fill_bytes(&mut self, dest: &mut [u8]) {
+        self.blocking_fill_bytes(dest);
+    }
+}
+
+impl<'d, M: Mode> rand_core_09::CryptoRng for Trng<'d, M> {}
diff --git a/embassy-mspm0/CHANGELOG.md b/embassy-mspm0/CHANGELOG.md
index 6972a8472..19275f35a 100644
--- a/embassy-mspm0/CHANGELOG.md
+++ b/embassy-mspm0/CHANGELOG.md
@@ -19,4 +19,5 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - feat: Add i2c target implementation (#4605)
 - fix: group irq handlers must check for NO_INTR (#4785)
 - feat: Add read_reset_cause function
-- feat: Add module Mathacl & example for mspm0g3507 (#4897)
\ No newline at end of file
+- feat: Add module Mathacl & example for mspm0g3507 (#4897)
+- feat: Add MSPM0G5187 supportt
diff --git a/embassy-mspm0/Cargo.toml b/embassy-mspm0/Cargo.toml
index 254e0209b..cf2346328 100644
--- a/embassy-mspm0/Cargo.toml
+++ b/embassy-mspm0/Cargo.toml
@@ -73,7 +73,7 @@ critical-section = "1.2.0"
 micromath = "2.0.0"
 
 # mspm0-metapac = { version = "" }
-mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-f21b04e9de074af4965bf67ec3646cb9fe1b9852" }
+mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-e91edd86813aa94cbb6737d34e4f1d22b8487cb6" }
 
 [build-dependencies]
 proc-macro2 = "1.0.94"
@@ -81,7 +81,7 @@ quote = "1.0.40"
 cfg_aliases = "0.2.1"
 
 # mspm0-metapac = { version = "", default-features = false, features = ["metadata"] }
-mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-f21b04e9de074af4965bf67ec3646cb9fe1b9852", default-features = false, features = ["metadata"] }
+mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-e91edd86813aa94cbb6737d34e4f1d22b8487cb6", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]
@@ -153,15 +153,14 @@ time-driver-tima1 = ["_time-driver"]
 #!
 #! **Important:** Do not forget to adapt the target chip in your toolchain,
 #! e.g. in `.cargo/config.toml`.
-
 mspm0c1103dgs20 = ["mspm0-metapac/mspm0c1103dgs20"]
-mspm0c1103dsg = ["mspm0-metapac/mspm0c1103dsg"]
-mspm0c1103dyy = ["mspm0-metapac/mspm0c1103dyy"]
 mspm0c1103ruk = ["mspm0-metapac/mspm0c1103ruk"]
+mspm0c1103dyy = ["mspm0-metapac/mspm0c1103dyy"]
+mspm0c1103dsg = ["mspm0-metapac/mspm0c1103dsg"]
 mspm0c1104dgs20 = ["mspm0-metapac/mspm0c1104dgs20"]
-mspm0c1104dsg = ["mspm0-metapac/mspm0c1104dsg"]
-mspm0c1104dyy = ["mspm0-metapac/mspm0c1104dyy"]
 mspm0c1104ruk = ["mspm0-metapac/mspm0c1104ruk"]
+mspm0c1104dyy = ["mspm0-metapac/mspm0c1104dyy"]
+mspm0c1104dsg = ["mspm0-metapac/mspm0c1104dsg"]
 mspm0c1104ycj = ["mspm0-metapac/mspm0c1104ycj"]
 mspm0c1105pt = ["mspm0-metapac/mspm0c1105pt"]
 mspm0c1105rgz = ["mspm0-metapac/mspm0c1105rgz"]
@@ -181,43 +180,54 @@ mspm0c1106rge = ["mspm0-metapac/mspm0c1106rge"]
 mspm0c1106dgs20 = ["mspm0-metapac/mspm0c1106dgs20"]
 mspm0c1106ruk = ["mspm0-metapac/mspm0c1106ruk"]
 mspm0c1106zcm = ["mspm0-metapac/mspm0c1106zcm"]
-mspm0g1105dgs28 = ["mspm0-metapac/mspm0g1105dgs28"]
-mspm0g1105pm = ["mspm0-metapac/mspm0g1105pm"]
-mspm0g1105pt = ["mspm0-metapac/mspm0g1105pt"]
 mspm0g1105rge = ["mspm0-metapac/mspm0g1105rge"]
-mspm0g1105rgz = ["mspm0-metapac/mspm0g1105rgz"]
+mspm0g1105dgs28 = ["mspm0-metapac/mspm0g1105dgs28"]
 mspm0g1105rhb = ["mspm0-metapac/mspm0g1105rhb"]
-mspm0g1106dgs28 = ["mspm0-metapac/mspm0g1106dgs28"]
-mspm0g1106pm = ["mspm0-metapac/mspm0g1106pm"]
-mspm0g1106pt = ["mspm0-metapac/mspm0g1106pt"]
+mspm0g1105rgz = ["mspm0-metapac/mspm0g1105rgz"]
+mspm0g1105pt = ["mspm0-metapac/mspm0g1105pt"]
+mspm0g1105pm = ["mspm0-metapac/mspm0g1105pm"]
 mspm0g1106rge = ["mspm0-metapac/mspm0g1106rge"]
-mspm0g1106rgz = ["mspm0-metapac/mspm0g1106rgz"]
+mspm0g1106dgs28 = ["mspm0-metapac/mspm0g1106dgs28"]
 mspm0g1106rhb = ["mspm0-metapac/mspm0g1106rhb"]
-mspm0g1107dgs28 = ["mspm0-metapac/mspm0g1107dgs28"]
-mspm0g1107pm = ["mspm0-metapac/mspm0g1107pm"]
-mspm0g1107pt = ["mspm0-metapac/mspm0g1107pt"]
+mspm0g1106rgz = ["mspm0-metapac/mspm0g1106rgz"]
+mspm0g1106pt = ["mspm0-metapac/mspm0g1106pt"]
+mspm0g1106pm = ["mspm0-metapac/mspm0g1106pm"]
 mspm0g1107rge = ["mspm0-metapac/mspm0g1107rge"]
-mspm0g1107rgz = ["mspm0-metapac/mspm0g1107rgz"]
+mspm0g1107dgs28 = ["mspm0-metapac/mspm0g1107dgs28"]
 mspm0g1107rhb = ["mspm0-metapac/mspm0g1107rhb"]
+mspm0g1107rgz = ["mspm0-metapac/mspm0g1107rgz"]
+mspm0g1107pt = ["mspm0-metapac/mspm0g1107pt"]
+mspm0g1107pm = ["mspm0-metapac/mspm0g1107pm"]
 mspm0g1107ycj = ["mspm0-metapac/mspm0g1107ycj"]
-mspm0g1505pm = ["mspm0-metapac/mspm0g1505pm"]
-mspm0g1505pt = ["mspm0-metapac/mspm0g1505pt"]
 mspm0g1505rge = ["mspm0-metapac/mspm0g1505rge"]
-mspm0g1505rgz = ["mspm0-metapac/mspm0g1505rgz"]
 mspm0g1505rhb = ["mspm0-metapac/mspm0g1505rhb"]
-mspm0g1506pm = ["mspm0-metapac/mspm0g1506pm"]
-mspm0g1506pt = ["mspm0-metapac/mspm0g1506pt"]
+mspm0g1505rgz = ["mspm0-metapac/mspm0g1505rgz"]
+mspm0g1505pt = ["mspm0-metapac/mspm0g1505pt"]
+mspm0g1505pm = ["mspm0-metapac/mspm0g1505pm"]
 mspm0g1506rge = ["mspm0-metapac/mspm0g1506rge"]
-mspm0g1506rgz = ["mspm0-metapac/mspm0g1506rgz"]
 mspm0g1506rhb = ["mspm0-metapac/mspm0g1506rhb"]
-mspm0g1507pm = ["mspm0-metapac/mspm0g1507pm"]
-mspm0g1507pt = ["mspm0-metapac/mspm0g1507pt"]
+mspm0g1506rgz = ["mspm0-metapac/mspm0g1506rgz"]
+mspm0g1506pt = ["mspm0-metapac/mspm0g1506pt"]
+mspm0g1506pm = ["mspm0-metapac/mspm0g1506pm"]
 mspm0g1507rge = ["mspm0-metapac/mspm0g1507rge"]
-mspm0g1507rgz = ["mspm0-metapac/mspm0g1507rgz"]
 mspm0g1507rhb = ["mspm0-metapac/mspm0g1507rhb"]
+mspm0g1507rgz = ["mspm0-metapac/mspm0g1507rgz"]
+mspm0g1507pt = ["mspm0-metapac/mspm0g1507pt"]
+mspm0g1507pm = ["mspm0-metapac/mspm0g1507pm"]
 mspm0g1507ycj = ["mspm0-metapac/mspm0g1507ycj"]
-mspm0g1519rgz = ["mspm0-metapac/mspm0g1519rgz"]
+mspm0g1518rhb = ["mspm0-metapac/mspm0g1518rhb"]
+mspm0g1518rgz = ["mspm0-metapac/mspm0g1518rgz"]
+mspm0g1518pt = ["mspm0-metapac/mspm0g1518pt"]
+mspm0g1518pm = ["mspm0-metapac/mspm0g1518pm"]
+mspm0g1518pz = ["mspm0-metapac/mspm0g1518pz"]
+mspm0g1518pn = ["mspm0-metapac/mspm0g1518pn"]
+mspm0g1518zaw = ["mspm0-metapac/mspm0g1518zaw"]
 mspm0g1519rhb = ["mspm0-metapac/mspm0g1519rhb"]
+mspm0g1519rgz = ["mspm0-metapac/mspm0g1519rgz"]
+mspm0g1519pt = ["mspm0-metapac/mspm0g1519pt"]
+mspm0g1519pm = ["mspm0-metapac/mspm0g1519pm"]
+mspm0g1519pz = ["mspm0-metapac/mspm0g1519pz"]
+mspm0g1519pn = ["mspm0-metapac/mspm0g1519pn"]
 mspm0g3105dgs20 = ["mspm0-metapac/mspm0g3105dgs20"]
 mspm0g3105dgs28 = ["mspm0-metapac/mspm0g3105dgs28"]
 mspm0g3105rhb = ["mspm0-metapac/mspm0g3105rhb"]
@@ -228,77 +238,92 @@ mspm0g3107dgs20 = ["mspm0-metapac/mspm0g3107dgs20"]
 mspm0g3107dgs28 = ["mspm0-metapac/mspm0g3107dgs28"]
 mspm0g3107rhb = ["mspm0-metapac/mspm0g3107rhb"]
 mspm0g3505dgs28 = ["mspm0-metapac/mspm0g3505dgs28"]
-mspm0g3505pm = ["mspm0-metapac/mspm0g3505pm"]
-mspm0g3505pt = ["mspm0-metapac/mspm0g3505pt"]
-mspm0g3505rgz = ["mspm0-metapac/mspm0g3505rgz"]
 mspm0g3505rhb = ["mspm0-metapac/mspm0g3505rhb"]
+mspm0g3505rgz = ["mspm0-metapac/mspm0g3505rgz"]
+mspm0g3505pt = ["mspm0-metapac/mspm0g3505pt"]
+mspm0g3505pm = ["mspm0-metapac/mspm0g3505pm"]
 mspm0g3506dgs28 = ["mspm0-metapac/mspm0g3506dgs28"]
-mspm0g3506pm = ["mspm0-metapac/mspm0g3506pm"]
-mspm0g3506pt = ["mspm0-metapac/mspm0g3506pt"]
-mspm0g3506rgz = ["mspm0-metapac/mspm0g3506rgz"]
 mspm0g3506rhb = ["mspm0-metapac/mspm0g3506rhb"]
+mspm0g3506rgz = ["mspm0-metapac/mspm0g3506rgz"]
+mspm0g3506pt = ["mspm0-metapac/mspm0g3506pt"]
+mspm0g3506pm = ["mspm0-metapac/mspm0g3506pm"]
 mspm0g3507dgs28 = ["mspm0-metapac/mspm0g3507dgs28"]
-mspm0g3507pm = ["mspm0-metapac/mspm0g3507pm"]
-mspm0g3507pt = ["mspm0-metapac/mspm0g3507pt"]
-mspm0g3507rgz = ["mspm0-metapac/mspm0g3507rgz"]
 mspm0g3507rhb = ["mspm0-metapac/mspm0g3507rhb"]
+mspm0g3507rgz = ["mspm0-metapac/mspm0g3507rgz"]
+mspm0g3507pt = ["mspm0-metapac/mspm0g3507pt"]
+mspm0g3507pm = ["mspm0-metapac/mspm0g3507pm"]
+mspm0g3518rhb = ["mspm0-metapac/mspm0g3518rhb"]
+mspm0g3518rgz = ["mspm0-metapac/mspm0g3518rgz"]
+mspm0g3518pt = ["mspm0-metapac/mspm0g3518pt"]
+mspm0g3518pm = ["mspm0-metapac/mspm0g3518pm"]
+mspm0g3518pz = ["mspm0-metapac/mspm0g3518pz"]
+mspm0g3518pn = ["mspm0-metapac/mspm0g3518pn"]
+mspm0g3519rhb = ["mspm0-metapac/mspm0g3519rhb"]
+mspm0g3519rgz = ["mspm0-metapac/mspm0g3519rgz"]
+mspm0g3519pt = ["mspm0-metapac/mspm0g3519pt"]
 mspm0g3519pm = ["mspm0-metapac/mspm0g3519pm"]
-mspm0g3519pn = ["mspm0-metapac/mspm0g3519pn"]
 mspm0g3519pz = ["mspm0-metapac/mspm0g3519pz"]
-mspm0g3519rgz = ["mspm0-metapac/mspm0g3519rgz"]
-mspm0g3519rhb = ["mspm0-metapac/mspm0g3519rhb"]
+mspm0g3519pn = ["mspm0-metapac/mspm0g3519pn"]
+mspm0g3519zaw = ["mspm0-metapac/mspm0g3519zaw"]
+mspm0g5187rhb = ["mspm0-metapac/mspm0g5187rhb"]
+mspm0g5187rgz = ["mspm0-metapac/mspm0g5187rgz"]
+mspm0g5187pt = ["mspm0-metapac/mspm0g5187pt"]
+mspm0g5187pm = ["mspm0-metapac/mspm0g5187pm"]
+mspm0g5187ruy = ["mspm0-metapac/mspm0g5187ruy"]
+mspm0g5187ycj = ["mspm0-metapac/mspm0g5187ycj"]
+mspm0g5187rge = ["mspm0-metapac/mspm0g5187rge"]
 mspm0h3216pt = ["mspm0-metapac/mspm0h3216pt"]
 mspm0l1105dgs20 = ["mspm0-metapac/mspm0l1105dgs20"]
 mspm0l1105dgs28 = ["mspm0-metapac/mspm0l1105dgs28"]
-mspm0l1105dyy = ["mspm0-metapac/mspm0l1105dyy"]
 mspm0l1105rge = ["mspm0-metapac/mspm0l1105rge"]
 mspm0l1105rtr = ["mspm0-metapac/mspm0l1105rtr"]
+mspm0l1105dyy = ["mspm0-metapac/mspm0l1105dyy"]
+mspm0l1106rhb = ["mspm0-metapac/mspm0l1106rhb"]
 mspm0l1106dgs20 = ["mspm0-metapac/mspm0l1106dgs20"]
 mspm0l1106dgs28 = ["mspm0-metapac/mspm0l1106dgs28"]
-mspm0l1106dyy = ["mspm0-metapac/mspm0l1106dyy"]
 mspm0l1106rge = ["mspm0-metapac/mspm0l1106rge"]
-mspm0l1106rhb = ["mspm0-metapac/mspm0l1106rhb"]
 mspm0l1106rtr = ["mspm0-metapac/mspm0l1106rtr"]
-mspm0l1227pm = ["mspm0-metapac/mspm0l1227pm"]
+mspm0l1106dyy = ["mspm0-metapac/mspm0l1106dyy"]
+mspm0l1227rhb = ["mspm0-metapac/mspm0l1227rhb"]
 mspm0l1227pn = ["mspm0-metapac/mspm0l1227pn"]
+mspm0l1227rgz = ["mspm0-metapac/mspm0l1227rgz"]
 mspm0l1227pt = ["mspm0-metapac/mspm0l1227pt"]
+mspm0l1227pm = ["mspm0-metapac/mspm0l1227pm"]
 mspm0l1227rge = ["mspm0-metapac/mspm0l1227rge"]
-mspm0l1227rgz = ["mspm0-metapac/mspm0l1227rgz"]
-mspm0l1227rhb = ["mspm0-metapac/mspm0l1227rhb"]
-mspm0l1228pm = ["mspm0-metapac/mspm0l1228pm"]
+mspm0l1228rhb = ["mspm0-metapac/mspm0l1228rhb"]
 mspm0l1228pn = ["mspm0-metapac/mspm0l1228pn"]
+mspm0l1228rgz = ["mspm0-metapac/mspm0l1228rgz"]
 mspm0l1228pt = ["mspm0-metapac/mspm0l1228pt"]
+mspm0l1228pm = ["mspm0-metapac/mspm0l1228pm"]
 mspm0l1228rge = ["mspm0-metapac/mspm0l1228rge"]
-mspm0l1228rgz = ["mspm0-metapac/mspm0l1228rgz"]
-mspm0l1228rhb = ["mspm0-metapac/mspm0l1228rhb"]
 mspm0l1303rge = ["mspm0-metapac/mspm0l1303rge"]
+mspm0l1304rhb = ["mspm0-metapac/mspm0l1304rhb"]
 mspm0l1304dgs20 = ["mspm0-metapac/mspm0l1304dgs20"]
 mspm0l1304dgs28 = ["mspm0-metapac/mspm0l1304dgs28"]
-mspm0l1304dyy = ["mspm0-metapac/mspm0l1304dyy"]
 mspm0l1304rge = ["mspm0-metapac/mspm0l1304rge"]
-mspm0l1304rhb = ["mspm0-metapac/mspm0l1304rhb"]
 mspm0l1304rtr = ["mspm0-metapac/mspm0l1304rtr"]
+mspm0l1304dyy = ["mspm0-metapac/mspm0l1304dyy"]
 mspm0l1305dgs20 = ["mspm0-metapac/mspm0l1305dgs20"]
 mspm0l1305dgs28 = ["mspm0-metapac/mspm0l1305dgs28"]
-mspm0l1305dyy = ["mspm0-metapac/mspm0l1305dyy"]
 mspm0l1305rge = ["mspm0-metapac/mspm0l1305rge"]
 mspm0l1305rtr = ["mspm0-metapac/mspm0l1305rtr"]
+mspm0l1305dyy = ["mspm0-metapac/mspm0l1305dyy"]
+mspm0l1306rhb = ["mspm0-metapac/mspm0l1306rhb"]
 mspm0l1306dgs20 = ["mspm0-metapac/mspm0l1306dgs20"]
 mspm0l1306dgs28 = ["mspm0-metapac/mspm0l1306dgs28"]
-mspm0l1306dyy = ["mspm0-metapac/mspm0l1306dyy"]
 mspm0l1306rge = ["mspm0-metapac/mspm0l1306rge"]
-mspm0l1306rhb = ["mspm0-metapac/mspm0l1306rhb"]
+mspm0l1306dyy = ["mspm0-metapac/mspm0l1306dyy"]
 mspm0l1343dgs20 = ["mspm0-metapac/mspm0l1343dgs20"]
 mspm0l1344dgs20 = ["mspm0-metapac/mspm0l1344dgs20"]
 mspm0l1345dgs28 = ["mspm0-metapac/mspm0l1345dgs28"]
 mspm0l1346dgs28 = ["mspm0-metapac/mspm0l1346dgs28"]
+mspm0l2227rgz = ["mspm0-metapac/mspm0l2227rgz"]
+mspm0l2227pt = ["mspm0-metapac/mspm0l2227pt"]
 mspm0l2227pm = ["mspm0-metapac/mspm0l2227pm"]
 mspm0l2227pn = ["mspm0-metapac/mspm0l2227pn"]
-mspm0l2227pt = ["mspm0-metapac/mspm0l2227pt"]
-mspm0l2227rgz = ["mspm0-metapac/mspm0l2227rgz"]
+mspm0l2228rgz = ["mspm0-metapac/mspm0l2228rgz"]
+mspm0l2228pt = ["mspm0-metapac/mspm0l2228pt"]
 mspm0l2228pm = ["mspm0-metapac/mspm0l2228pm"]
 mspm0l2228pn = ["mspm0-metapac/mspm0l2228pn"]
-mspm0l2228pt = ["mspm0-metapac/mspm0l2228pt"]
-mspm0l2228rgz = ["mspm0-metapac/mspm0l2228rgz"]
 msps003f3pw20 = ["mspm0-metapac/msps003f3pw20"]
-msps003f4pw20 = ["mspm0-metapac/msps003f4pw20"]
+msps003f4pw20 = ["mspm0-metapac/msps003f4pw20"]
\ No newline at end of file
diff --git a/embassy-mspm0/build.rs b/embassy-mspm0/build.rs
index 0fe056c4e..ac40adbdf 100644
--- a/embassy-mspm0/build.rs
+++ b/embassy-mspm0/build.rs
@@ -31,7 +31,7 @@ fn generate_code(cfgs: &mut CfgSet) {
         PathBuf::from(env::var_os("OUT_DIR").unwrap()).display(),
     );
 
-    cfgs.declare_all(&["gpio_pb", "gpio_pc", "int_group1"]);
+    cfgs.declare_all(&["gpio_pb", "gpio_pc", "int_group1", "unicomm"]);
 
     let chip_name = match env::vars()
         .map(|(a, _)| a)
@@ -116,6 +116,10 @@ fn get_chip_cfgs(chip_name: &str) -> Vec<String> {
         cfgs.push("mspm0g351x".to_string());
     }
 
+    if chip_name.starts_with("mspm0g518") {
+        cfgs.push("mspm0g518x".to_string());
+    }
+
     if chip_name.starts_with("mspm0h321") {
         cfgs.push("mspm0h321x".to_string());
     }
@@ -300,6 +304,15 @@ fn get_singletons(cfgs: &mut common::CfgSet) -> Vec<Singleton> {
             // by the HAL.
             "iomux" | "cpuss" => true,
 
+            // Unicomm instances get their own singletons, but we need to enable a cfg for unicomm drivers.
+            "unicomm" => {
+                cfgs.enable("unicomm");
+                false
+            }
+
+            // TODO: Remove after TIMB is fixed
+            "tim" if peripheral.name.starts_with("TIMB") => true,
+
             _ => false,
         };
 
@@ -423,6 +436,8 @@ fn time_driver(singletons: &mut Vec<Singleton>, cfgs: &mut CfgSet) {
     // Verify the selected timer is available
     let selected_timer = match time_driver.as_ref().map(|x| x.as_ref()) {
         None => "",
+        // TODO: Fix TIMB0
+        // Some("timb0") => "TIMB0",
         Some("timg0") => "TIMG0",
         Some("timg1") => "TIMG1",
         Some("timg2") => "TIMG2",
@@ -440,16 +455,17 @@ fn time_driver(singletons: &mut Vec<Singleton>, cfgs: &mut CfgSet) {
         Some("tima1") => "TIMA1",
         Some("any") => {
             // Order of timer candidates:
-            // 1. 16-bit, 2 channel
-            // 2. 16-bit, 2 channel with shadow registers
-            // 3. 16-bit, 4 channel
-            // 4. 16-bit with QEI
-            // 5. Advanced timers
+            // 1. Basic timers
+            // 2. 16-bit, 2 channel
+            // 3. 16-bit, 2 channel with shadow registers
+            // 4. 16-bit, 4 channel
+            // 5. 16-bit with QEI
+            // 6. Advanced timers
             //
-            // TODO: Select RTC first if available
             // TODO: 32-bit timers are not considered yet
             [
-                // 16-bit, 2 channel
+                // basic timers. No PWM pins
+                // "TIMB0", // 16-bit, 2 channel
                 "TIMG0", "TIMG1", "TIMG2", "TIMG3", // 16-bit, 2 channel with shadow registers
                 "TIMG4", "TIMG5", "TIMG6", "TIMG7",  // 16-bit, 4 channel
                 "TIMG14", // 16-bit with QEI
@@ -519,6 +535,8 @@ fn generate_timers() -> TokenStream {
         .peripherals
         .iter()
         .filter(|p| p.name.starts_with("TIM"))
+        // TODO: Fix TIMB when used at time driver.
+        .filter(|p| !p.name.starts_with("TIMB"))
         .map(|peripheral| {
             let name = Ident::new(&peripheral.name, Span::call_site());
             let timers = &*TIMERS;
@@ -730,6 +748,24 @@ struct TimerDesc {
 const TIMERS: LazyLock<HashMap<String, TimerDesc>> = LazyLock::new(|| {
     let mut map = HashMap::new();
     map.insert(
+        "TIMB0".into(),
+        TimerDesc {
+            bits: 16,
+            prescaler: true,
+            repeat_counter: false,
+            ccp_channels_internal: 2,
+            ccp_channels_external: 2,
+            external_pwm_channels: 0,
+            phase_load: false,
+            shadow_load: false,
+            shadow_ccs: false,
+            deadband: false,
+            fault_handler: false,
+            qei_hall: false,
+        },
+    );
+
+    map.insert(
         "TIMG0".into(),
         TimerDesc {
             bits: 16,
diff --git a/embassy-mspm0/src/gpio.rs b/embassy-mspm0/src/gpio.rs
index d8eb42dc2..709102c59 100644
--- a/embassy-mspm0/src/gpio.rs
+++ b/embassy-mspm0/src/gpio.rs
@@ -841,6 +841,7 @@ impl<'d> embedded_hal_async::digital::Wait for OutputOpenDrain<'d> {
     }
 }
 
+#[cfg_attr(mspm0g518x, allow(dead_code))]
 #[derive(Copy, Clone)]
 pub struct PfType {
     pull: Pull,
@@ -948,6 +949,7 @@ pub(crate) trait SealedPin {
         });
     }
 
+    #[cfg_attr(mspm0g518x, allow(dead_code))]
     fn update_pf(&self, ty: PfType) {
         let pincm = pac::IOMUX.pincm(self._pin_cm() as usize);
         let pf = pincm.read().pf();
@@ -955,6 +957,7 @@ pub(crate) trait SealedPin {
         set_pf(self._pin_cm() as usize, pf, ty);
     }
 
+    #[cfg_attr(mspm0g518x, allow(dead_code))]
     fn set_as_pf(&self, pf: u8, ty: PfType) {
         set_pf(self._pin_cm() as usize, pf, ty)
     }
@@ -967,6 +970,7 @@ pub(crate) trait SealedPin {
     ///
     /// Note that this also disables the internal weak pull-up and pull-down resistors.
     #[inline]
+    #[cfg_attr(mspm0g518x, allow(dead_code))]
     fn set_as_disconnected(&self) {
         self.set_as_analog();
     }
diff --git a/embassy-mspm0/src/i2c_target.rs b/embassy-mspm0/src/i2c_target.rs
index 86be91415..e371fa903 100644
--- a/embassy-mspm0/src/i2c_target.rs
+++ b/embassy-mspm0/src/i2c_target.rs
@@ -12,12 +12,13 @@ use embassy_embedded_hal::SetConfig;
 use mspm0_metapac::i2c::vals::CpuIntIidxStat;
 
 use crate::gpio::{AnyPin, SealedPin};
-use crate::interrupt::InterruptExt;
-use crate::mode::{Async, Blocking, Mode};
-use crate::pac::{self, i2c::vals};
-use crate::{i2c, i2c_target, interrupt, Peri};
 // Re-use I2c controller types
 use crate::i2c::{ClockSel, ConfigError, Info, Instance, InterruptHandler, SclPin, SdaPin, State};
+use crate::interrupt::InterruptExt;
+use crate::mode::{Async, Blocking, Mode};
+use crate::pac::i2c::vals;
+use crate::pac::{self};
+use crate::{Peri, i2c, i2c_target, interrupt};
 
 #[non_exhaustive]
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
diff --git a/embassy-mspm0/src/lib.rs b/embassy-mspm0/src/lib.rs
index c43c81853..548fb33ca 100644
--- a/embassy-mspm0/src/lib.rs
+++ b/embassy-mspm0/src/lib.rs
@@ -8,20 +8,23 @@
 )]
 #![doc = include_str!("../README.md")]
 
-// This mod MUST go first, so that the others see its macros.
+// These mods MUST go first, so that the others see the macros.
 pub(crate) mod fmt;
-
-// This must be declared early as well for
 mod macros;
 
 pub mod adc;
 pub mod dma;
 pub mod gpio;
+// TODO: I2C unicomm
+#[cfg(not(unicomm))]
 pub mod i2c;
+#[cfg(not(unicomm))]
 pub mod i2c_target;
 #[cfg(any(mspm0g150x, mspm0g151x, mspm0g350x, mspm0g351x))]
 pub mod mathacl;
 pub mod timer;
+// TODO: UART unicomm
+#[cfg(not(unicomm))]
 pub mod uart;
 pub mod wwdt;
 
@@ -276,7 +279,7 @@ pub enum ResetCause {
     /// WWDT0 violation
     BootrstWwdt0Violation,
     /// WWDT1 violation (G-series only)
-    #[cfg(any(mspm0g110x, mspm0g150x, mspm0g151x, mspm0g310x, mspm0g350x, mspm0g351x))]
+    #[cfg(any(mspm0g110x, mspm0g150x, mspm0g151x, mspm0g310x, mspm0g350x, mspm0g351x, mspm0g518x))]
     SysrstWwdt1Violation,
     /// BSL exit (if present)
     SysrstBslExit,
@@ -326,7 +329,8 @@ pub fn read_reset_cause() -> Result<ResetCause, u8> {
             mspm0g151x,
             mspm0g310x,
             mspm0g350x,
-            mspm0g351x
+            mspm0g351x,
+            mspm0g518x,
         )))]
         Id::BOOTNONPMUPARITY => Ok(BootrstNonPmuParityFault),
         Id::BOOTCLKFAIL => Ok(BootrstClockFault),
@@ -335,7 +339,7 @@ pub fn read_reset_cause() -> Result<ResetCause, u8> {
         Id::BOOTWWDT0 => Ok(BootrstWwdt0Violation),
         Id::SYSBSLEXIT => Ok(SysrstBslExit),
         Id::SYSBSLENTRY => Ok(SysrstBslEntry),
-        #[cfg(any(mspm0g110x, mspm0g150x, mspm0g151x, mspm0g310x, mspm0g350x, mspm0g351x))]
+        #[cfg(any(mspm0g110x, mspm0g150x, mspm0g151x, mspm0g310x, mspm0g350x, mspm0g351x, mspm0g518x))]
         Id::SYSWWDT1 => Ok(SysrstWwdt1Violation),
         #[cfg(not(any(mspm0c110x, mspm0c1105_c1106, mspm0g351x, mspm0g151x)))]
         Id::SYSFLASHECC => Ok(SysrstFlashEccError),
diff --git a/embassy-mspm0/src/macros.rs b/embassy-mspm0/src/macros.rs
index 5355e7d59..3a12a528a 100644
--- a/embassy-mspm0/src/macros.rs
+++ b/embassy-mspm0/src/macros.rs
@@ -1,5 +1,6 @@
 #![macro_use]
 
+#[allow(unused)]
 macro_rules! new_pin {
     ($name: ident, $pf_type: expr) => {{
         let pin = $name;
diff --git a/embassy-mspm0/src/time_driver.rs b/embassy-mspm0/src/time_driver.rs
index 0743c667b..b42ff61c2 100644
--- a/embassy-mspm0/src/time_driver.rs
+++ b/embassy-mspm0/src/time_driver.rs
@@ -16,6 +16,8 @@ use crate::timer::SealedTimer;
 compile_error!("TIMG12 and TIMG13 are not supported by the time driver yet");
 
 // Currently TIMG12 and TIMG13 are excluded because those are 32-bit timers.
+#[cfg(time_driver_timb0)]
+type T = peripherals::TIMB0;
 #[cfg(time_driver_timg0)]
 type T = peripherals::TIMG0;
 #[cfg(time_driver_timg1)]
@@ -333,6 +335,8 @@ pub(crate) fn init(cs: CriticalSection) {
     DRIVER.init(cs);
 }
 
+// TODO: TIMB0
+
 #[cfg(time_driver_timg0)]
 #[interrupt]
 fn TIMG0() {
diff --git a/embassy-net-nrf91/CHANGELOG.md b/embassy-net-nrf91/CHANGELOG.md
index 11974ac04..66a576b72 100644
--- a/embassy-net-nrf91/CHANGELOG.md
+++ b/embassy-net-nrf91/CHANGELOG.md
@@ -8,8 +8,6 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
-- changed: updated to nrf-pac with nrf52/nrf53/nrf91 register layout more similar to nrf54
+## 0.1.0 - 2025-12-15
 
-## 0.1.1 - 2025-08-14
-
-- First release with changelog.
+- Initial release
diff --git a/embassy-net-nrf91/Cargo.toml b/embassy-net-nrf91/Cargo.toml
index cd9bf2987..349ff2880 100644
--- a/embassy-net-nrf91/Cargo.toml
+++ b/embassy-net-nrf91/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-net-nrf91"
-version = "0.1.1"
+version = "0.1.0"
 edition = "2024"
 description = "embassy-net driver for Nordic nRF91-series cellular modems"
 keywords = ["embedded", "nrf91", "embassy-net", "cellular"]
@@ -8,7 +8,7 @@ categories = ["embedded", "hardware-support", "no-std", "network-programming", "
 license = "MIT OR Apache-2.0"
 repository = "https://github.com/embassy-rs/embassy"
 documentation = "https://docs.embassy.dev/embassy-net-nrf91"
-publish = false
+publish = true
 
 [features]
 defmt = ["dep:defmt", "heapless/defmt-03"]
@@ -18,7 +18,7 @@ log = ["dep:log"]
 defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.14", optional = true }
 
-nrf-pac = { version = "0.1.0", git = "https://github.com/embassy-rs/nrf-pac.git", rev = "52fd51ce762a3d3a81660dea62947e6d2d1e9d91" }
+nrf-pac = { version = "0.2.0", git = "https://github.com/embassy-rs/nrf-pac.git", rev = "7f450696f95591ce42f4da6e7d0402750ab1e50a" }
 cortex-m = "0.7.7"
 
 embassy-time = { version = "0.5.0", path = "../embassy-time" }
diff --git a/embassy-net-nrf91/src/lib.rs b/embassy-net-nrf91/src/lib.rs
index dd4812aae..2ffa2890f 100644
--- a/embassy-net-nrf91/src/lib.rs
+++ b/embassy-net-nrf91/src/lib.rs
@@ -311,7 +311,7 @@ struct PendingRequest {
     waker: Waker,
 }
 
-#[derive(Copy, Clone, PartialEq, Eq)]
+#[derive(Copy, Clone, PartialEq, Eq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 struct NoFreeBufs;
 
@@ -1061,7 +1061,8 @@ struct ListItem {
 }
 
 #[repr(C)]
-#[derive(defmt::Format, Clone, Copy)]
+#[derive(Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 struct Message {
     id: u32,
 
diff --git a/embassy-net-tuntap/Cargo.toml b/embassy-net-tuntap/Cargo.toml
index 77668b445..95dc1e1f0 100644
--- a/embassy-net-tuntap/Cargo.toml
+++ b/embassy-net-tuntap/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-net-tuntap"
-version = "0.1.0"
+version = "0.1.1"
 description = "embassy-net driver for Linux TUN/TAP interfaces."
 keywords = ["embedded", "tuntap", "embassy-net", "ethernet", "async"]
 categories = ["embedded", "hardware-support", "network-programming", "asynchronous"]
@@ -11,7 +11,7 @@ documentation = "https://docs.embassy.dev/embassy-net-tuntap"
 
 [dependencies]
 embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver" }
-async-io = "1.6.0"
+async-io = "2.6.0"
 log = "0.4.14"
 libc = "0.2.101"
 
diff --git a/embassy-net-tuntap/src/lib.rs b/embassy-net-tuntap/src/lib.rs
index 2ff23f462..33a251248 100644
--- a/embassy-net-tuntap/src/lib.rs
+++ b/embassy-net-tuntap/src/lib.rs
@@ -2,7 +2,9 @@
 #![doc = include_str!("../README.md")]
 use std::io;
 use std::io::{Read, Write};
+use std::os::fd::AsFd;
 use std::os::unix::io::{AsRawFd, RawFd};
+use std::os::unix::prelude::BorrowedFd;
 use std::task::Context;
 
 use async_io::Async;
@@ -69,6 +71,12 @@ impl AsRawFd for TunTap {
     }
 }
 
+impl AsFd for TunTap {
+    fn as_fd(&self) -> BorrowedFd<'_> {
+        unsafe { BorrowedFd::borrow_raw(self.fd) }
+    }
+}
+
 impl TunTap {
     /// Create a new TUN/TAP device.
     pub fn new(name: &str) -> io::Result<TunTap> {
@@ -164,7 +172,7 @@ impl Driver for TunTapDevice {
     fn receive(&mut self, cx: &mut Context) -> Option<(Self::RxToken<'_>, Self::TxToken<'_>)> {
         let mut buf = vec![0; self.device.get_ref().mtu];
         loop {
-            match self.device.get_mut().read(&mut buf) {
+            match unsafe { self.device.get_mut() }.read(&mut buf) {
                 Ok(n) => {
                     buf.truncate(n);
                     return Some((
@@ -233,7 +241,7 @@ impl<'a> embassy_net_driver::TxToken for TxToken<'a> {
         let result = f(&mut buffer);
 
         // todo handle WouldBlock with async
-        match self.device.get_mut().write(&buffer) {
+        match unsafe { self.device.get_mut() }.write(&buffer) {
             Ok(_) => {}
             Err(e) if e.kind() == io::ErrorKind::WouldBlock => info!("transmit WouldBlock"),
             Err(e) => panic!("transmit error: {:?}", e),
diff --git a/embassy-nrf/CHANGELOG.md b/embassy-nrf/CHANGELOG.md
index 9c53e66a7..0d7bfb5f0 100644
--- a/embassy-nrf/CHANGELOG.md
+++ b/embassy-nrf/CHANGELOG.md
@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+## 0.9.0 - 2025-12-15
+
 - changed: apply trimming values from FICR.TRIMCNF on nrf53/54l
 - changed: do not panic on BufferedUarte overrun
 - added: allow direct access to the input pin of `gpiote::InputChannel`
@@ -32,6 +34,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 * added: support for nrf54l10 and nrf54l05
 * added: expose uicr write functions
 * added: support for nrf54lm20a
+- added: support buffered rram for nrf54
 
 ## 0.8.0 - 2025-09-30
 
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index ee070f0c0..f8a6ef864 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-nrf"
-version = "0.8.0"
+version = "0.9.0"
 edition = "2024"
 license = "MIT OR Apache-2.0"
 description = "Embassy Hardware Abstraction Layer (HAL) for nRF series microcontrollers"
@@ -223,10 +223,10 @@ embedded-io-async = { version = "0.6.1" }
 rand-core-06 = { package = "rand_core", version = "0.6" }
 rand-core-09 = { package = "rand_core", version = "0.9" }
 
-nrf-pac = { version = "0.1.0", git = "https://github.com/embassy-rs/nrf-pac.git", rev = "52fd51ce762a3d3a81660dea62947e6d2d1e9d91" }
+nrf-pac = { version = "0.2.0", git = "https://github.com/embassy-rs/nrf-pac.git", rev = "7f450696f95591ce42f4da6e7d0402750ab1e50a" }
 
 defmt = { version = "1.0.1", optional = true }
-bitflags = "2.4.2"
+bitflags = "2.10.0"
 log = { version = "0.4.14", optional = true }
 cortex-m-rt = ">=0.6.15,<0.8"
 cortex-m = "0.7.6"
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index 1f6000b13..6b9d2d1da 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -29,17 +29,14 @@ const CHANNEL_COUNT: usize = 12;
 /// Max channels per port
 const CHANNELS_PER_PORT: usize = 8;
 
-#[cfg(any(
-    feature = "nrf52833",
-    feature = "nrf52840",
-    feature = "_nrf5340",
-    feature = "_nrf54l15",
-    feature = "_nrf54l10",
-    feature = "_nrf54l05"
-))]
+#[cfg(any(feature = "nrf52833", feature = "nrf52840", feature = "_nrf5340"))]
 const PIN_COUNT: usize = 48;
+#[cfg(any(feature = "_nrf54l15", feature = "_nrf54l10", feature = "_nrf54l05"))]
+// Highest pin index is P2.10 => (2 * 32 + 10) = 74
+const PIN_COUNT: usize = 75;
 #[cfg(feature = "_nrf54lm20")]
-const PIN_COUNT: usize = 66;
+// Highest pin index is P3.12 => (3 * 32 + 12) = 108
+const PIN_COUNT: usize = 109;
 #[cfg(not(any(
     feature = "nrf52833",
     feature = "nrf52840",
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index db71dee10..584d0a0be 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -845,9 +845,9 @@ pub fn init(config: config::Config) -> Peripherals {
                     // Chips with a certain chip type-specific build code or higher have an
                     // improved APPROTECT ("hardware and software controlled access port protection")
                     // which needs explicit action by the firmware to keep it unlocked
-                    // See https://devzone.nordicsemi.com/nordic/nordic-blog/b/blog/posts/working-with-the-nrf52-series-improved-approtect
+                    // See https://docs.nordicsemi.com/bundle/ps_nrf52840/page/dif.html#d402e184
 
-                    // UICR.APPROTECT = SwDisabled
+                    // UICR.APPROTECT = HwDisabled
                     let res = uicr_write(consts::UICR_APPROTECT, consts::APPROTECT_DISABLED);
                     needs_reset |= res == WriteResult::Written;
                     // APPROTECT.DISABLE = SwDisabled
diff --git a/embassy-nrf/src/rramc.rs b/embassy-nrf/src/rramc.rs
index 521ac4ee7..961e0a535 100644
--- a/embassy-nrf/src/rramc.rs
+++ b/embassy-nrf/src/rramc.rs
@@ -1,5 +1,6 @@
 //! Resistive Random-Access Memory Controller driver.
 
+use core::marker::PhantomData;
 use core::{ptr, slice};
 
 use embedded_storage::nor_flash::{
@@ -9,11 +10,28 @@ use embedded_storage::nor_flash::{
 use crate::peripherals::RRAMC;
 use crate::{Peri, pac};
 
+/// Unbuffered RRAMC mode.
+pub struct Unbuffered;
+
+/// Buffered RRAMC mode.
+pub struct Buffered<const BUFFER_SIZE_BYTES: usize>;
+
+trait SealedRramMode {}
+
+/// Operating modes for RRAMC
+#[allow(private_bounds)]
+pub trait RramMode: SealedRramMode {}
+
+impl SealedRramMode for Unbuffered {}
+impl RramMode for Unbuffered {}
+impl<const BUFFER_SIZE_BYTES: usize> SealedRramMode for Buffered<BUFFER_SIZE_BYTES> {}
+impl<const BUFFER_SIZE_BYTES: usize> RramMode for Buffered<BUFFER_SIZE_BYTES> {}
+
 //
 // Export Nvmc alias and page size for downstream compatibility
 //
 /// RRAM-backed `Nvmc` compatibile driver.
-pub type Nvmc<'d> = Rramc<'d>;
+pub type Nvmc<'d> = Rramc<'d, Unbuffered>;
 /// Emulated page size.  RRAM does not use pages. This exists only for downstream compatibility.
 pub const PAGE_SIZE: usize = 4096;
 
@@ -44,16 +62,27 @@ impl NorFlashError for Error {
 
 /// Resistive Random-Access Memory Controller (RRAMC) that implements the `embedded-storage`
 /// traits.
-pub struct Rramc<'d> {
+pub struct Rramc<'d, MODE: RramMode> {
     _p: Peri<'d, RRAMC>,
+    _d: PhantomData<MODE>,
+}
+
+impl<'d> Rramc<'d, Unbuffered> {
+    /// Create Rramc driver.
+    pub fn new(_p: Peri<'d, RRAMC>) -> Rramc<'d, Unbuffered> {
+        Self { _p, _d: PhantomData }
+    }
 }
 
-impl<'d> Rramc<'d> {
+impl<'d, const BUFFER_SIZE_BYTES: usize> Rramc<'d, Buffered<BUFFER_SIZE_BYTES>> {
     /// Create Rramc driver.
-    pub fn new(_p: Peri<'d, RRAMC>) -> Self {
-        Self { _p }
+    pub fn new_buffered(_p: Peri<'d, RRAMC>) -> Rramc<'d, Buffered<BUFFER_SIZE_BYTES>> {
+        assert!(BUFFER_SIZE_BYTES > 0 && BUFFER_SIZE_BYTES <= 512);
+        Self { _p, _d: PhantomData }
     }
+}
 
+impl<'d, MODE: RramMode> Rramc<'d, MODE> {
     fn regs() -> pac::rramc::Rramc {
         pac::RRAMC
     }
@@ -63,18 +92,48 @@ impl<'d> Rramc<'d> {
         while !p.ready().read().ready() {}
     }
 
+    fn enable_read(&self) {
+        Self::regs().config().write(|w| w.set_wen(false));
+    }
+
+    fn finish_write(&mut self) {
+        self.enable_read();
+        self.wait_ready();
+    }
+}
+
+impl<'d> Rramc<'d, Unbuffered> {
+    fn wait_ready_write(&mut self) {
+        let p = Self::regs();
+        while !p.readynext().read().readynext() {}
+    }
+
+    fn enable_write(&self) {
+        Self::regs().config().write(|w| {
+            w.set_wen(true);
+            w.set_writebufsize(pac::rramc::vals::Writebufsize::UNBUFFERED)
+        });
+    }
+}
+
+impl<'d, const SIZE: usize> Rramc<'d, Buffered<SIZE>> {
     fn wait_ready_write(&mut self) {
         let p = Self::regs();
         while !p.readynext().read().readynext() {}
         while !p.bufstatus().writebufempty().read().empty() {}
     }
 
-    fn enable_read(&self) {
-        Self::regs().config().write(|w| w.set_wen(false));
+    fn commit(&self) {
+        let p = Self::regs();
+        p.tasks_commitwritebuf().write_value(1);
+        while !p.bufstatus().writebufempty().read().empty() {}
     }
 
     fn enable_write(&self) {
-        Self::regs().config().write(|w| w.set_wen(true));
+        Self::regs().config().write(|w| {
+            w.set_wen(true);
+            w.set_writebufsize(pac::rramc::vals::Writebufsize::from_bits(SIZE as _))
+        });
     }
 }
 
@@ -83,13 +142,13 @@ impl<'d> Rramc<'d> {
 // implement the traits for downstream compatibility.
 //
 
-impl<'d> MultiwriteNorFlash for Rramc<'d> {}
+impl<'d> MultiwriteNorFlash for Rramc<'d, Unbuffered> {}
 
-impl<'d> ErrorType for Rramc<'d> {
+impl<'d> ErrorType for Rramc<'d, Unbuffered> {
     type Error = Error;
 }
 
-impl<'d> ReadNorFlash for Rramc<'d> {
+impl<'d> ReadNorFlash for Rramc<'d, Unbuffered> {
     const READ_SIZE: usize = 1;
 
     fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
@@ -107,7 +166,7 @@ impl<'d> ReadNorFlash for Rramc<'d> {
     }
 }
 
-impl<'d> NorFlash for Rramc<'d> {
+impl<'d> NorFlash for Rramc<'d, Unbuffered> {
     const WRITE_SIZE: usize = WRITE_LINE_SIZE;
     const ERASE_SIZE: usize = PAGE_SIZE;
 
@@ -139,11 +198,100 @@ impl<'d> NorFlash for Rramc<'d> {
                 self.wait_ready_write();
             }
         }
+        self.finish_write();
+        Ok(())
+    }
+
+    fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
+        if offset as usize + bytes.len() > FLASH_SIZE {
+            return Err(Error::OutOfBounds);
+        }
+        if offset as usize % Self::WRITE_SIZE != 0 || bytes.len() % Self::WRITE_SIZE != 0 {
+            return Err(Error::Unaligned);
+        }
+
+        self.enable_write();
+        self.wait_ready();
+
+        unsafe {
+            let p_src = bytes.as_ptr() as *const u32;
+            let p_dst = offset as *mut u32;
+            let words = bytes.len() / 4;
+            for i in 0..words {
+                let w = ptr::read_unaligned(p_src.add(i));
+                ptr::write_volatile(p_dst.add(i), w);
+                if (i + 1) % (Self::WRITE_SIZE / 4) == 0 {
+                    self.wait_ready_write();
+                }
+            }
+        }
 
         self.enable_read();
         self.wait_ready();
         Ok(())
     }
+}
+
+impl<'d, const BUFFER_SIZE_BYTES: usize> MultiwriteNorFlash for Rramc<'d, Buffered<BUFFER_SIZE_BYTES>> {}
+
+impl<'d, const BUFFER_SIZE_BYTES: usize> ErrorType for Rramc<'d, Buffered<BUFFER_SIZE_BYTES>> {
+    type Error = Error;
+}
+
+impl<'d, const BUFFER_SIZE_BYTES: usize> ReadNorFlash for Rramc<'d, Buffered<BUFFER_SIZE_BYTES>> {
+    const READ_SIZE: usize = 1;
+
+    fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
+        if offset as usize >= FLASH_SIZE || offset as usize + bytes.len() > FLASH_SIZE {
+            return Err(Error::OutOfBounds);
+        }
+
+        let flash_data = unsafe { slice::from_raw_parts(offset as *const u8, bytes.len()) };
+        bytes.copy_from_slice(flash_data);
+        Ok(())
+    }
+
+    fn capacity(&self) -> usize {
+        FLASH_SIZE
+    }
+}
+
+impl<'d, const BUFFER_SIZE_BYTES: usize> NorFlash for Rramc<'d, Buffered<BUFFER_SIZE_BYTES>> {
+    const WRITE_SIZE: usize = WRITE_LINE_SIZE;
+    const ERASE_SIZE: usize = PAGE_SIZE;
+
+    // RRAM can overwrite in-place, so emulate page erases by overwriting the page bytes with 0xFF.
+    fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
+        if to < from || to as usize > FLASH_SIZE {
+            return Err(Error::OutOfBounds);
+        }
+        if from as usize % Self::ERASE_SIZE != 0 || to as usize % Self::ERASE_SIZE != 0 {
+            return Err(Error::Unaligned);
+        }
+
+        self.enable_write();
+        self.wait_ready();
+
+        // Treat each emulated page separately so callers can rely on post‑erase read‑back
+        // returning 0xFF just like on real NOR flash.
+        let buf = [0xFFu8; BUFFER_SIZE_BYTES];
+        for page_addr in (from..to).step_by(Self::ERASE_SIZE) {
+            let page_end = page_addr + Self::ERASE_SIZE as u32;
+            for line_addr in (page_addr..page_end).step_by(BUFFER_SIZE_BYTES) {
+                unsafe {
+                    let src = buf.as_ptr() as *const u32;
+                    let dst = line_addr as *mut u32;
+                    for i in 0..(Self::WRITE_SIZE / 4) {
+                        core::ptr::write_volatile(dst.add(i), core::ptr::read_unaligned(src.add(i)));
+                    }
+                }
+                self.wait_ready_write();
+            }
+        }
+        self.commit();
+        self.finish_write();
+        Ok(())
+    }
 
     fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
         if offset as usize + bytes.len() > FLASH_SIZE {
@@ -169,6 +317,7 @@ impl<'d> NorFlash for Rramc<'d> {
             }
         }
 
+        self.commit();
         self.enable_read();
         self.wait_ready();
         Ok(())
diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs
index abf9a923f..6c38ab3fe 100644
--- a/embassy-nrf/src/twim.rs
+++ b/embassy-nrf/src/twim.rs
@@ -174,7 +174,7 @@ impl<'d> Twim<'d> {
                 });
                 w.set_drive1(gpiovals::Drive::D);
             }
-            if config.sda_pullup {
+            if config.scl_pullup {
                 w.set_pull(gpiovals::Pull::PULLUP);
             }
         });
diff --git a/embassy-stm32-wpan/Cargo.toml b/embassy-stm32-wpan/Cargo.toml
index 103dedead..acf977ed5 100644
--- a/embassy-stm32-wpan/Cargo.toml
+++ b/embassy-stm32-wpan/Cargo.toml
@@ -41,12 +41,12 @@ log = { version = "0.4.17", optional = true }
 
 cortex-m = "0.7.6"
 heapless = "0.8"
-aligned = "0.4.1"
-critical-section = "1.1"
+aligned = "0.4.2"
+critical-section = "1.2"
 
 bit_field = "0.10.2"
 stm32-device-signature = { version = "0.3.3", features = ["stm32wb5x"] }
-stm32wb-hci = { version = "0.17.0", optional = true }
+stm32wb-hci = { version = "0.17.3", optional = true }
 futures-util = { version = "0.3.30", default-features = false }
 bitflags = { version = "2.3.3", optional = true }
 
@@ -57,7 +57,7 @@ wb55 = []
 wb55_ble = ["dep:stm32wb-hci"]
 wb55_mac = ["dep:bitflags", "dep:embassy-net-driver", "dep:smoltcp", "smoltcp/medium-ieee802154"]
 
-wba = [ "dep:stm32-bindings" ]
+wba = [ "dep:stm32-bindings", "dep:embassy-time" ]
 wba_ble = [ "stm32-bindings/wba_wpan_mac" , "stm32-bindings/wba_wpan" ]
 wba_mac = [ "stm32-bindings/wba_wpan_mac", "stm32-bindings/wba_wpan_ble" , "stm32-bindings/lib_wba5_linklayer15_4", "stm32-bindings/lib_wba_mac_lib" , "stm32-bindings/wba_wpan" ]
 
diff --git a/embassy-stm32-wpan/src/wb55/sub/ble.rs b/embassy-stm32-wpan/src/wb55/sub/ble.rs
index afc4a510a..a822d6530 100644
--- a/embassy-stm32-wpan/src/wb55/sub/ble.rs
+++ b/embassy-stm32-wpan/src/wb55/sub/ble.rs
@@ -73,7 +73,9 @@ impl<'a> Ble<'a> {
     pub async fn tl_read(&mut self) -> EvtBox<Self> {
         self.ipcc_ble_event_channel
             .receive(|| unsafe {
-                if let Some(node_ptr) = LinkedListNode::remove_head(EVT_QUEUE.as_mut_ptr()) {
+                if let Some(node_ptr) =
+                    critical_section::with(|cs| LinkedListNode::remove_head(cs, EVT_QUEUE.as_mut_ptr()))
+                {
                     Some(EvtBox::new(node_ptr.cast()))
                 } else {
                     None
@@ -128,12 +130,8 @@ impl<'a> hci::Controller for Ble<'a> {
         self.tl_write(opcode.0, payload).await;
     }
 
-    #[allow(invalid_reference_casting)]
-    async fn controller_read_into(&self, buf: &mut [u8]) {
-        // A complete hack since I cannot update the trait
-        let s = unsafe { &mut *(self as *const _ as *mut Ble) };
-
-        let evt_box = s.tl_read().await;
+    async fn controller_read_into(&mut self, buf: &mut [u8]) {
+        let evt_box = self.tl_read().await;
         let evt_serial = evt_box.serial();
 
         buf[..evt_serial.len()].copy_from_slice(evt_serial);
diff --git a/embassy-stm32-wpan/src/wb55/sub/mm.rs b/embassy-stm32-wpan/src/wb55/sub/mm.rs
index cbb5f130b..0ca7d1835 100644
--- a/embassy-stm32-wpan/src/wb55/sub/mm.rs
+++ b/embassy-stm32-wpan/src/wb55/sub/mm.rs
@@ -4,7 +4,6 @@ use core::mem::MaybeUninit;
 use core::task::Poll;
 
 use aligned::{A4, Aligned};
-use cortex_m::interrupt;
 use embassy_stm32::ipcc::IpccTxChannel;
 use embassy_sync::waitqueue::AtomicWaker;
 
@@ -52,7 +51,7 @@ impl<'a> MemoryManager<'a> {
         loop {
             poll_fn(|cx| unsafe {
                 MM_WAKER.register(cx.waker());
-                if LinkedListNode::is_empty(LOCAL_FREE_BUF_QUEUE.as_mut_ptr()) {
+                if critical_section::with(|cs| LinkedListNode::is_empty(cs, LOCAL_FREE_BUF_QUEUE.as_mut_ptr())) {
                     Poll::Pending
                 } else {
                     Poll::Ready(())
@@ -62,10 +61,9 @@ impl<'a> MemoryManager<'a> {
 
             self.ipcc_mm_release_buffer_channel
                 .send(|| {
-                    interrupt::free(|_| unsafe {
-                        // CS required while moving nodes
-                        while let Some(node_ptr) = LinkedListNode::remove_head(LOCAL_FREE_BUF_QUEUE.as_mut_ptr()) {
-                            LinkedListNode::insert_head(FREE_BUF_QUEUE.as_mut_ptr(), node_ptr);
+                    critical_section::with(|cs| unsafe {
+                        while let Some(node_ptr) = LinkedListNode::remove_head(cs, LOCAL_FREE_BUF_QUEUE.as_mut_ptr()) {
+                            LinkedListNode::insert_head(cs, FREE_BUF_QUEUE.as_mut_ptr(), node_ptr);
                         }
                     })
                 })
@@ -77,8 +75,8 @@ impl<'a> MemoryManager<'a> {
 impl<'a> evt::MemoryManager for MemoryManager<'a> {
     /// SAFETY: passing a pointer to something other than a managed event packet is UB
     unsafe fn drop_event_packet(evt: *mut EvtPacket) {
-        interrupt::free(|_| unsafe {
-            LinkedListNode::insert_head(LOCAL_FREE_BUF_QUEUE.as_mut_ptr(), evt as *mut _);
+        critical_section::with(|cs| unsafe {
+            LinkedListNode::insert_head(cs, LOCAL_FREE_BUF_QUEUE.as_mut_ptr(), evt as *mut _);
         });
 
         MM_WAKER.wake();
diff --git a/embassy-stm32-wpan/src/wb55/sub/sys.rs b/embassy-stm32-wpan/src/wb55/sub/sys.rs
index 4376314c7..2e625a677 100644
--- a/embassy-stm32-wpan/src/wb55/sub/sys.rs
+++ b/embassy-stm32-wpan/src/wb55/sub/sys.rs
@@ -87,10 +87,12 @@ impl<'a> Sys<'a> {
     /// This method takes the place of the `HW_IPCC_SYS_EvtNot`/`SysUserEvtRx`/`APPE_SysUserEvtRx`,
     /// as the embassy implementation avoids the need to call C public bindings, and instead
     /// handles the event channels directly.
-    pub async fn read<'b>(&mut self) -> EvtBox<mm::MemoryManager<'b>> {
+    pub async fn read(&mut self) -> EvtBox<mm::MemoryManager<'_>> {
         self.ipcc_system_event_channel
             .receive(|| unsafe {
-                if let Some(node_ptr) = LinkedListNode::remove_head(SYSTEM_EVT_QUEUE.as_mut_ptr()) {
+                if let Some(node_ptr) =
+                    critical_section::with(|cs| LinkedListNode::remove_head(cs, SYSTEM_EVT_QUEUE.as_mut_ptr()))
+                {
                     Some(EvtBox::new(node_ptr.cast()))
                 } else {
                     None
diff --git a/embassy-stm32-wpan/src/wb55/unsafe_linked_list.rs b/embassy-stm32-wpan/src/wb55/unsafe_linked_list.rs
index d8bc29763..c84ee1bb6 100644
--- a/embassy-stm32-wpan/src/wb55/unsafe_linked_list.rs
+++ b/embassy-stm32-wpan/src/wb55/unsafe_linked_list.rs
@@ -11,9 +11,10 @@
     unused_mut
 )]
 
+use core::fmt::Debug;
 use core::ptr;
 
-use cortex_m::interrupt;
+use critical_section::CriticalSection;
 
 #[derive(Copy, Clone)]
 #[repr(C, packed(4))]
@@ -42,216 +43,227 @@ impl LinkedListNode {
         );
     }
 
-    pub unsafe fn is_empty(mut p_list_head: *mut LinkedListNode) -> bool {
-        interrupt::free(|_| ptr::read_volatile(p_list_head).next == p_list_head)
+    pub unsafe fn is_empty(_cs: CriticalSection, mut p_list_head: *mut LinkedListNode) -> bool {
+        ptr::read_volatile(p_list_head).next == p_list_head
     }
 
     /// Insert `node` after `list_head` and before the next node
-    pub unsafe fn insert_head(mut p_list_head: *mut LinkedListNode, mut p_node: *mut LinkedListNode) {
-        interrupt::free(|_| {
-            let mut list_head = ptr::read_volatile(p_list_head);
-            if p_list_head != list_head.next {
-                let mut node_next = ptr::read_volatile(list_head.next);
-                let node = LinkedListNode {
-                    next: list_head.next,
-                    prev: p_list_head,
-                };
-
-                list_head.next = p_node;
-                node_next.prev = p_node;
-
-                // All nodes must be written because they will all be seen by another core
-                ptr::write_volatile(p_node, node);
-                ptr::write_volatile(node.next, node_next);
-                ptr::write_volatile(p_list_head, list_head);
-            } else {
-                let node = LinkedListNode {
-                    next: list_head.next,
-                    prev: p_list_head,
-                };
-
-                list_head.next = p_node;
-                list_head.prev = p_node;
-
-                // All nodes must be written because they will all be seen by another core
-                ptr::write_volatile(p_node, node);
-                ptr::write_volatile(p_list_head, list_head);
-            }
-        });
+    pub unsafe fn insert_head(
+        _cs: CriticalSection,
+        mut p_list_head: *mut LinkedListNode,
+        mut p_node: *mut LinkedListNode,
+    ) {
+        let mut list_head = ptr::read_volatile(p_list_head);
+        if p_list_head != list_head.next {
+            let mut node_next = ptr::read_volatile(list_head.next);
+            let node = LinkedListNode {
+                next: list_head.next,
+                prev: p_list_head,
+            };
+
+            list_head.next = p_node;
+            node_next.prev = p_node;
+
+            // All nodes must be written because they will all be seen by another core
+            ptr::write_volatile(p_node, node);
+            ptr::write_volatile(node.next, node_next);
+            ptr::write_volatile(p_list_head, list_head);
+        } else {
+            let node = LinkedListNode {
+                next: list_head.next,
+                prev: p_list_head,
+            };
+
+            list_head.next = p_node;
+            list_head.prev = p_node;
+
+            // All nodes must be written because they will all be seen by another core
+            ptr::write_volatile(p_node, node);
+            ptr::write_volatile(p_list_head, list_head);
+        }
     }
 
     /// Insert `node` before `list_tail` and after the second-to-last node
-    pub unsafe fn insert_tail(mut p_list_tail: *mut LinkedListNode, mut p_node: *mut LinkedListNode) {
-        interrupt::free(|_| {
-            let mut list_tail = ptr::read_volatile(p_list_tail);
-            if p_list_tail != list_tail.prev {
-                let mut node_prev = ptr::read_volatile(list_tail.prev);
-                let node = LinkedListNode {
-                    next: p_list_tail,
-                    prev: list_tail.prev,
-                };
-
-                list_tail.prev = p_node;
-                node_prev.next = p_node;
-
-                // All nodes must be written because they will all be seen by another core
-                ptr::write_volatile(p_node, node);
-                ptr::write_volatile(node.prev, node_prev);
-                ptr::write_volatile(p_list_tail, list_tail);
-            } else {
-                let node = LinkedListNode {
-                    next: p_list_tail,
-                    prev: list_tail.prev,
-                };
-
-                list_tail.prev = p_node;
-                list_tail.next = p_node;
-
-                // All nodes must be written because they will all be seen by another core
-                ptr::write_volatile(p_node, node);
-                ptr::write_volatile(p_list_tail, list_tail);
-            }
-        });
+    pub unsafe fn insert_tail(
+        _cs: CriticalSection,
+        mut p_list_tail: *mut LinkedListNode,
+        mut p_node: *mut LinkedListNode,
+    ) {
+        let mut list_tail = ptr::read_volatile(p_list_tail);
+        if p_list_tail != list_tail.prev {
+            let mut node_prev = ptr::read_volatile(list_tail.prev);
+            let node = LinkedListNode {
+                next: p_list_tail,
+                prev: list_tail.prev,
+            };
+
+            list_tail.prev = p_node;
+            node_prev.next = p_node;
+
+            // All nodes must be written because they will all be seen by another core
+            ptr::write_volatile(p_node, node);
+            ptr::write_volatile(node.prev, node_prev);
+            ptr::write_volatile(p_list_tail, list_tail);
+        } else {
+            let node = LinkedListNode {
+                next: p_list_tail,
+                prev: list_tail.prev,
+            };
+
+            list_tail.prev = p_node;
+            list_tail.next = p_node;
+
+            // All nodes must be written because they will all be seen by another core
+            ptr::write_volatile(p_node, node);
+            ptr::write_volatile(p_list_tail, list_tail);
+        }
     }
 
     /// Remove `node` from the linked list
-    pub unsafe fn remove_node(mut p_node: *mut LinkedListNode) {
-        interrupt::free(|_| {
-            // trace!("remove node: {:x}", p_node);
-            // apparently linked list nodes are not always aligned.
-            // if more hardfaults occur, more of these may need to be converted to unaligned.
-            let node = ptr::read_unaligned(p_node);
-            // trace!("remove node: prev/next {:x}/{:x}", node.prev, node.next);
-
-            if node.next != node.prev {
-                let mut node_next = ptr::read_volatile(node.next);
-                let mut node_prev = ptr::read_volatile(node.prev);
-
-                node_prev.next = node.next;
-                node_next.prev = node.prev;
-
-                ptr::write_volatile(node.next, node_next);
-                ptr::write_volatile(node.prev, node_prev);
-            } else {
-                let mut node_next = ptr::read_volatile(node.next);
-
-                node_next.next = node.next;
-                node_next.prev = node.prev;
-
-                ptr::write_volatile(node.next, node_next);
-            }
-        });
+    pub unsafe fn remove_node(_cs: CriticalSection, mut p_node: *mut LinkedListNode) {
+        let node = ptr::read_unaligned(p_node);
+
+        if node.next != node.prev {
+            let mut node_next = ptr::read_volatile(node.next);
+            let mut node_prev = ptr::read_volatile(node.prev);
+
+            node_prev.next = node.next;
+            node_next.prev = node.prev;
+
+            ptr::write_volatile(node.next, node_next);
+            ptr::write_volatile(node.prev, node_prev);
+        } else {
+            let mut node_next = ptr::read_volatile(node.next);
+
+            node_next.next = node.next;
+            node_next.prev = node.prev;
+
+            ptr::write_volatile(node.next, node_next);
+        }
     }
 
     /// Remove `list_head` and return a pointer to the `node`.
-    pub unsafe fn remove_head(mut p_list_head: *mut LinkedListNode) -> Option<*mut LinkedListNode> {
-        interrupt::free(|_| {
-            let list_head = ptr::read_volatile(p_list_head);
-
-            if list_head.next == p_list_head {
-                None
-            } else {
-                // Allowed because a removed node is not seen by another core
-                let p_node = list_head.next;
-                Self::remove_node(p_node);
-
-                Some(p_node)
-            }
-        })
+    pub unsafe fn remove_head(
+        _cs: CriticalSection,
+        mut p_list_head: *mut LinkedListNode,
+    ) -> Option<*mut LinkedListNode> {
+        let list_head = ptr::read_volatile(p_list_head);
+
+        if list_head.next == p_list_head {
+            None
+        } else {
+            // Allowed because a removed node is not seen by another core
+            let p_node = list_head.next;
+            Self::remove_node(_cs, p_node);
+
+            Some(p_node)
+        }
     }
 
     /// Remove `list_tail` and return a pointer to the `node`.
-    pub unsafe fn remove_tail(mut p_list_tail: *mut LinkedListNode) -> Option<*mut LinkedListNode> {
-        interrupt::free(|_| {
-            let list_tail = ptr::read_volatile(p_list_tail);
-
-            if list_tail.prev == p_list_tail {
-                None
-            } else {
-                // Allowed because a removed node is not seen by another core
-                let p_node = list_tail.prev;
-                Self::remove_node(p_node);
-
-                Some(p_node)
-            }
-        })
-    }
+    pub unsafe fn remove_tail(
+        _cs: CriticalSection,
+        mut p_list_tail: *mut LinkedListNode,
+    ) -> Option<*mut LinkedListNode> {
+        let list_tail = ptr::read_volatile(p_list_tail);
+
+        if list_tail.prev == p_list_tail {
+            None
+        } else {
+            // Allowed because a removed node is not seen by another core
+            let p_node = list_tail.prev;
+            Self::remove_node(_cs, p_node);
 
-    pub unsafe fn insert_node_after(mut node: *mut LinkedListNode, mut ref_node: *mut LinkedListNode) {
-        interrupt::free(|_| {
-            (*node).next = (*ref_node).next;
-            (*node).prev = ref_node;
-            (*ref_node).next = node;
-            (*(*node).next).prev = node;
-        });
+            Some(p_node)
+        }
+    }
 
-        todo!("this function has not been converted to volatile semantics");
+    pub unsafe fn insert_node_after(
+        _cs: CriticalSection,
+        mut p_node: *mut LinkedListNode,
+        mut p_ref_node: *mut LinkedListNode,
+    ) {
+        let mut node = ptr::read_volatile(p_node);
+        let mut ref_node = ptr::read_volatile(p_ref_node);
+        let mut prev_node = ptr::read_volatile(ref_node.next);
+
+        node.next = ref_node.next;
+        node.prev = p_ref_node;
+        ref_node.next = p_node;
+        prev_node.prev = p_node;
+
+        ptr::write_volatile(p_node, node);
+        ptr::write_volatile(p_ref_node, ref_node);
+        ptr::write_volatile(node.next, prev_node);
     }
 
-    pub unsafe fn insert_node_before(mut node: *mut LinkedListNode, mut ref_node: *mut LinkedListNode) {
-        interrupt::free(|_| {
-            (*node).next = ref_node;
-            (*node).prev = (*ref_node).prev;
-            (*ref_node).prev = node;
-            (*(*node).prev).next = node;
-        });
+    pub unsafe fn insert_node_before(
+        _cs: CriticalSection,
+        mut node: *mut LinkedListNode,
+        mut ref_node: *mut LinkedListNode,
+    ) {
+        (*node).next = ref_node;
+        (*node).prev = (*ref_node).prev;
+        (*ref_node).prev = node;
+        (*(*node).prev).next = node;
 
         todo!("this function has not been converted to volatile semantics");
     }
 
-    pub unsafe fn get_size(mut list_head: *mut LinkedListNode) -> usize {
-        interrupt::free(|_| {
-            let mut size = 0;
-            let mut temp: *mut LinkedListNode = core::ptr::null_mut::<LinkedListNode>();
+    pub unsafe fn get_size(_cs: CriticalSection, mut list_head: *mut LinkedListNode) -> usize {
+        let mut size = 0;
+        let mut temp: *mut LinkedListNode = core::ptr::null_mut::<LinkedListNode>();
 
-            temp = (*list_head).next;
-            while temp != list_head {
-                size += 1;
-                temp = (*temp).next
-            }
+        temp = (*list_head).next;
+        while temp != list_head {
+            size += 1;
+            temp = (*temp).next
+        }
 
-            size
-        });
+        let _ = size;
 
         todo!("this function has not been converted to volatile semantics");
     }
 
-    pub unsafe fn get_next_node(mut p_ref_node: *mut LinkedListNode) -> *mut LinkedListNode {
-        interrupt::free(|_| {
-            let ref_node = ptr::read_volatile(p_ref_node);
+    pub unsafe fn get_next_node(_cs: CriticalSection, mut p_ref_node: *mut LinkedListNode) -> *mut LinkedListNode {
+        let ref_node = ptr::read_volatile(p_ref_node);
 
-            // Allowed because a removed node is not seen by another core
-            ref_node.next
-        })
+        // Allowed because a removed node is not seen by another core
+        ref_node.next
     }
 
-    pub unsafe fn get_prev_node(mut p_ref_node: *mut LinkedListNode) -> *mut LinkedListNode {
-        interrupt::free(|_| {
-            let ref_node = ptr::read_volatile(p_ref_node);
+    pub unsafe fn get_prev_node(_cs: CriticalSection, mut p_ref_node: *mut LinkedListNode) -> *mut LinkedListNode {
+        let ref_node = ptr::read_volatile(p_ref_node);
 
-            // Allowed because a removed node is not seen by another core
-            ref_node.prev
-        })
+        // Allowed because a removed node is not seen by another core
+        ref_node.prev
     }
 }
 
-#[allow(dead_code)]
-unsafe fn debug_linked_list(mut p_node: *mut LinkedListNode) {
-    info!("iterating list from node: {:x}", p_node);
-    let mut p_current_node = p_node;
-    let mut i = 0;
-    loop {
-        let current_node = ptr::read_volatile(p_current_node);
-        info!(
-            "node (prev, current, next): {:x}, {:x}, {:x}",
-            current_node.prev, p_current_node, current_node.next
-        );
+pub struct DebuggableLinkedListNode(*const LinkedListNode);
+
+impl Debug for DebuggableLinkedListNode {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        // Safe because this is just reading memory, and using unaligned to do it
+        let p_node = self.0;
+
+        f.write_fmt(format_args!("iterating list from node: {:x}", p_node as usize))?;
+
+        let mut p_current_node = p_node;
+        for _ in 0..30 {
+            let current_node = unsafe { ptr::read_unaligned(p_current_node) };
+            f.write_fmt(format_args!(
+                "node (prev, current, next): {:x}, {:x}, {:x}",
+                current_node.prev as usize, p_current_node as usize, current_node.next as usize
+            ))?;
+
+            if current_node.next == p_node as *mut _ {
+                break;
+            }
 
-        i += 1;
-        if i > 10 || current_node.next == p_node {
-            break;
+            p_current_node = current_node.next;
         }
 
-        p_current_node = current_node.next;
+        Ok(())
     }
 }
diff --git a/embassy-stm32-wpan/src/wba/linklayer_plat.rs b/embassy-stm32-wpan/src/wba/linklayer_plat.rs
index c011b3bcb..e6a342b52 100644
--- a/embassy-stm32-wpan/src/wba/linklayer_plat.rs
+++ b/embassy-stm32-wpan/src/wba/linklayer_plat.rs
@@ -1,6 +1,3 @@
-#[allow(dead_code)]
-fn test_fn() {}
-
 // /* USER CODE BEGIN Header */
 // /**
 //   ******************************************************************************
@@ -72,131 +69,339 @@ fn test_fn() {}
 // uint8_t AHB5_SwitchedOff = 0;
 // uint32_t radio_sleep_timer_val = 0;
 //
+// /* USER CODE BEGIN LINKLAYER_PLAT 0 */
+//
+// /* USER CODE END LINKLAYER_PLAT 0 */
+#![cfg(feature = "wba")]
+#![allow(clippy::missing_safety_doc)]
+
+use core::hint::spin_loop;
+use core::ptr;
+use core::sync::atomic::{AtomicBool, AtomicI32, AtomicPtr, AtomicU32, Ordering};
+
+use cortex_m::asm::{dsb, isb};
+use cortex_m::interrupt::InterruptNumber;
+use cortex_m::peripheral::NVIC;
+use cortex_m::register::basepri;
+use critical_section;
+#[cfg(feature = "defmt")]
+use defmt::trace;
+use embassy_stm32::NVIC_PRIO_BITS;
+use embassy_time::{Duration, block_for};
+
+use super::bindings::{link_layer, mac};
+
+// Missing constant from stm32-bindings - RADIO_SW_LOW interrupt number
+// For STM32WBA, this is typically RADIO_IRQ_BUSY (interrupt 43)
+const RADIO_SW_LOW_INTR_NUM: u32 = 43;
+
+type Callback = unsafe extern "C" fn();
+
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[repr(transparent)]
+struct RawInterrupt(u16);
+
+impl RawInterrupt {
+    fn new(irq: u32) -> Self {
+        debug_assert!(irq <= u16::MAX as u32);
+        Self(irq as u16)
+    }
+}
+
+impl From<u32> for RawInterrupt {
+    fn from(value: u32) -> Self {
+        Self::new(value)
+    }
+}
+
+unsafe impl InterruptNumber for RawInterrupt {
+    fn number(self) -> u16 {
+        self.0
+    }
+}
+
+static RADIO_CALLBACK: AtomicPtr<()> = AtomicPtr::new(ptr::null_mut());
+static LOW_ISR_CALLBACK: AtomicPtr<()> = AtomicPtr::new(ptr::null_mut());
+
+static IRQ_COUNTER: AtomicI32 = AtomicI32::new(0);
+
+static PRIO_HIGH_ISR_COUNTER: AtomicI32 = AtomicI32::new(0);
+static PRIO_LOW_ISR_COUNTER: AtomicI32 = AtomicI32::new(0);
+static PRIO_SYS_ISR_COUNTER: AtomicI32 = AtomicI32::new(0);
+static LOCAL_BASEPRI_VALUE: AtomicU32 = AtomicU32::new(0);
+
+static RADIO_SW_LOW_ISR_RUNNING_HIGH_PRIO: AtomicBool = AtomicBool::new(false);
+static AHB5_SWITCHED_OFF: AtomicBool = AtomicBool::new(false);
+static RADIO_SLEEP_TIMER_VAL: AtomicU32 = AtomicU32::new(0);
+
+static PRNG_STATE: AtomicU32 = AtomicU32::new(0);
+static PRNG_INIT: AtomicBool = AtomicBool::new(false);
+
+// Critical-section restore token for IRQ enable/disable pairing.
+// Only written when the IRQ disable counter transitions 0->1, and consumed when it transitions 1->0.
+static mut CS_RESTORE_STATE: Option<critical_section::RestoreState> = None;
+
+fn read_system_core_clock() -> u32 {
+    0
+}
+
+fn store_callback(slot: &AtomicPtr<()>, cb: Option<Callback>) {
+    let ptr = cb.map_or(ptr::null_mut(), |f| f as *mut ());
+    slot.store(ptr, Ordering::Release);
+}
+
+fn load_callback(slot: &AtomicPtr<()>) -> Option<Callback> {
+    let ptr = slot.load(Ordering::Acquire);
+    if ptr.is_null() {
+        None
+    } else {
+        Some(unsafe { core::mem::transmute::<*mut (), Callback>(ptr) })
+    }
+}
+
+fn priority_shift() -> u8 {
+    8 - NVIC_PRIO_BITS as u8
+}
+
+fn pack_priority(raw: u32) -> u8 {
+    let shift = priority_shift();
+    let priority_bits = NVIC_PRIO_BITS as u32;
+    let mask = if priority_bits >= 32 {
+        u32::MAX
+    } else {
+        (1u32 << priority_bits) - 1
+    };
+    let clamped = raw & mask;
+    (clamped << u32::from(shift)) as u8
+}
+
+fn counter_release(counter: &AtomicI32) -> bool {
+    counter.fetch_sub(1, Ordering::SeqCst) <= 1
+}
+
+fn counter_acquire(counter: &AtomicI32) -> bool {
+    counter.fetch_add(1, Ordering::SeqCst) == 0
+}
+
+unsafe fn nvic_enable(irq: u32) {
+    NVIC::unmask(RawInterrupt::new(irq));
+    dsb();
+    isb();
+}
+
+unsafe fn nvic_disable(irq: u32) {
+    NVIC::mask(RawInterrupt::new(irq));
+    dsb();
+    isb();
+}
+
+unsafe fn nvic_set_pending(irq: u32) {
+    NVIC::pend(RawInterrupt::new(irq));
+    dsb();
+    isb();
+}
+
+unsafe fn nvic_get_active(irq: u32) -> bool {
+    NVIC::is_active(RawInterrupt::new(irq))
+}
+
+unsafe fn nvic_set_priority(irq: u32, priority: u8) {
+    // STM32WBA is ARMv8-M, which uses byte-accessible IPR registers
+    let nvic = &*NVIC::PTR;
+    nvic.ipr[irq as usize].write(priority);
+
+    dsb();
+    isb();
+}
+
+fn set_basepri_max(value: u8) {
+    unsafe {
+        if basepri::read() < value {
+            basepri::write(value);
+        }
+    }
+}
+
+fn prng_next() -> u32 {
+    #[inline]
+    fn xorshift(mut x: u32) -> u32 {
+        x ^= x << 13;
+        x ^= x >> 17;
+        x ^= x << 5;
+        x
+    }
+
+    if !PRNG_INIT.load(Ordering::Acquire) {
+        let seed = unsafe {
+            let timer = link_layer::ll_intf_cmn_get_slptmr_value();
+            let core_clock = read_system_core_clock();
+            timer ^ core_clock ^ 0x6C8E_9CF5
+        };
+        PRNG_STATE.store(seed, Ordering::Relaxed);
+        PRNG_INIT.store(true, Ordering::Release);
+    }
+
+    let mut current = PRNG_STATE.load(Ordering::Relaxed);
+    loop {
+        let next = xorshift(current);
+        match PRNG_STATE.compare_exchange_weak(current, next, Ordering::AcqRel, Ordering::Relaxed) {
+            Ok(_) => return next,
+            Err(v) => current = v,
+        }
+    }
+}
+
+pub unsafe fn run_radio_high_isr() {
+    if let Some(cb) = load_callback(&RADIO_CALLBACK) {
+        cb();
+    }
+}
+
+pub unsafe fn run_radio_sw_low_isr() {
+    if let Some(cb) = load_callback(&LOW_ISR_CALLBACK) {
+        cb();
+    }
+
+    if RADIO_SW_LOW_ISR_RUNNING_HIGH_PRIO.swap(false, Ordering::AcqRel) {
+        nvic_set_priority(RADIO_SW_LOW_INTR_NUM, pack_priority(mac::RADIO_SW_LOW_INTR_PRIO));
+    }
+}
+
 // /**
 //   * @brief  Configure the necessary clock sources for the radio.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_ClockInit()
-// {
-//   uint32_t linklayer_slp_clk_src = LL_RCC_RADIOSLEEPSOURCE_NONE;
-//
-//   /* Get the Link Layer sleep timer clock source */
-//   linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource();
-//   if(linklayer_slp_clk_src == LL_RCC_RADIOSLEEPSOURCE_NONE)
-//   {
-//     /* If there is no clock source defined, should be selected before */
-//     assert_param(0);
-//   }
-//
-//   /* Enable AHB5ENR peripheral clock (bus CLK) */
-//   __HAL_RCC_RADIO_CLK_ENABLE();
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_ClockInit() {
+    //   uint32_t linklayer_slp_clk_src = LL_RCC_RADIOSLEEPSOURCE_NONE;
+    //
+    //   /* Get the Link Layer sleep timer clock source */
+    //   linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource();
+    //   if(linklayer_slp_clk_src == LL_RCC_RADIOSLEEPSOURCE_NONE)
+    //   {
+    //     /* If there is no clock source defined, should be selected before */
+    //     assert_param(0);
+    //   }
+    //
+    //   /* Enable AHB5ENR peripheral clock (bus CLK) */
+    //   __HAL_RCC_RADIO_CLK_ENABLE();
+    trace!("LINKLAYER_PLAT_ClockInit: get_slptmr_value");
+    let _ = link_layer::ll_intf_cmn_get_slptmr_value();
+}
+
 // /**
 //   * @brief  Link Layer active waiting loop.
 //   * @param  delay: delay in us
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_DelayUs(uint32_t delay)
-// {
-//   static uint8_t lock = 0;
-//   uint32_t t0;
-//   uint32_t primask_bit;
-//
-//   /* Enter critical section */
-//   primask_bit= __get_PRIMASK();
-//   __disable_irq();
-//
-//   if (lock == 0U)
-//   {
-//     /* Initialize counter */
-//     /* Reset cycle counter to prevent overflow
-//        As a us counter, it is assumed than even with re-entrancy,
-//        overflow will never happen before re-initializing this counter */
-//     DWT->CYCCNT = 0U;
-//     /* Enable DWT by safety but should be useless (as already set) */
-//     SET_BIT(DCB->DEMCR, DCB_DEMCR_TRCENA_Msk);
-//     /* Enable counter */
-//     SET_BIT(DWT->CTRL, DWT_CTRL_CYCCNTENA_Msk);
-//   }
-//   /* Increment 're-entrance' counter */
-//   lock++;
-//   /* Get starting time stamp */
-//   t0 = DWT->CYCCNT;
-//   /* Exit critical section */
-//  __set_PRIMASK(primask_bit);
-//
-//   /* Turn us into cycles */
-//   delay = delay * (SystemCoreClock / 1000000U);
-//   delay += t0;
-//
-//   /* Busy waiting loop */
-//   while (DWT->CYCCNT < delay)
-//   {
-//   };
-//
-//   /* Enter critical section */
-//   primask_bit= __get_PRIMASK();
-//   __disable_irq();
-//   if (lock == 1U)
-//   {
-//     /* Disable counter */
-//     CLEAR_BIT(DWT->CTRL, DWT_CTRL_CYCCNTENA_Msk);
-//   }
-//   /* Decrement 're-entrance' counter */
-//   lock--;
-//   /* Exit critical section */
-//  __set_PRIMASK(primask_bit);
-//
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_DelayUs(delay: u32) {
+    //   static uint8_t lock = 0;
+    //   uint32_t t0;
+    //   uint32_t primask_bit;
+    //
+    //   /* Enter critical section */
+    //   primask_bit= __get_PRIMASK();
+    //   __disable_irq();
+    //
+    //   if (lock == 0U)
+    //   {
+    //     /* Initialize counter */
+    //     /* Reset cycle counter to prevent overflow
+    //        As a us counter, it is assumed than even with re-entrancy,
+    //        overflow will never happen before re-initializing this counter */
+    //     DWT->CYCCNT = 0U;
+    //     /* Enable DWT by safety but should be useless (as already set) */
+    //     SET_BIT(DCB->DEMCR, DCB_DEMCR_TRCENA_Msk);
+    //     /* Enable counter */
+    //     SET_BIT(DWT->CTRL, DWT_CTRL_CYCCNTENA_Msk);
+    //   }
+    //   /* Increment 're-entrance' counter */
+    //   lock++;
+    //   /* Get starting time stamp */
+    //   t0 = DWT->CYCCNT;
+    //   /* Exit critical section */
+    //  __set_PRIMASK(primask_bit);
+    //
+    //   /* Turn us into cycles */
+    //   delay = delay * (SystemCoreClock / 1000000U);
+    //   delay += t0;
+    //
+    //   /* Busy waiting loop */
+    //   while (DWT->CYCCNT < delay)
+    //   {
+    //   };
+    //
+    //   /* Enter critical section */
+    //   primask_bit= __get_PRIMASK();
+    //   __disable_irq();
+    //   if (lock == 1U)
+    //   {
+    //     /* Disable counter */
+    //     CLEAR_BIT(DWT->CTRL, DWT_CTRL_CYCCNTENA_Msk);
+    //   }
+    //   /* Decrement 're-entrance' counter */
+    //   lock--;
+    //   /* Exit critical section */
+    //  __set_PRIMASK(primask_bit);
+    //
+    trace!("LINKLAYER_PLAT_DelayUs: delay={}", delay);
+    block_for(Duration::from_micros(u64::from(delay)));
+}
+
 // /**
 //   * @brief  Link Layer assertion API
 //   * @param  condition: conditional statement to be checked.
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_Assert(uint8_t condition)
-// {
-//   assert_param(condition);
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_Assert(condition: u8) {
+    if condition == 0 {
+        panic!("LINKLAYER_PLAT assertion failed");
+    }
+}
+
 // /**
 //   * @brief  Enable/disable the Link Layer active clock (baseband clock).
 //   * @param  enable: boolean value to enable (1) or disable (0) the clock.
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_WaitHclkRdy(void)
-// {
-//   /* Wait on radio bus clock readiness if it has been turned of */
-//   if (AHB5_SwitchedOff == 1)
-//   {
-//     AHB5_SwitchedOff = 0;
-//     while (radio_sleep_timer_val == ll_intf_cmn_get_slptmr_value());
-//   }
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_WaitHclkRdy() {
+    trace!("LINKLAYER_PLAT_WaitHclkRdy");
+    if AHB5_SWITCHED_OFF.swap(false, Ordering::AcqRel) {
+        let reference = RADIO_SLEEP_TIMER_VAL.load(Ordering::Acquire);
+        trace!("LINKLAYER_PLAT_WaitHclkRdy: reference={}", reference);
+        while reference == link_layer::ll_intf_cmn_get_slptmr_value() {
+            spin_loop();
+        }
+    }
+}
+
 // /**
 //   * @brief  Notify the Link Layer platform layer the system will enter in WFI
 //   *         and AHB5 clock may be turned of regarding the 2.4Ghz radio state.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_NotifyWFIEnter(void)
-// {
-//   /* Check if Radio state will allow the AHB5 clock to be cut */
-//
-//   /* AHB5 clock will be cut in the following cases:
-//    * - 2.4GHz radio is not in ACTIVE mode (in SLEEP or DEEPSLEEP mode).
-//    * - RADIOSMEN and STRADIOCLKON bits are at 0.
-//    */
-//   if((LL_PWR_GetRadioMode() != LL_PWR_RADIO_ACTIVE_MODE) ||
-//      ((__HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() == 0) && (LL_RCC_RADIO_IsEnabledSleepTimerClock() == 0)))
-//   {
-//     AHB5_SwitchedOff = 1;
-//   }
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_NotifyWFIEnter() {
+    //   /* Check if Radio state will allow the AHB5 clock to be cut */
+    //
+    //   /* AHB5 clock will be cut in the following cases:
+    //    * - 2.4GHz radio is not in ACTIVE mode (in SLEEP or DEEPSLEEP mode).
+    //    * - RADIOSMEN and STRADIOCLKON bits are at 0.
+    //    */
+    //   if((LL_PWR_GetRadioMode() != LL_PWR_RADIO_ACTIVE_MODE) ||
+    //      ((__HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() == 0) && (LL_RCC_RADIO_IsEnabledSleepTimerClock() == 0)))
+    //   {
+    //     AHB5_SwitchedOff = 1;
+    //   }
+    trace!("LINKLAYER_PLAT_NotifyWFIEnter");
+    AHB5_SWITCHED_OFF.store(true, Ordering::Release);
+}
+
 // /**
 //   * @brief  Notify the Link Layer platform layer the system exited WFI and AHB5
 //   *         clock may be resynchronized as is may have been turned of during
@@ -204,172 +409,202 @@ fn test_fn() {}
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_NotifyWFIExit(void)
-// {
-//   /* Check if AHB5 clock has been turned of and needs resynchronisation */
-//   if (AHB5_SwitchedOff)
-//   {
-//     /* Read sleep register as earlier as possible */
-//     radio_sleep_timer_val = ll_intf_cmn_get_slptmr_value();
-//   }
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_NotifyWFIExit() {
+    trace!("LINKLAYER_PLAT_NotifyWFIExit");
+    //   /* Check if AHB5 clock has been turned of and needs resynchronisation */
+    if AHB5_SWITCHED_OFF.load(Ordering::Acquire) {
+        //     /* Read sleep register as earlier as possible */
+        let value = link_layer::ll_intf_cmn_get_slptmr_value();
+        RADIO_SLEEP_TIMER_VAL.store(value, Ordering::Release);
+    }
+}
+
 // /**
 //   * @brief  Active wait on bus clock readiness.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_AclkCtrl(uint8_t enable)
-// {
-//   if(enable != 0u)
-//   {
-// #if (CFG_SCM_SUPPORTED == 1)
-//     /* SCM HSE BEGIN */
-//     /* Polling on HSE32 activation */
-//     SCM_HSE_WaitUntilReady();
-//     /* Enable RADIO baseband clock (active CLK) */
-//     HAL_RCCEx_EnableRadioBBClock();
-//     /* SCM HSE END */
-// #else
-//     /* Enable RADIO baseband clock (active CLK) */
-//     HAL_RCCEx_EnableRadioBBClock();
-//     /* Polling on HSE32 activation */
-//     while ( LL_RCC_HSE_IsReady() == 0);
-// #endif /* CFG_SCM_SUPPORTED */
-//   }
-//   else
-//   {
-//     /* Disable RADIO baseband clock (active CLK) */
-//     HAL_RCCEx_DisableRadioBBClock();
-//   }
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_AclkCtrl(_enable: u8) {
+    trace!("LINKLAYER_PLAT_AclkCtrl: enable={}", _enable);
+    if _enable != 0 {
+        // #if (CFG_SCM_SUPPORTED == 1)
+        //     /* SCM HSE BEGIN */
+        //     /* Polling on HSE32 activation */
+        //     SCM_HSE_WaitUntilReady();
+        //     /* Enable RADIO baseband clock (active CLK) */
+        //     HAL_RCCEx_EnableRadioBBClock();
+        //     /* SCM HSE END */
+        // #else
+        //     /* Enable RADIO baseband clock (active CLK) */
+        //     HAL_RCCEx_EnableRadioBBClock();
+        //     /* Polling on HSE32 activation */
+        //     while ( LL_RCC_HSE_IsReady() == 0);
+        // #endif /* CFG_SCM_SUPPORTED */
+        // NOTE: Add a proper assertion once a typed `Radio` peripheral exists in embassy-stm32
+        // that exposes the baseband clock enable status via RCC.
+    } else {
+        //     /* Disable RADIO baseband clock (active CLK) */
+        //     HAL_RCCEx_DisableRadioBBClock();
+    }
+}
+
 // /**
 //   * @brief  Link Layer RNG request.
 //   * @param  ptr_rnd: pointer to the variable that hosts the number.
 //   * @param  len: number of byte of anthropy to get.
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_GetRNG(uint8_t *ptr_rnd, uint32_t len)
-// {
-//   uint32_t nb_remaining_rng = len;
-//   uint32_t generated_rng;
-//
-//   /* Get the requested RNGs (4 bytes by 4bytes) */
-//   while(nb_remaining_rng >= 4)
-//   {
-//     generated_rng = 0;
-//     HW_RNG_Get(1, &generated_rng);
-//     memcpy((ptr_rnd+(len-nb_remaining_rng)), &generated_rng, 4);
-//     nb_remaining_rng -=4;
-//   }
-//
-//   /* Get the remaining number of RNGs */
-//   if(nb_remaining_rng>0){
-//     generated_rng = 0;
-//     HW_RNG_Get(1, &generated_rng);
-//     memcpy((ptr_rnd+(len-nb_remaining_rng)), &generated_rng, nb_remaining_rng);
-//   }
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_GetRNG(ptr_rnd: *mut u8, len: u32) {
+    //   uint32_t nb_remaining_rng = len;
+    //   uint32_t generated_rng;
+    //
+    //   /* Get the requested RNGs (4 bytes by 4bytes) */
+    //   while(nb_remaining_rng >= 4)
+    //   {
+    //     generated_rng = 0;
+    //     HW_RNG_Get(1, &generated_rng);
+    //     memcpy((ptr_rnd+(len-nb_remaining_rng)), &generated_rng, 4);
+    //     nb_remaining_rng -=4;
+    //   }
+    //
+    //   /* Get the remaining number of RNGs */
+    //   if(nb_remaining_rng>0){
+    //     generated_rng = 0;
+    //     HW_RNG_Get(1, &generated_rng);
+    //     memcpy((ptr_rnd+(len-nb_remaining_rng)), &generated_rng, nb_remaining_rng);
+    //   }
+    trace!("LINKLAYER_PLAT_GetRNG: ptr_rnd={:?}, len={}", ptr_rnd, len);
+    if ptr_rnd.is_null() || len == 0 {
+        return;
+    }
+
+    for i in 0..len {
+        let byte = (prng_next() >> ((i & 3) * 8)) as u8;
+        ptr::write_volatile(ptr_rnd.add(i as usize), byte);
+    }
+}
+
 // /**
 //   * @brief  Initialize Link Layer radio high priority interrupt.
 //   * @param  intr_cb: function pointer to assign for the radio high priority ISR routine.
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_SetupRadioIT(void (*intr_cb)())
-// {
-//   radio_callback = intr_cb;
-//   HAL_NVIC_SetPriority((IRQn_Type) RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH, 0);
-//   HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_INTR_NUM);
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_SetupRadioIT(intr_cb: Option<Callback>) {
+    trace!("LINKLAYER_PLAT_SetupRadioIT: intr_cb={:?}", intr_cb);
+    store_callback(&RADIO_CALLBACK, intr_cb);
+
+    if intr_cb.is_some() {
+        nvic_set_priority(mac::RADIO_INTR_NUM, pack_priority(mac::RADIO_INTR_PRIO_HIGH));
+        nvic_enable(mac::RADIO_INTR_NUM);
+    } else {
+        nvic_disable(mac::RADIO_INTR_NUM);
+    }
+}
+
 // /**
 //   * @brief  Initialize Link Layer SW low priority interrupt.
 //   * @param  intr_cb: function pointer to assign for the SW low priority ISR routine.
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_SetupSwLowIT(void (*intr_cb)())
-// {
-//   low_isr_callback = intr_cb;
-//
-//   HAL_NVIC_SetPriority((IRQn_Type) RADIO_SW_LOW_INTR_NUM, RADIO_SW_LOW_INTR_PRIO, 0);
-//   HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_SW_LOW_INTR_NUM);
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_SetupSwLowIT(intr_cb: Option<Callback>) {
+    trace!("LINKLAYER_PLAT_SetupSwLowIT: intr_cb={:?}", intr_cb);
+    store_callback(&LOW_ISR_CALLBACK, intr_cb);
+
+    if intr_cb.is_some() {
+        nvic_set_priority(RADIO_SW_LOW_INTR_NUM, pack_priority(mac::RADIO_SW_LOW_INTR_PRIO));
+        nvic_enable(RADIO_SW_LOW_INTR_NUM);
+    } else {
+        nvic_disable(RADIO_SW_LOW_INTR_NUM);
+    }
+}
+
 // /**
 //   * @brief  Trigger the link layer SW low interrupt.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_TriggerSwLowIT(uint8_t priority)
-// {
-//   uint8_t low_isr_priority = RADIO_INTR_PRIO_LOW;
-//
-//   /* Check if a SW low interrupt as already been raised.
-//    * Nested call far radio low isr are not supported
-//    **/
-//
-//   if(NVIC_GetActive(RADIO_SW_LOW_INTR_NUM) == 0)
-//   {
-//     /* No nested SW low ISR, default behavior */
-//
-//     if(priority == 0)
-//     {
-//       low_isr_priority = RADIO_SW_LOW_INTR_PRIO;
-//     }
-//
-//     HAL_NVIC_SetPriority((IRQn_Type) RADIO_SW_LOW_INTR_NUM, low_isr_priority, 0);
-//   }
-//   else
-//   {
-//     /* Nested call detected */
-//     /* No change for SW radio low interrupt priority for the moment */
-//
-//     if(priority != 0)
-//     {
-//       /* At the end of current SW radio low ISR, this pending SW low interrupt
-//        * will run with RADIO_INTR_PRIO_LOW priority
-//        **/
-//       radio_sw_low_isr_is_running_high_prio = 1;
-//     }
-//   }
-//
-//   HAL_NVIC_SetPendingIRQ((IRQn_Type) RADIO_SW_LOW_INTR_NUM);
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_TriggerSwLowIT(priority: u8) {
+    trace!("LINKLAYER_PLAT_TriggerSwLowIT: priority={}", priority);
+    let active = nvic_get_active(RADIO_SW_LOW_INTR_NUM);
+
+    //   /* Check if a SW low interrupt as already been raised.
+    //    * Nested call far radio low isr are not supported
+    //    **/
+    if !active {
+        let prio = if priority == 0 {
+            //     /* No nested SW low ISR, default behavior */
+            pack_priority(mac::RADIO_SW_LOW_INTR_PRIO)
+        } else {
+            pack_priority(mac::RADIO_INTR_PRIO_LOW)
+        };
+        nvic_set_priority(RADIO_SW_LOW_INTR_NUM, prio);
+    } else if priority != 0 {
+        //     /* Nested call detected */
+        //     /* No change for SW radio low interrupt priority for the moment */
+        //
+        //     if(priority != 0)
+        //     {
+        //       /* At the end of current SW radio low ISR, this pending SW low interrupt
+        //        * will run with RADIO_INTR_PRIO_LOW priority
+        //        **/
+        //       radio_sw_low_isr_is_running_high_prio = 1;
+        //     }
+        RADIO_SW_LOW_ISR_RUNNING_HIGH_PRIO.store(true, Ordering::Release);
+    }
+
+    nvic_set_pending(RADIO_SW_LOW_INTR_NUM);
+}
+
 // /**
 //   * @brief  Enable interrupts.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_EnableIRQ(void)
-// {
-//   irq_counter = max(0,irq_counter-1);
-//
-//   if(irq_counter == 0)
-//   {
-//     /* When irq_counter reaches 0, restore primask bit */
-//     __set_PRIMASK(primask_bit);
-//   }
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_EnableIRQ() {
+    trace!("LINKLAYER_PLAT_EnableIRQ");
+    //   irq_counter = max(0,irq_counter-1);
+    //
+    //   if(irq_counter == 0)
+    //   {
+    //     /* When irq_counter reaches 0, restore primask bit */
+    //     __set_PRIMASK(primask_bit);
+    //   }
+    if counter_release(&IRQ_COUNTER) {
+        // When the counter reaches zero, restore prior interrupt state using the captured token.
+        if let Some(token) = CS_RESTORE_STATE.take() {
+            critical_section::release(token);
+        }
+    }
+}
+
 // /**
 //   * @brief  Disable interrupts.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_DisableIRQ(void)
-// {
-//   if(irq_counter == 0)
-//   {
-//     /* Save primask bit at first interrupt disablement */
-//     primask_bit= __get_PRIMASK();
-//   }
-//   __disable_irq();
-//   irq_counter ++;
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_DisableIRQ() {
+    trace!("LINKLAYER_PLAT_DisableIRQ");
+    //   if(irq_counter == 0)
+    //   {
+    //     /* Save primask bit at first interrupt disablement */
+    //     primask_bit= __get_PRIMASK();
+    //   }
+    //   __disable_irq();
+    //   irq_counter ++;
+    if counter_acquire(&IRQ_COUNTER) {
+        // Capture and disable using critical-section API on first disable.
+        CS_RESTORE_STATE = Some(critical_section::acquire());
+    }
+}
+
 // /**
 //   * @brief  Enable specific interrupt group.
 //   * @param  isr_type: mask for interrupt group to enable.
@@ -380,43 +615,62 @@ fn test_fn() {}
 //   *              lower priority that link layer SW low interrupt.
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_EnableSpecificIRQ(uint8_t isr_type)
-// {
-//   if( (isr_type & LL_HIGH_ISR_ONLY) != 0 )
-//   {
-//     prio_high_isr_counter--;
-//     if(prio_high_isr_counter == 0)
-//     {
-//       /* When specific counter for link layer high ISR reaches 0, interrupt is enabled */
-//       HAL_NVIC_EnableIRQ(RADIO_INTR_NUM);
-//       /* USER CODE BEGIN LINKLAYER_PLAT_EnableSpecificIRQ_1 */
-//
-//       /* USER CODE END LINKLAYER_PLAT_EnableSpecificIRQ_1 */
-//     }
-//   }
-//
-//   if( (isr_type & LL_LOW_ISR_ONLY) != 0 )
-//   {
-//     prio_low_isr_counter--;
-//     if(prio_low_isr_counter == 0)
-//     {
-//       /* When specific counter for link layer SW low ISR reaches 0, interrupt is enabled */
-//       HAL_NVIC_EnableIRQ(RADIO_SW_LOW_INTR_NUM);
-//     }
-//
-//   }
-//
-//   if( (isr_type & SYS_LOW_ISR) != 0 )
-//   {
-//     prio_sys_isr_counter--;
-//     if(prio_sys_isr_counter == 0)
-//     {
-//       /* Restore basepri value */
-//       __set_BASEPRI(local_basepri_value);
-//     }
-//   }
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_EnableSpecificIRQ(isr_type: u8) {
+    trace!("LINKLAYER_PLAT_EnableSpecificIRQ: isr_type={}", isr_type);
+    //   if( (isr_type & LL_HIGH_ISR_ONLY) != 0 )
+    //   {
+    //     prio_high_isr_counter--;
+    //     if(prio_high_isr_counter == 0)
+    //     {
+    //       /* When specific counter for link layer high ISR reaches 0, interrupt is enabled */
+    //       HAL_NVIC_EnableIRQ(RADIO_INTR_NUM);
+    //       /* USER CODE BEGIN LINKLAYER_PLAT_EnableSpecificIRQ_1 */
+    //
+    //       /* USER CODE END LINKLAYER_PLAT_EnableSpecificIRQ_1 */
+    //     }
+    //   }
+    //
+    //   if( (isr_type & LL_LOW_ISR_ONLY) != 0 )
+    //   {
+    //     prio_low_isr_counter--;
+    //     if(prio_low_isr_counter == 0)
+    //     {
+    //       /* When specific counter for link layer SW low ISR reaches 0, interrupt is enabled */
+    //       HAL_NVIC_EnableIRQ(RADIO_SW_LOW_INTR_NUM);
+    //     }
+    //
+    //   }
+    //
+    //   if( (isr_type & SYS_LOW_ISR) != 0 )
+    //   {
+    //     prio_sys_isr_counter--;
+    //     if(prio_sys_isr_counter == 0)
+    //     {
+    //       /* Restore basepri value */
+    //       __set_BASEPRI(local_basepri_value);
+    //     }
+    //   }
+    if (isr_type & link_layer::LL_HIGH_ISR_ONLY as u8) != 0 {
+        if counter_release(&PRIO_HIGH_ISR_COUNTER) {
+            nvic_enable(mac::RADIO_INTR_NUM);
+        }
+    }
+
+    if (isr_type & link_layer::LL_LOW_ISR_ONLY as u8) != 0 {
+        if counter_release(&PRIO_LOW_ISR_COUNTER) {
+            nvic_enable(RADIO_SW_LOW_INTR_NUM);
+        }
+    }
+
+    if (isr_type & link_layer::SYS_LOW_ISR as u8) != 0 {
+        if counter_release(&PRIO_SYS_ISR_COUNTER) {
+            let stored = LOCAL_BASEPRI_VALUE.load(Ordering::Relaxed) as u8;
+            basepri::write(stored);
+        }
+    }
+}
+
 // /**
 //   * @brief  Disable specific interrupt group.
 //   * @param  isr_type: mask for interrupt group to disable.
@@ -427,219 +681,240 @@ fn test_fn() {}
 //   *              lower priority that link layer SW low interrupt.
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_DisableSpecificIRQ(uint8_t isr_type)
-// {
-//   if( (isr_type & LL_HIGH_ISR_ONLY) != 0 )
-//   {
-//     prio_high_isr_counter++;
-//     if(prio_high_isr_counter == 1)
-//     {
-//       /* USER CODE BEGIN LINKLAYER_PLAT_DisableSpecificIRQ_1 */
-//
-//       /* USER CODE END LINKLAYER_PLAT_DisableSpecificIRQ_1 */
-//       /* When specific counter for link layer high ISR value is 1, interrupt is disabled */
-//       HAL_NVIC_DisableIRQ(RADIO_INTR_NUM);
-//     }
-//   }
-//
-//   if( (isr_type & LL_LOW_ISR_ONLY) != 0 )
-//   {
-//     prio_low_isr_counter++;
-//     if(prio_low_isr_counter == 1)
-//     {
-//       /* When specific counter for link layer SW low ISR value is 1, interrupt is disabled */
-//       HAL_NVIC_DisableIRQ(RADIO_SW_LOW_INTR_NUM);
-//     }
-//   }
-//
-//   if( (isr_type & SYS_LOW_ISR) != 0 )
-//   {
-//     prio_sys_isr_counter++;
-//     if(prio_sys_isr_counter == 1)
-//     {
-//       /* Save basepri register value */
-//       local_basepri_value = __get_BASEPRI();
-//
-//       /* Mask all other interrupts with lower priority that link layer SW low ISR */
-//       __set_BASEPRI_MAX(RADIO_INTR_PRIO_LOW<<4);
-//     }
-//   }
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_DisableSpecificIRQ(isr_type: u8) {
+    //   if( (isr_type & LL_HIGH_ISR_ONLY) != 0 )
+    //   {
+    //     prio_high_isr_counter++;
+    //     if(prio_high_isr_counter == 1)
+    //     {
+    //       /* USER CODE BEGIN LINKLAYER_PLAT_DisableSpecificIRQ_1 */
+    //
+    //       /* USER CODE END LINKLAYER_PLAT_DisableSpecificIRQ_1 */
+    //       /* When specific counter for link layer high ISR value is 1, interrupt is disabled */
+    //       HAL_NVIC_DisableIRQ(RADIO_INTR_NUM);
+    //     }
+    //   }
+    //
+    //   if( (isr_type & LL_LOW_ISR_ONLY) != 0 )
+    //   {
+    //     prio_low_isr_counter++;
+    //     if(prio_low_isr_counter == 1)
+    //     {
+    //       /* When specific counter for link layer SW low ISR value is 1, interrupt is disabled */
+    //       HAL_NVIC_DisableIRQ(RADIO_SW_LOW_INTR_NUM);
+    //     }
+    //   }
+    //
+    //   if( (isr_type & SYS_LOW_ISR) != 0 )
+    //   {
+    //     prio_sys_isr_counter++;
+    //     if(prio_sys_isr_counter == 1)
+    //     {
+    //       /* Save basepri register value */
+    //       local_basepri_value = __get_BASEPRI();
+    //
+    //       /* Mask all other interrupts with lower priority that link layer SW low ISR */
+    //       __set_BASEPRI_MAX(RADIO_INTR_PRIO_LOW<<4);
+    //     }
+    //   }
+    trace!("LINKLAYER_PLAT_DisableSpecificIRQ: isr_type={}", isr_type);
+    if (isr_type & link_layer::LL_HIGH_ISR_ONLY as u8) != 0 {
+        if counter_acquire(&PRIO_HIGH_ISR_COUNTER) {
+            nvic_disable(mac::RADIO_INTR_NUM);
+        }
+    }
+
+    if (isr_type & link_layer::LL_LOW_ISR_ONLY as u8) != 0 {
+        if counter_acquire(&PRIO_LOW_ISR_COUNTER) {
+            nvic_disable(RADIO_SW_LOW_INTR_NUM);
+        }
+    }
+
+    if (isr_type & link_layer::SYS_LOW_ISR as u8) != 0 {
+        if counter_acquire(&PRIO_SYS_ISR_COUNTER) {
+            let current = basepri::read();
+            LOCAL_BASEPRI_VALUE.store(current.into(), Ordering::Relaxed);
+            set_basepri_max(pack_priority(mac::RADIO_INTR_PRIO_LOW));
+        }
+    }
+}
+
 // /**
 //   * @brief  Enable link layer high priority ISR only.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_EnableRadioIT(void)
-// {
-//   /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_1 */
-//
-//   /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_1 */
-//
-//   HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_INTR_NUM);
-//
-//   /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_2 */
-//
-//   /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_2 */
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_EnableRadioIT() {
+    trace!("LINKLAYER_PLAT_EnableRadioIT");
+    nvic_enable(mac::RADIO_INTR_NUM);
+}
+
 // /**
 //   * @brief  Disable link layer high priority ISR only.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_DisableRadioIT(void)
-// {
-//   /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_1 */
-//
-//   /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_1 */
-//
-//   HAL_NVIC_DisableIRQ((IRQn_Type) RADIO_INTR_NUM);
-//
-//   /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_2 */
-//
-//   /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_2 */
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_DisableRadioIT() {
+    trace!("LINKLAYER_PLAT_DisableRadioIT");
+    nvic_disable(mac::RADIO_INTR_NUM);
+}
+
 // /**
 //   * @brief  Link Layer notification for radio activity start.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_StartRadioEvt(void)
-// {
-//   __HAL_RCC_RADIO_CLK_SLEEP_ENABLE();
-//   NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH);
-// #if (CFG_SCM_SUPPORTED == 1)
-//   scm_notifyradiostate(SCM_RADIO_ACTIVE);
-// #endif /* CFG_SCM_SUPPORTED */
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_StartRadioEvt() {
+    trace!("LINKLAYER_PLAT_StartRadioEvt");
+    //   __HAL_RCC_RADIO_CLK_SLEEP_ENABLE();
+    //   NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH);
+    // #if (CFG_SCM_SUPPORTED == 1)
+    //   scm_notifyradiostate(SCM_RADIO_ACTIVE);
+    // #endif /* CFG_SCM_SUPPORTED */
+    nvic_set_priority(mac::RADIO_INTR_NUM, pack_priority(mac::RADIO_INTR_PRIO_HIGH));
+    nvic_enable(mac::RADIO_INTR_NUM);
+}
+
 // /**
 //   * @brief  Link Layer notification for radio activity end.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_StopRadioEvt(void)
-// {
-//   __HAL_RCC_RADIO_CLK_SLEEP_DISABLE();
-//   NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_LOW);
-// #if (CFG_SCM_SUPPORTED == 1)
-//   scm_notifyradiostate(SCM_RADIO_NOT_ACTIVE);
-// #endif /* CFG_SCM_SUPPORTED */
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_StopRadioEvt() {
+    trace!("LINKLAYER_PLAT_StopRadioEvt");
+    // {
+    //   __HAL_RCC_RADIO_CLK_SLEEP_DISABLE();
+    //   NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_LOW);
+    // #if (CFG_SCM_SUPPORTED == 1)
+    //   scm_notifyradiostate(SCM_RADIO_NOT_ACTIVE);
+    // #endif /* CFG_SCM_SUPPORTED */
+    nvic_set_priority(mac::RADIO_INTR_NUM, pack_priority(mac::RADIO_INTR_PRIO_LOW));
+}
+
 // /**
 //   * @brief  Link Layer notification for RCO calibration start.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_RCOStartClbr(void)
-// {
-// #if (CFG_LPM_LEVEL != 0)
-//   PWR_DisableSleepMode();
-//   /* Disabling stop mode prevents also from entering in standby */
-//   UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_DISABLE);
-// #endif /* (CFG_LPM_LEVEL != 0) */
-// #if (CFG_SCM_SUPPORTED == 1)
-//   scm_setsystemclock(SCM_USER_LL_HW_RCO_CLBR, HSE_32MHZ);
-//   while (LL_PWR_IsActiveFlag_VOS() == 0);
-// #endif /* (CFG_SCM_SUPPORTED == 1) */
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_RCOStartClbr() {
+    trace!("LINKLAYER_PLAT_RCOStartClbr");
+    // #if (CFG_LPM_LEVEL != 0)
+    //   PWR_DisableSleepMode();
+    //   /* Disabling stop mode prevents also from entering in standby */
+    //   UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_DISABLE);
+    // #endif /* (CFG_LPM_LEVEL != 0) */
+    // #if (CFG_SCM_SUPPORTED == 1)
+    //   scm_setsystemclock(SCM_USER_LL_HW_RCO_CLBR, HSE_32MHZ);
+    //   while (LL_PWR_IsActiveFlag_VOS() == 0);
+    // #endif /* (CFG_SCM_SUPPORTED == 1) */
+}
+
 // /**
 //   * @brief  Link Layer notification for RCO calibration end.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_RCOStopClbr(void)
-// {
-// #if (CFG_LPM_LEVEL != 0)
-//   PWR_EnableSleepMode();
-//   UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_ENABLE);
-// #endif /* (CFG_LPM_LEVEL != 0) */
-// #if (CFG_SCM_SUPPORTED == 1)
-//   scm_setsystemclock(SCM_USER_LL_HW_RCO_CLBR, HSE_16MHZ);
-// #endif /* (CFG_SCM_SUPPORTED == 1) */
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_RCOStopClbr() {
+    trace!("LINKLAYER_PLAT_RCOStopClbr");
+    // #if (CFG_LPM_LEVEL != 0)
+    //   PWR_EnableSleepMode();
+    //   UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_ENABLE);
+    // #endif /* (CFG_LPM_LEVEL != 0) */
+    // #if (CFG_SCM_SUPPORTED == 1)
+    //   scm_setsystemclock(SCM_USER_LL_HW_RCO_CLBR, HSE_16MHZ);
+    // #endif /* (CFG_SCM_SUPPORTED == 1) */
+}
+
 // /**
 //   * @brief  Link Layer requests temperature.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_RequestTemperature(void)
-// {
-// #if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1)
-//   ll_sys_bg_temperature_measurement();
-// #endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_RequestTemperature() {
+    trace!("LINKLAYER_PLAT_RequestTemperature");
+    // #if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1)
+    //   ll_sys_bg_temperature_measurement();
+    // #endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */
+}
+
 // /**
 //   * @brief  PHY Start calibration.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_PhyStartClbr(void)
-// {
-//   /* USER CODE BEGIN LINKLAYER_PLAT_PhyStartClbr_0 */
-//
-//   /* USER CODE END LINKLAYER_PLAT_PhyStartClbr_0 */
-//
-//   /* USER CODE BEGIN LINKLAYER_PLAT_PhyStartClbr_1 */
-//
-//   /* USER CODE END LINKLAYER_PLAT_PhyStartClbr_1 */
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_PhyStartClbr() {
+    trace!("LINKLAYER_PLAT_PhyStartClbr");
+}
+
 // /**
 //   * @brief  PHY Stop calibration.
 //   * @param  None
 //   * @retval None
 //   */
-// void LINKLAYER_PLAT_PhyStopClbr(void)
-// {
-//   /* USER CODE BEGIN LINKLAYER_PLAT_PhyStopClbr_0 */
-//
-//   /* USER CODE END LINKLAYER_PLAT_PhyStopClbr_0 */
-//
-//   /* USER CODE BEGIN LINKLAYER_PLAT_PhyStopClbr_1 */
-//
-//   /* USER CODE END LINKLAYER_PLAT_PhyStopClbr_1 */
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_PhyStopClbr() {
+    trace!("LINKLAYER_PLAT_PhyStopClbr");
+}
+
 // /**
 //  * @brief Notify the upper layer that new Link Layer timings have been applied.
 //  * @param evnt_timing[in]: Evnt_timing_t pointer to structure contains drift time , execution time and scheduling time
 //  * @retval None.
 //  */
-// void LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT(Evnt_timing_t * p_evnt_timing)
-// {
-//   /* USER CODE BEGIN LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT_0 */
-//
-//   /* USER CODE END LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT_0 */
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT(_timings: *const link_layer::Evnt_timing_t) {
+    trace!("LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT: timings={:?}", _timings);
+}
+
 // /**
 //   * @brief  Get the ST company ID.
 //   * @param  None
 //   * @retval Company ID
 //   */
-// uint32_t LINKLAYER_PLAT_GetSTCompanyID(void)
-// {
-//   return LL_FLASH_GetSTCompanyID();
-// }
-//
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_GetSTCompanyID() -> u32 {
+    trace!("LINKLAYER_PLAT_GetSTCompanyID");
+    // STMicroelectronics Bluetooth SIG Company Identifier
+    // TODO: Pull in update from latest stm32-generated-data
+    0x0030
+}
+
 // /**
 //   * @brief  Get the Unique Device Number (UDN).
 //   * @param  None
 //   * @retval UDN
 //   */
-// uint32_t LINKLAYER_PLAT_GetUDN(void)
-// {
-//   return LL_FLASH_GetUDN();
-// }
-//
-// /* USER CODE BEGIN LINKLAYER_PLAT 0 */
-//
-// /* USER CODE END LINKLAYER_PLAT 0 */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_PLAT_GetUDN() -> u32 {
+    trace!("LINKLAYER_PLAT_GetUDN");
+    // Read the first 32 bits of the STM32 unique 96-bit ID
+    let uid = embassy_stm32::uid::uid();
+    u32::from_le_bytes([uid[0], uid[1], uid[2], uid[3]])
+}
+
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_DEBUG_SIGNAL_SET() {
+    trace!("LINKLAYER_DEBUG_SIGNAL_SET");
+    todo!()
+}
+
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_DEBUG_SIGNAL_RESET() {
+    trace!("LINKLAYER_DEBUG_SIGNAL_RESET");
+    todo!()
+}
+
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn LINKLAYER_DEBUG_SIGNAL_TOGGLE() {
+    trace!("LINKLAYER_DEBUG_SIGNAL_TOGGLE");
+    todo!()
+}
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 38f22b1c3..9e0d69078 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -6,6 +6,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
 ## Unreleased - ReleaseDate
+- Add `receive_waveform` method in `InputCapture`, allowing asynchronous input capture with DMA.
 
 - fix: stm32: GPDMA driver reset ignored during channel configuration
 - fix: stm32: SPI driver SSOE and SSM manegment, add `nss_output_disable` to SPI Config
@@ -93,6 +94,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - stm32: Add blocking_listen for blocking I2C driver
 - fix: stm32l47*/stm32l48* adc analog pin setup
 - fix: keep stm32/sai: make NODIV independent of MCKDIV
+- fix: Source system clock from MSIS before (de)configuring PLLs on STM32U5
+- feat: adc: allow DMA reads to loop through enabled channels
 
 ## 0.4.0 - 2025-08-26
 
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 7989fc5d7..880df5f33 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -193,18 +193,18 @@ document-features = "0.2.7"
 
 static_assertions = { version = "1.1" }
 volatile-register = { version = "0.2.1" }
-bitflags = "2.4.2"
+bitflags = "2.10.0"
 
 block-device-driver = { version = "0.2" }
 aligned = "0.4.1"
 heapless = "0.9.1"
 
 #stm32-metapac = { version = "18" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-497fb3042b49b765d8974aac87b8ab4fa3566d74" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-658588478e426d68090a59ff8385bce5b407c2bc" }
 
 [build-dependencies]
 #stm32-metapac = { version = "18", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-497fb3042b49b765d8974aac87b8ab4fa3566d74", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-658588478e426d68090a59ff8385bce5b407c2bc", default-features = false, features = ["metadata"] }
 
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
@@ -241,8 +241,9 @@ log = ["dep:log"]
 chrono = ["dep:chrono"]
 
 exti = []
-low-power = [ "dep:embassy-executor", "embassy-executor?/arch-cortex-m", "time" ]
-low-power-debug-with-sleep = []
+low-power = [ "dep:embassy-executor", "time" ]
+low-power-pender = [ "low-power" ]
+low-power-debug-with-sleep = [ "low-power" ]
 
 ## Automatically generate `memory.x` file based on the memory map from [`stm32-metapac`](https://docs.rs/stm32-metapac/)
 memory-x = []
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 46d6290e7..a3b863340 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -950,6 +950,60 @@ fn main() {
             }
         }
 
+        if kind == "gpio" {
+            for p in METADATA.peripherals {
+                // set all GPIOs to analog mode except for PA13 and PA14 which are SWDIO and SWDCLK
+                if p.registers.is_some()
+                    && p.registers.as_ref().unwrap().kind == "gpio"
+                    && p.registers.as_ref().unwrap().version != "v1"
+                {
+                    let port = format_ident!("{}", p.name);
+                    if p.name == "GPIOA" {
+                        gg.extend(quote! {
+                            // leave PA13 and PA14 as unchanged
+                            crate::pac::#port.moder().modify(|w| {
+                                w.set_moder(0, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(1, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(2, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(3, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(4, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(5, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(6, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(7, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(8, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(9, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(10, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(11, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(12, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(15, crate::pac::gpio::vals::Moder::ANALOG);
+                            });
+                        });
+                    } else {
+                        gg.extend(quote! {
+                            crate::pac::#port.moder().modify(|w| {
+                                w.set_moder(0, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(1, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(2, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(3, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(4, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(5, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(6, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(7, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(8, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(9, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(10, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(11, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(12, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(13, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(14, crate::pac::gpio::vals::Moder::ANALOG);
+                                w.set_moder(15, crate::pac::gpio::vals::Moder::ANALOG);
+                            });
+                        });
+                    }
+                }
+            }
+        }
+
         let fname = format_ident!("init_{}", kind);
         g.extend(quote! {
             pub unsafe fn #fname(){
diff --git a/embassy-stm32/src/adc/adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 43509873f..491569c34 100644
--- a/embassy-stm32/src/adc/adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -24,23 +24,23 @@ pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
 pub const VREF_CALIB_MV: u32 = 3300;
 
-impl<'d, T: Instance> super::SealedSpecialConverter<super::VrefInt> for Adc4<'d, T> {
+impl super::SealedSpecialConverter<super::VrefInt> for crate::peripherals::ADC4 {
     const CHANNEL: u8 = 0;
 }
 
-impl<'d, T: Instance> super::SealedSpecialConverter<super::Temperature> for Adc4<'d, T> {
+impl super::SealedSpecialConverter<super::Temperature> for crate::peripherals::ADC4 {
     const CHANNEL: u8 = 13;
 }
 
-impl<'d, T: Instance> super::SealedSpecialConverter<super::Vcore> for Adc4<'d, T> {
+impl super::SealedSpecialConverter<super::Vcore> for crate::peripherals::ADC4 {
     const CHANNEL: u8 = 12;
 }
 
-impl<'d, T: Instance> super::SealedSpecialConverter<super::Vbat> for Adc4<'d, T> {
+impl super::SealedSpecialConverter<super::Vbat> for crate::peripherals::ADC4 {
     const CHANNEL: u8 = 14;
 }
 
-impl<'d, T: Instance> super::SealedSpecialConverter<super::Dac> for Adc4<'d, T> {
+impl super::SealedSpecialConverter<super::Dac> for crate::peripherals::ADC4 {
     const CHANNEL: u8 = 21;
 }
 
@@ -197,17 +197,6 @@ impl AdcRegs for crate::pac::adc::Adc4 {
     }
 }
 
-pub struct Adc4<'d, T: Instance> {
-    #[allow(unused)]
-    adc: crate::Peri<'d, T>,
-}
-
-#[derive(Copy, Clone, Debug)]
-pub enum Adc4Error {
-    InvalidSequence,
-    DMAError,
-}
-
 impl<'d, T: Instance<Regs = crate::pac::adc::Adc4>> super::Adc<'d, T> {
     /// Create a new ADC driver.
     pub fn new_adc4(adc: Peri<'d, T>) -> Self {
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index a6af1175a..17b1dae77 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -208,13 +208,13 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().enable();
         T::regs().convert();
 
-        unsafe { *T::regs().data() }
+        unsafe { core::ptr::read_volatile(T::regs().data()) }
     }
 
     #[cfg(any(adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
     /// Read one or multiple ADC regular channels using DMA.
     ///
-    /// `sequence` iterator and `readings` must have the same length.
+    /// `readings` must have a length that is a multiple of the length of the `sequence` iterator.
     ///
     /// Example
     /// ```rust,ignore
@@ -253,8 +253,8 @@ impl<'d, T: Instance> Adc<'d, T> {
     ) {
         assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
         assert!(
-            sequence.len() == readings.len(),
-            "Sequence length must be equal to readings length"
+            readings.len() % sequence.len() == 0,
+            "Readings length must be a multiple of sequence length"
         );
         assert!(
             sequence.len() <= 16,
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index 09fc2ab22..962816194 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -5,6 +5,8 @@ use pac::adc::vals::{Adstp, Difsel, Dmngt, Exten, Pcsel};
 use pac::adccommon::vals::Presc;
 
 use super::{Adc, Averaging, Instance, Resolution, SampleTime, Temperature, Vbat, VrefInt, blocking_delay_us};
+#[cfg(stm32u5)]
+use crate::adc::DefaultInstance;
 use crate::adc::{AdcRegs, ConversionMode};
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
@@ -47,15 +49,15 @@ impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
 }
 
 #[cfg(stm32u5)]
-impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+impl<T: DefaultInstance> super::SealedSpecialConverter<super::VrefInt> for T {
     const CHANNEL: u8 = 0;
 }
 #[cfg(stm32u5)]
-impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+impl<T: DefaultInstance> super::SealedSpecialConverter<super::Temperature> for T {
     const CHANNEL: u8 = 19;
 }
 #[cfg(stm32u5)]
-impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+impl<T: DefaultInstance> super::SealedSpecialConverter<super::Vbat> for T {
     const CHANNEL: u8 = 18;
 }
 
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index e62de0454..e5c68acbd 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -94,17 +94,14 @@ pub struct HardwareSemaphoreInterruptHandler<T: Instance> {
 impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for HardwareSemaphoreInterruptHandler<T> {
     unsafe fn on_interrupt() {
         let core_id = CoreId::current();
+        let isr = T::regs().isr(core_id.to_index()).read();
 
         for number in 0..5 {
-            if T::regs().isr(core_id.to_index()).read().isf(number as usize) {
+            if isr.isf(number as usize) {
                 T::regs()
                     .icr(core_id.to_index())
                     .write(|w| w.set_isc(number as usize, true));
 
-                T::regs()
-                    .ier(core_id.to_index())
-                    .modify(|w| w.set_ise(number as usize, false));
-
                 T::state().waker_for(number).wake();
             }
         }
@@ -120,6 +117,18 @@ pub struct HardwareSemaphoreMutex<'a, T: Instance> {
 
 impl<'a, T: Instance> Drop for HardwareSemaphoreMutex<'a, T> {
     fn drop(&mut self) {
+        let core_id = CoreId::current();
+
+        T::regs()
+            .icr(core_id.to_index())
+            .write(|w| w.set_isc(self.index as usize, true));
+
+        critical_section::with(|_| {
+            T::regs()
+                .ier(core_id.to_index())
+                .modify(|w| w.set_ise(self.index as usize, false));
+        });
+
         HardwareSemaphoreChannel::<'a, T> {
             index: self.index,
             _lifetime: PhantomData,
@@ -148,6 +157,7 @@ impl<'a, T: Instance> HardwareSemaphoreChannel<'a, T> {
     /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
     /// check if the lock has been successful, carried out from the HSEM_Rx register.
     pub async fn lock(&mut self, process_id: u8) -> HardwareSemaphoreMutex<'a, T> {
+        let _scoped_block_stop = T::RCC_INFO.block_stop();
         let core_id = CoreId::current();
 
         poll_fn(|cx| {
@@ -155,9 +165,11 @@ impl<'a, T: Instance> HardwareSemaphoreChannel<'a, T> {
 
             compiler_fence(Ordering::SeqCst);
 
-            T::regs()
-                .ier(core_id.to_index())
-                .modify(|w| w.set_ise(self.index as usize, true));
+            critical_section::with(|_| {
+                T::regs()
+                    .ier(core_id.to_index())
+                    .modify(|w| w.set_ise(self.index as usize, true));
+            });
 
             match self.try_lock(process_id) {
                 Some(mutex) => Poll::Ready(mutex),
@@ -241,7 +253,7 @@ impl<T: Instance> HardwareSemaphore<T> {
         _peripheral: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, HardwareSemaphoreInterruptHandler<T>> + 'd,
     ) -> Self {
-        rcc::enable_and_reset::<T>();
+        rcc::enable_and_reset_without_stop::<T>();
 
         HardwareSemaphore { _type: PhantomData }
     }
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index 0bf430ffc..0aa2d1da9 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -129,7 +129,7 @@ impl<'d> Drop for I2CDropGuard<'d> {
             x.set_as_disconnected()
         }
 
-        self.info.rcc.disable();
+        self.info.rcc.disable_without_stop();
     }
 }
 
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index 10c4a820b..74ce0b29e 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -10,6 +10,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::interrupt::typelevel::Interrupt;
 use crate::peripherals::IPCC;
+use crate::rcc::SealedRccPeripheral;
 use crate::{interrupt, rcc};
 
 /// Interrupt handler.
@@ -84,6 +85,7 @@ impl<'a> IpccTxChannel<'a> {
 
     /// Send data to an IPCC channel. The closure is called to write the data when appropriate.
     pub async fn send(&mut self, f: impl FnOnce()) {
+        let _scoped_block_stop = IPCC::RCC_INFO.block_stop();
         let regs = IPCC::regs();
 
         self.flush().await;
@@ -98,6 +100,7 @@ impl<'a> IpccTxChannel<'a> {
 
     /// Wait for the tx channel to become clear
     pub async fn flush(&mut self) {
+        let _scoped_block_stop = IPCC::RCC_INFO.block_stop();
         let regs = IPCC::regs();
 
         // This is a race, but is nice for debugging
@@ -143,6 +146,7 @@ impl<'a> IpccRxChannel<'a> {
 
     /// Receive data from an IPCC channel. The closure is called to read the data when appropriate.
     pub async fn receive<R>(&mut self, mut f: impl FnMut() -> Option<R>) -> R {
+        let _scoped_block_stop = IPCC::RCC_INFO.block_stop();
         let regs = IPCC::regs();
 
         loop {
@@ -220,9 +224,12 @@ impl Ipcc {
         + 'd,
         _config: Config,
     ) -> Self {
-        rcc::enable_and_reset::<IPCC>();
+        rcc::enable_and_reset_without_stop::<IPCC>();
         IPCC::set_cpu2(true);
 
+        // Verify rfwkpsel is set
+        let _ = IPCC::frequency();
+
         let regs = IPCC::regs();
 
         regs.cpu(0).cr().modify(|w| {
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 2f783bf64..a0b2f045c 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -138,6 +138,9 @@ pub mod wdg;
 #[cfg(xspi)]
 pub mod xspi;
 
+#[cfg(feature = "low-power")]
+pub use low_power::Executor;
+
 // This must go last, so that it sees all the impl_foo! macros defined earlier.
 pub(crate) mod _generated {
     #![allow(dead_code)]
diff --git a/embassy-stm32/src/low_power.rs b/embassy-stm32/src/low_power.rs
index 2388abe3c..02116e08a 100644
--- a/embassy-stm32/src/low_power.rs
+++ b/embassy-stm32/src/low_power.rs
@@ -3,31 +3,31 @@
 //! The STM32 line of microcontrollers support various deep-sleep modes which exploit clock-gating
 //! to reduce power consumption. `embassy-stm32` provides a low-power executor, [`Executor`] which
 //! can use knowledge of which peripherals are currently blocked upon to transparently and safely
-//! enter such low-power modes (currently, only `STOP2`) when idle.
+//! enter such low-power modes including `STOP1` and `STOP2` when idle.
 //!
 //! The executor determines which peripherals are active by their RCC state; consequently,
-//! low-power states can only be entered if all peripherals have been `drop`'d. There are a few
-//! exceptions to this rule:
+//! low-power states can only be entered if peripherals which block stop have been `drop`'d and if
+//! peripherals that do not block stop are busy. Peripherals which never block stop include:
 //!
 //!  * `GPIO`
 //!  * `RTC`
 //!
+//! Other peripherals which block stop when busy include (this list may be stale):
+//!
+//!  * `I2C`
+//!  * `USART`
+//!
 //! Since entering and leaving low-power modes typically incurs a significant latency, the
 //! low-power executor will only attempt to enter when the next timer event is at least
-//! [`time_driver::min_stop_pause`] in the future.
+//! [`config.min_stop_pause`] in the future.
 //!
-//! Currently there is no macro analogous to `embassy_executor::main` for this executor;
-//! consequently one must define their entrypoint manually. Moreover, you must relinquish control
-//! of the `RTC` peripheral to the executor. This will typically look like
 //!
 //! ```rust,no_run
 //! use embassy_executor::Spawner;
-//! use embassy_stm32::low_power;
-//! use embassy_stm32::rtc::{Rtc, RtcConfig};
 //! use embassy_time::Duration;
 //!
-//! #[embassy_executor::main(executor = "low_power::Executor")]
-//! async fn async_main(spawner: Spawner) {
+//! #[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
+//! async fn main(spawner: Spawner) {
 //!     // initialize the platform...
 //!     let mut config = embassy_stm32::Config::default();
 //!     // the default value, but can be adjusted
@@ -43,7 +43,7 @@
 use core::arch::asm;
 use core::marker::PhantomData;
 use core::mem;
-use core::sync::atomic::{Ordering, compiler_fence};
+use core::sync::atomic::{AtomicBool, Ordering, compiler_fence};
 
 use cortex_m::peripheral::SCB;
 use critical_section::CriticalSection;
@@ -56,7 +56,27 @@ use crate::time_driver::get_driver;
 
 const THREAD_PENDER: usize = usize::MAX;
 
-static mut EXECUTOR_TAKEN: bool = false;
+static EXECUTOR_TAKEN: AtomicBool = AtomicBool::new(false);
+#[cfg(feature = "low-power-pender")]
+static TASKS_PENDING: AtomicBool = AtomicBool::new(false);
+
+#[cfg(feature = "low-power-pender")]
+#[unsafe(export_name = "__pender")]
+fn __pender(context: *mut ()) {
+    unsafe {
+        // Safety: `context` is either `usize::MAX` created by `Executor::run`, or a valid interrupt
+        // request number given to `InterruptExecutor::start`.
+
+        let context = context as usize;
+
+        // Try to make Rust optimize the branching away if we only use thread mode.
+        if context == THREAD_PENDER {
+            TASKS_PENDING.store(true, Ordering::Release);
+            core::arch::asm!("sev");
+            return;
+        }
+    }
+}
 
 /// Prevent the device from going into the stop mode if held
 pub struct DeviceBusy {
@@ -124,9 +144,9 @@ impl Into<Lpms> for StopMode {
     fn into(self) -> Lpms {
         match self {
             StopMode::Stop1 => Lpms::STOP1,
-            #[cfg(not(any(stm32wb, stm32wba)))]
+            #[cfg(not(stm32wba))]
             StopMode::Standby | StopMode::Stop2 => Lpms::STOP2,
-            #[cfg(any(stm32wb, stm32wba))]
+            #[cfg(stm32wba)]
             StopMode::Standby | StopMode::Stop2 => Lpms::STOP1, // TODO: WBA has no STOP2?
         }
     }
@@ -150,12 +170,10 @@ pub struct Executor {
 impl Executor {
     /// Create a new Executor.
     pub fn new() -> Self {
-        unsafe {
-            if EXECUTOR_TAKEN {
-                panic!("Low power executor can only be taken once.");
-            } else {
-                EXECUTOR_TAKEN = true;
-            }
+        if EXECUTOR_TAKEN.load(Ordering::Acquire) {
+            panic!("Low power executor can only be taken once.");
+        } else {
+            EXECUTOR_TAKEN.store(true, Ordering::Release);
         }
 
         Self {
@@ -170,24 +188,45 @@ impl Executor {
         }
 
         critical_section::with(|cs| {
-            #[cfg(stm32wlex)]
+            #[cfg(any(stm32wlex, stm32wb))]
             {
                 let es = crate::pac::PWR.extscr().read();
+                #[cfg(stm32wlex)]
                 match (es.c1stopf(), es.c1stop2f()) {
                     (true, false) => debug!("low power: wake from STOP1"),
                     (false, true) => debug!("low power: wake from STOP2"),
                     (true, true) => debug!("low power: wake from STOP1 and STOP2 ???"),
                     (false, false) => trace!("low power: stop mode not entered"),
                 };
+
+                #[cfg(stm32wb)]
+                match (es.c1stopf(), es.c2stopf()) {
+                    (true, false) => debug!("low power: cpu1 wake from STOP"),
+                    (false, true) => debug!("low power: cpu2 wake from STOP"),
+                    (true, true) => debug!("low power: cpu1 and cpu2 wake from STOP"),
+                    (false, false) => trace!("low power: stop mode not entered"),
+                };
                 crate::pac::PWR.extscr().modify(|w| {
                     w.set_c1cssf(false);
                 });
 
-                if es.c1stop2f() || es.c1stopf() {
+                let _has_stopped2 = {
+                    #[cfg(stm32wb)]
+                    {
+                        es.c2stopf()
+                    }
+
+                    #[cfg(stm32wlex)]
+                    {
+                        es.c1stop2f()
+                    }
+                };
+
+                #[cfg(not(stm32wb))]
+                if es.c1stopf() || _has_stopped2 {
                     // when we wake from any stop mode we need to re-initialize the rcc
                     crate::rcc::init(RCC_CONFIG.unwrap());
-
-                    if es.c1stop2f() {
+                    if _has_stopped2 {
                         // when we wake from STOP2, we need to re-initialize the time driver
                         get_driver().init_timer(cs);
                         // reset the refcounts for STOP2 and STOP1 (initializing the time driver will increment one of them for the timer)
@@ -276,6 +315,20 @@ impl Executor {
 
         drop(sem3_mutex);
 
+        // on PWR
+        RCC.apb1enr1().modify(|r| r.0 |= 1 << 28);
+        cortex_m::asm::dsb();
+
+        // off SMPS, on Bypass
+        PWR.cr5().modify(|r| {
+            let mut val = r.0;
+            val &= !(1 << 15); // sdeb = 0 (off SMPS)
+            val |= 1 << 14; // sdben = 1 (on Bypass)
+            r.0 = val
+        });
+
+        cortex_m::asm::delay(1000);
+
         Ok(())
     }
 
@@ -304,7 +357,14 @@ impl Executor {
             w.set_c1cssf(true);
         });
 
-        compiler_fence(Ordering::SeqCst);
+        #[cfg(feature = "low-power-pender")]
+        if TASKS_PENDING.load(Ordering::Acquire) {
+            TASKS_PENDING.store(false, Ordering::Release);
+
+            return;
+        }
+
+        compiler_fence(Ordering::Acquire);
 
         critical_section::with(|cs| {
             let _ = unsafe { RCC_CONFIG }?;
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 2e1cbd702..0d668103c 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -135,7 +135,14 @@ pub const WPAN_DEFAULT: Config = Config {
     apb1_pre: APBPrescaler::DIV1,
     apb2_pre: APBPrescaler::DIV1,
 
-    mux: super::mux::ClockMux::default(),
+    mux: {
+        use crate::pac::rcc::vals::Rfwkpsel;
+
+        let mut mux = super::mux::ClockMux::default();
+
+        mux.rfwkpsel = Rfwkpsel::LSE;
+        mux
+    },
 };
 
 fn msi_enable(range: MSIRange) {
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 2a9a1595a..753ee1290 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -312,6 +312,15 @@ impl RccInfo {
     }
 
     #[allow(dead_code)]
+    fn increment_minimum_stop_refcount_with_cs(&self, _cs: CriticalSection) {
+        #[cfg(all(any(stm32wlex, stm32wb), feature = "low-power"))]
+        match self.stop_mode {
+            StopMode::Stop1 | StopMode::Stop2 => increment_stop_refcount(_cs, StopMode::Stop2),
+            _ => {}
+        }
+    }
+
+    #[allow(dead_code)]
     pub(crate) fn increment_stop_refcount(&self) {
         #[cfg(feature = "low-power")]
         critical_section::with(|cs| self.increment_stop_refcount_with_cs(cs))
@@ -324,6 +333,15 @@ impl RccInfo {
     }
 
     #[allow(dead_code)]
+    fn decrement_minimum_stop_refcount_with_cs(&self, _cs: CriticalSection) {
+        #[cfg(all(any(stm32wlex, stm32wb), feature = "low-power"))]
+        match self.stop_mode {
+            StopMode::Stop1 | StopMode::Stop2 => decrement_stop_refcount(_cs, StopMode::Stop2),
+            _ => {}
+        }
+    }
+
+    #[allow(dead_code)]
     pub(crate) fn decrement_stop_refcount(&self) {
         #[cfg(feature = "low-power")]
         critical_section::with(|cs| self.decrement_stop_refcount_with_cs(cs))
@@ -339,7 +357,10 @@ impl RccInfo {
 
     #[allow(dead_code)]
     pub(crate) fn enable_and_reset_without_stop(&self) {
-        critical_section::with(|cs| self.enable_and_reset_with_cs(cs))
+        critical_section::with(|cs| {
+            self.enable_and_reset_with_cs(cs);
+            self.increment_minimum_stop_refcount_with_cs(cs);
+        })
     }
 
     // TODO: should this be `unsafe`?
@@ -353,7 +374,10 @@ impl RccInfo {
     // TODO: should this be `unsafe`?
     #[allow(dead_code)]
     pub(crate) fn disable_without_stop(&self) {
-        critical_section::with(|cs| self.disable_with_cs(cs))
+        critical_section::with(|cs| {
+            self.disable_with_cs(cs);
+            self.decrement_minimum_stop_refcount_with_cs(cs);
+        })
     }
 
     #[allow(dead_code)]
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 7b0dcb63f..47cc29c6f 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -343,6 +343,16 @@ pub(crate) unsafe fn init(config: Config) {
 
     let hsi48 = config.hsi48.map(super::init_hsi48);
 
+    // There's a possibility that a bootloader that ran before us has configured the system clock
+    // source to be PLL1_R. In that case we'd get forever stuck on (de)configuring PLL1 as the chip
+    // prohibits disabling PLL1 when it's used as a source for system clock. Change the system
+    // clock source to MSIS which doesn't suffer from this conflict. The correct source per the
+    // provided config is then set further down.
+    // See https://github.com/embassy-rs/embassy/issues/5072
+    let default_system_clock_source = Config::default().sys;
+    RCC.cfgr1().modify(|w| w.set_sw(default_system_clock_source));
+    while RCC.cfgr1().read().sws() != default_system_clock_source {}
+
     let pll_input = PllInput { hse, hsi, msi: msis };
     let pll1 = init_pll(PllInstance::Pll1, config.pll1, &pll_input, config.voltage_range);
     let pll2 = init_pll(PllInstance::Pll2, config.pll2, &pll_input, config.voltage_range);
diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs
index dada9bda1..b8dfc7ecf 100644
--- a/embassy-stm32/src/rng.rs
+++ b/embassy-stm32/src/rng.rs
@@ -13,6 +13,23 @@ use crate::{Peri, interrupt, pac, peripherals, rcc};
 
 static RNG_WAKER: AtomicWaker = AtomicWaker::new();
 
+/// WBA-specific health test configuration values for RNG
+#[derive(Clone, Copy)]
+#[allow(dead_code)]
+enum Htcfg {
+    /// WBA-specific health test configuration (0x0000AAC7)
+    /// Corresponds to configuration A, B, and C thresholds as recommended in the reference manual
+    WbaRecommended = 0x0000_AAC7,
+}
+
+impl Htcfg {
+    /// Convert to the raw u32 value for register access
+    #[allow(dead_code)]
+    fn value(self) -> u32 {
+        self as u32
+    }
+}
+
 /// RNG error
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -100,7 +117,7 @@ impl<'d, T: Instance> Rng<'d, T> {
         // wait for CONDRST to be set
         while !T::regs().cr().read().condrst() {}
 
-        // TODO for WBA6, the HTCR reg is different
+        // Set health test configuration values
         #[cfg(not(rng_wba6))]
         {
             // magic number must be written immediately before every read or write access to HTCR
@@ -111,6 +128,12 @@ impl<'d, T: Instance> Rng<'d, T> {
                 .htcr()
                 .write(|w| w.set_htcfg(pac::rng::vals::Htcfg::RECOMMENDED));
         }
+        #[cfg(rng_wba6)]
+        {
+            // For WBA6, set RNG_HTCR0 to the recommended value for configurations A, B, and C
+            // This value corresponds to the health test thresholds specified in the reference manual
+            T::regs().htcr(0).write(|w| w.0 = Htcfg::WbaRecommended.value());
+        }
 
         // finish conditioning
         T::regs().cr().modify(|reg| {
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index 12086cd3a..cfe18ef52 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -7,6 +7,7 @@ use core::marker::PhantomData;
 use core::slice;
 use core::task::Poll;
 
+use aligned::{A4, Aligned};
 use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
 use sdio_host::Cmd;
@@ -139,14 +140,36 @@ impl Default for Signalling {
     }
 }
 
+const fn aligned_mut(x: &mut [u32]) -> &mut Aligned<A4, [u8]> {
+    let len = x.len() * 4;
+    unsafe { core::mem::transmute(slice::from_raw_parts_mut(x.as_mut_ptr() as *mut u8, len)) }
+}
+
 const fn slice8_mut(x: &mut [u32]) -> &mut [u8] {
     let len = x.len() * 4;
-    unsafe { slice::from_raw_parts_mut(x.as_mut_ptr() as _, len) }
+    unsafe { slice::from_raw_parts_mut(x.as_mut_ptr() as *mut u8, len) }
+}
+
+#[allow(unused)]
+const fn slice32_mut(x: &mut Aligned<A4, [u8]>) -> &mut [u32] {
+    let len = (size_of_val(x) + 4 - 1) / 4;
+    unsafe { slice::from_raw_parts_mut(x as *mut Aligned<A4, [u8]> as *mut u32, len) }
+}
+
+const fn aligned_ref(x: &[u32]) -> &Aligned<A4, [u8]> {
+    let len = x.len() * 4;
+    unsafe { core::mem::transmute(slice::from_raw_parts(x.as_ptr() as *const u8, len)) }
 }
 
 const fn slice8_ref(x: &[u32]) -> &[u8] {
     let len = x.len() * 4;
-    unsafe { slice::from_raw_parts(x.as_ptr() as _, len) }
+    unsafe { slice::from_raw_parts(x.as_ptr() as *const u8, len) }
+}
+
+#[allow(unused)]
+const fn slice32_ref(x: &Aligned<A4, [u8]>) -> &[u32] {
+    let len = (size_of_val(x) + 4 - 1) / 4;
+    unsafe { slice::from_raw_parts(x as *const Aligned<A4, [u8]> as *const u32, len) }
 }
 
 /// Errors
@@ -187,6 +210,11 @@ enum PowerCtrl {
     On = 0b11,
 }
 
+enum DatapathMode {
+    Block(BlockSize),
+    Byte,
+}
+
 fn get_waitresp_val(rlen: ResponseLen) -> u8 {
     match rlen {
         common_cmd::ResponseLen::Zero => 0,
@@ -768,12 +796,16 @@ impl<'d> Sdmmc<'d> {
     #[allow(unused_variables)]
     fn prepare_datapath_read<'a>(
         &'a self,
-        buffer: &'a mut [u32],
-        block_size: BlockSize,
-        byte_mode: bool,
+        buffer: &'a mut Aligned<A4, [u8]>,
+        mode: DatapathMode,
     ) -> WrappedTransfer<'a> {
         let regs = self.info.regs;
 
+        let (byte_mode, block_size) = match mode {
+            DatapathMode::Block(block_size) => (false, block_size as u8),
+            DatapathMode::Byte => (true, 0),
+        };
+
         // Command AND Data state machines must be idle
         self.wait_idle();
         self.clear_interrupt_flags();
@@ -783,8 +815,11 @@ impl<'d> Sdmmc<'d> {
         // SAFETY: No other functions use the dma
         #[cfg(sdmmc_v1)]
         let transfer = unsafe {
-            self.dma
-                .read_unchecked(regs.fifor().as_ptr() as *mut u32, buffer, DMA_TRANSFER_OPTIONS)
+            self.dma.read_unchecked(
+                regs.fifor().as_ptr() as *mut u32,
+                slice32_mut(buffer),
+                DMA_TRANSFER_OPTIONS,
+            )
         };
         #[cfg(sdmmc_v2)]
         let transfer = {
@@ -817,14 +852,14 @@ impl<'d> Sdmmc<'d> {
     /// # Safety
     ///
     /// `buffer` must be valid for the whole transfer and word aligned
-    fn prepare_datapath_write<'a>(
-        &'a self,
-        buffer: &'a [u32],
-        block_size: BlockSize,
-        byte_mode: bool,
-    ) -> WrappedTransfer<'a> {
+    fn prepare_datapath_write<'a>(&'a self, buffer: &'a Aligned<A4, [u8]>, mode: DatapathMode) -> WrappedTransfer<'a> {
         let regs = self.info.regs;
 
+        let (byte_mode, block_size) = match mode {
+            DatapathMode::Block(block_size) => (false, block_size as u8),
+            DatapathMode::Byte => (true, 0),
+        };
+
         // Command AND Data state machines must be idle
         self.wait_idle();
         self.clear_interrupt_flags();
@@ -834,8 +869,11 @@ impl<'d> Sdmmc<'d> {
         // SAFETY: No other functions use the dma
         #[cfg(sdmmc_v1)]
         let transfer = unsafe {
-            self.dma
-                .write_unchecked(buffer, regs.fifor().as_ptr() as *mut u32, DMA_TRANSFER_OPTIONS)
+            self.dma.write_unchecked(
+                slice32_ref(buffer),
+                regs.fifor().as_ptr() as *mut u32,
+                DMA_TRANSFER_OPTIONS,
+            )
         };
         #[cfg(sdmmc_v2)]
         let transfer = {
@@ -1141,6 +1179,7 @@ impl<'d> Drop for Sdmmc<'d> {
     fn drop(&mut self) {
         // T::Interrupt::disable();
         self.on_drop();
+        self.info.rcc.disable_without_stop();
 
         critical_section::with(|_| {
             self.clk.set_as_disconnected();
diff --git a/embassy-stm32/src/sdmmc/sd.rs b/embassy-stm32/src/sdmmc/sd.rs
index 6190226b8..20318bbfa 100644
--- a/embassy-stm32/src/sdmmc/sd.rs
+++ b/embassy-stm32/src/sdmmc/sd.rs
@@ -5,7 +5,10 @@ use sdio_host::emmc::{EMMC, ExtCSD};
 use sdio_host::sd::{BusWidth, CIC, CID, CSD, CardCapacity, CardStatus, CurrentState, OCR, RCA, SCR, SD, SDStatus};
 use sdio_host::{common_cmd, emmc_cmd, sd_cmd};
 
-use crate::sdmmc::{BlockSize, Error, Sdmmc, Signalling, block_size, bus_width_vals, slice8_mut, slice8_ref};
+use crate::sdmmc::{
+    BlockSize, DatapathMode, Error, Sdmmc, Signalling, aligned_mut, aligned_ref, block_size, bus_width_vals,
+    slice8_mut, slice8_ref,
+};
 use crate::time::{Hertz, mhz};
 
 /// Aligned data block for SDMMC transfers.
@@ -230,10 +233,8 @@ impl<'a, 'b> StorageDevice<'a, 'b, Card> {
             };
 
         let buffer = &mut cmd_block.0[..64 / 4];
-
-        let transfer = self
-            .sdmmc
-            .prepare_datapath_read(buffer, block_size(size_of_val(buffer)), false);
+        let mode = DatapathMode::Block(block_size(size_of_val(buffer)));
+        let transfer = self.sdmmc.prepare_datapath_read(aligned_mut(buffer), mode);
 
         self.sdmmc.cmd(sd_cmd::cmd6(set_function), true)?; // CMD6
 
@@ -272,7 +273,9 @@ impl<'a, 'b> StorageDevice<'a, 'b, Card> {
 
         // Arm `OnDrop` after the buffer, so it will be dropped first
 
-        let transfer = self.sdmmc.prepare_datapath_read(scr, BlockSize::Size8, false);
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_read(aligned_mut(scr), DatapathMode::Block(BlockSize::Size8));
         self.sdmmc.cmd(sd_cmd::send_scr(), true)?;
 
         self.sdmmc.complete_datapath_transfer(transfer, true).await?;
@@ -290,10 +293,9 @@ impl<'a, 'b> StorageDevice<'a, 'b, Card> {
         self.sdmmc.cmd(common_cmd::app_cmd(rca), false)?; // APP
 
         let buffer = &mut cmd_block.as_mut()[..64 / 4];
+        let mode = DatapathMode::Block(block_size(size_of_val(buffer)));
 
-        let transfer = self
-            .sdmmc
-            .prepare_datapath_read(buffer, block_size(size_of_val(buffer)), false);
+        let transfer = self.sdmmc.prepare_datapath_read(aligned_mut(buffer), mode);
         self.sdmmc.cmd(sd_cmd::sd_status(), true)?;
 
         self.sdmmc.complete_datapath_transfer(transfer, true).await?;
@@ -398,9 +400,10 @@ impl<'a, 'b> StorageDevice<'a, 'b, Emmc> {
             .cmd(common_cmd::set_block_length(size_of::<DataBlock>() as u32), false)
             .unwrap(); // CMD16
 
-        let transfer = self
-            .sdmmc
-            .prepare_datapath_read(&mut data_block.0, block_size(size_of::<DataBlock>()), false);
+        let transfer = self.sdmmc.prepare_datapath_read(
+            aligned_mut(&mut data_block.0),
+            DatapathMode::Block(block_size(size_of::<DataBlock>())),
+        );
         self.sdmmc.cmd(emmc_cmd::send_ext_csd(), true)?;
 
         self.sdmmc.complete_datapath_transfer(transfer, true).await?;
@@ -418,7 +421,7 @@ impl<'a, 'b, A: Addressable> StorageDevice<'a, 'b, A> {
 
     /// Read a data block.
     #[inline]
-    pub async fn read_block(&mut self, block_idx: u32, buffer: &mut DataBlock) -> Result<(), Error> {
+    pub async fn read_block(&mut self, block_idx: u32, data_block: &mut DataBlock) -> Result<(), Error> {
         let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
         let card_capacity = self.info.get_capacity();
 
@@ -431,9 +434,10 @@ impl<'a, 'b, A: Addressable> StorageDevice<'a, 'b, A> {
         self.sdmmc
             .cmd(common_cmd::set_block_length(size_of::<DataBlock>() as u32), false)?; // CMD16
 
-        let transfer = self
-            .sdmmc
-            .prepare_datapath_read(&mut buffer.0, block_size(size_of::<DataBlock>()), false);
+        let transfer = self.sdmmc.prepare_datapath_read(
+            aligned_mut(&mut data_block.0),
+            DatapathMode::Block(block_size(size_of::<DataBlock>())),
+        );
         self.sdmmc.cmd(common_cmd::read_single_block(address), true)?;
 
         self.sdmmc.complete_datapath_transfer(transfer, true).await?;
@@ -464,9 +468,10 @@ impl<'a, 'b, A: Addressable> StorageDevice<'a, 'b, A> {
         self.sdmmc
             .cmd(common_cmd::set_block_length(size_of::<DataBlock>() as u32), false)?; // CMD16
 
-        let transfer = self
-            .sdmmc
-            .prepare_datapath_read(buffer, block_size(size_of::<DataBlock>()), false);
+        let transfer = self.sdmmc.prepare_datapath_read(
+            aligned_mut(buffer),
+            DatapathMode::Block(block_size(size_of::<DataBlock>())),
+        );
         self.sdmmc.cmd(common_cmd::read_multiple_blocks(address), true)?;
 
         self.sdmmc.complete_datapath_transfer(transfer, false).await?;
@@ -497,9 +502,10 @@ impl<'a, 'b, A: Addressable> StorageDevice<'a, 'b, A> {
         #[cfg(sdmmc_v1)]
         self.sdmmc.cmd(common_cmd::write_single_block(address), true)?;
 
-        let transfer = self
-            .sdmmc
-            .prepare_datapath_write(&buffer.0, block_size(size_of::<DataBlock>()), false);
+        let transfer = self.sdmmc.prepare_datapath_write(
+            aligned_ref(&buffer.0),
+            DatapathMode::Block(block_size(size_of::<DataBlock>())),
+        );
 
         #[cfg(sdmmc_v2)]
         self.sdmmc.cmd(common_cmd::write_single_block(address), true)?;
@@ -548,10 +554,10 @@ impl<'a, 'b, A: Addressable> StorageDevice<'a, 'b, A> {
         self.sdmmc.cmd(common_cmd::write_multiple_blocks(address), true)?; // CMD25
 
         // Setup write command
-        let transfer = self
-            .sdmmc
-            .prepare_datapath_write(buffer, block_size(size_of::<DataBlock>()), false);
-
+        let transfer = self.sdmmc.prepare_datapath_write(
+            aligned_ref(buffer),
+            DatapathMode::Block(block_size(size_of::<DataBlock>())),
+        );
         #[cfg(sdmmc_v2)]
         self.sdmmc.cmd(common_cmd::write_multiple_blocks(address), true)?; // CMD25
 
diff --git a/embassy-stm32/src/sdmmc/sdio.rs b/embassy-stm32/src/sdmmc/sdio.rs
index 1412b21fc..e436d68cb 100644
--- a/embassy-stm32/src/sdmmc/sdio.rs
+++ b/embassy-stm32/src/sdmmc/sdio.rs
@@ -1,10 +1,11 @@
 use core::ops::{Deref, DerefMut};
 
+use aligned::{A4, Aligned};
 use sdio_host::common_cmd::{R1, Rz, cmd};
 use sdio_host::sd::BusWidth;
 use sdio_host::sd_cmd;
 
-use crate::sdmmc::{Error, Sdmmc, block_size, slice8_mut, slice8_ref};
+use crate::sdmmc::{DatapathMode, Error, Sdmmc, aligned_mut, aligned_ref, block_size, slice8_mut, slice8_ref};
 use crate::time::Hertz;
 
 /// Aligned data block for SDMMC transfers.
@@ -39,7 +40,7 @@ impl DerefMut for DataBlock {
 /// Storage Device
 pub struct SerialDataInterface<'a, 'b> {
     /// Inner member
-    pub sdmmc: &'a mut Sdmmc<'b>,
+    sdmmc: &'a mut Sdmmc<'b>,
 }
 
 /// Card Storage Device
@@ -101,9 +102,10 @@ impl<'a, 'b> SerialDataInterface<'a, 'b> {
             )
         };
 
-        let transfer = self
-            .sdmmc
-            .prepare_datapath_read(buffer, block_size(size_of::<DataBlock>()), false);
+        let transfer = self.sdmmc.prepare_datapath_read(
+            aligned_mut(buffer),
+            DatapathMode::Block(block_size(size_of::<DataBlock>())),
+        );
         self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
 
         self.sdmmc.complete_datapath_transfer(transfer, false).await?;
@@ -113,12 +115,10 @@ impl<'a, 'b> SerialDataInterface<'a, 'b> {
     }
 
     /// Read in multibyte mode using cmd53
-    pub async fn cmd53_byte_read(&mut self, arg: u32, buffer: &mut [u32]) -> Result<(), Error> {
+    pub async fn cmd53_byte_read(&mut self, arg: u32, buffer: &mut Aligned<A4, [u8]>) -> Result<(), Error> {
         let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
 
-        let transfer = self
-            .sdmmc
-            .prepare_datapath_read(buffer, block_size(size_of::<DataBlock>()), true);
+        let transfer = self.sdmmc.prepare_datapath_read(buffer, DatapathMode::Byte);
         self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
 
         self.sdmmc.complete_datapath_transfer(transfer, false).await?;
@@ -142,9 +142,10 @@ impl<'a, 'b> SerialDataInterface<'a, 'b> {
         #[cfg(sdmmc_v1)]
         self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
 
-        let transfer = self
-            .sdmmc
-            .prepare_datapath_read(buffer, block_size(size_of::<DataBlock>()), false);
+        let transfer = self.sdmmc.prepare_datapath_write(
+            aligned_ref(buffer),
+            DatapathMode::Block(block_size(size_of::<DataBlock>())),
+        );
 
         #[cfg(sdmmc_v2)]
         self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
@@ -164,7 +165,7 @@ impl<'a, 'b> SerialDataInterface<'a, 'b> {
 
         let transfer = self
             .sdmmc
-            .prepare_datapath_write(buffer, block_size(size_of::<DataBlock>()), true);
+            .prepare_datapath_write(aligned_ref(buffer), DatapathMode::Byte);
 
         #[cfg(sdmmc_v2)]
         self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index af51b79b4..13ff31a34 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -1126,7 +1126,7 @@ impl<'d, M: PeriMode, CM: CommunicationMode> Drop for Spi<'d, M, CM> {
         self.miso.as_ref().map(|x| x.set_as_disconnected());
         self.nss.as_ref().map(|x| x.set_as_disconnected());
 
-        self.info.rcc.disable();
+        self.info.rcc.disable_without_stop();
     }
 }
 
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index 3e1482b67..905f2de1a 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -156,6 +156,48 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
         self.new_future(channel, InputCaptureMode::BothEdges, InputTISelection::Alternate)
             .await
     }
+
+    /// Capture a sequence of timer input edges into a buffer using DMA
+    pub async fn receive_waveform<M>(&mut self, dma: Peri<'_, impl super::Dma<T, M>>, buf: &mut [u16])
+    where
+        M: TimerChannel,
+    {
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        let original_enable_state = self.is_enabled(M::CHANNEL);
+        let original_cc_dma_enable_state = self.inner.get_cc_dma_enable_state(M::CHANNEL);
+
+        self.inner.set_input_ti_selection(M::CHANNEL, InputTISelection::Normal);
+        self.inner
+            .set_input_capture_mode(M::CHANNEL, InputCaptureMode::BothEdges);
+
+        if !original_cc_dma_enable_state {
+            self.inner.set_cc_dma_enable_state(M::CHANNEL, true);
+        }
+
+        if !original_enable_state {
+            self.enable(M::CHANNEL);
+        }
+
+        unsafe {
+            use crate::dma::{Transfer, TransferOptions};
+
+            Transfer::new_read(
+                dma,
+                req,
+                self.inner.regs_gp16().ccr(M::CHANNEL.index()).as_ptr() as *mut u16,
+                buf,
+                TransferOptions::default(),
+            )
+            .await
+        };
+
+        // restore output compare state
+        if !original_enable_state {
+            self.disable(M::CHANNEL);
+        }
+    }
 }
 
 #[must_use = "futures do nothing unless you `.await` or poll them"]
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 9a5f0fd1d..4ffa58778 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -97,6 +97,11 @@ impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
         self.timer.get_channel_enable_state(self.channel)
     }
 
+    /// Get the frequency of the PWM channel.
+    pub fn get_frequency(&self) -> Hertz {
+        self.timer.get_frequency()
+    }
+
     /// Get max duty value.
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
@@ -330,6 +335,11 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
         self.inner.set_frequency_internal(freq * multiplier, 16);
     }
 
+    /// Get the PWM driver frequency.
+    pub fn get_frequency(&self) -> Hertz {
+        self.inner.get_frequency()
+    }
+
     /// Get max duty value.
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
diff --git a/embassy-sync/src/pipe.rs b/embassy-sync/src/pipe.rs
index 215a556d9..d6c21299a 100644
--- a/embassy-sync/src/pipe.rs
+++ b/embassy-sync/src/pipe.rs
@@ -393,7 +393,7 @@ where
     /// Attempt to immediately write some bytes to the pipe.
     ///
     /// This method will either write a nonzero amount of bytes to the pipe immediately,
-    /// or return an error if the pipe is empty. See [`write`](Self::write) for a variant
+    /// or return an error if the pipe is full. See [`write`](Self::write) for a variant
     /// that waits instead of returning an error.
     pub fn try_write(&self, buf: &[u8]) -> Result<usize, TryWriteError> {
         self.try_write_with_context(None, buf)
diff --git a/embassy-usb-dfu/Cargo.toml b/embassy-usb-dfu/Cargo.toml
index 8b32582c0..4f952a047 100644
--- a/embassy-usb-dfu/Cargo.toml
+++ b/embassy-usb-dfu/Cargo.toml
@@ -35,7 +35,7 @@ features = ["defmt", "cortex-m", "dfu"]
 defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.17", optional = true }
 
-bitflags = "2.4.1"
+bitflags = "2.10.0"
 cortex-m = { version = "0.7.7", features = ["inline-asm"], optional = true }
 embassy-boot = { version = "0.6.1", path = "../embassy-boot" }
 embassy-futures = { version = "0.1.2", path = "../embassy-futures" }
diff --git a/embassy-usb/src/msos.rs b/embassy-usb/src/msos.rs
index 66689871e..6d7f87061 100644
--- a/embassy-usb/src/msos.rs
+++ b/embassy-usb/src/msos.rs
@@ -110,10 +110,6 @@ impl<'d> MsOsDescriptorWriter<'d> {
             !self.is_empty(),
             "device features may only be added after the header is written"
         );
-        assert!(
-            self.config_mark.is_none(),
-            "device features must be added before the first configuration subset"
-        );
         self.write(desc);
     }
 
diff --git a/examples/boot/application/nrf/Cargo.toml b/examples/boot/application/nrf/Cargo.toml
index 79286e295..ccaa24e3e 100644
--- a/examples/boot/application/nrf/Cargo.toml
+++ b/examples/boot/application/nrf/Cargo.toml
@@ -9,9 +9,9 @@ publish = false
 embassy-sync = { version = "0.7.2", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.9.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.5.0", path = "../../../../embassy-time", features = [] }
-embassy-nrf = { version = "0.8.0", path = "../../../../embassy-nrf", features = ["gpiote", ] }
+embassy-nrf = { version = "0.9.0", path = "../../../../embassy-nrf", features = ["gpiote", ] }
 embassy-boot = { version = "0.6.1", path = "../../../../embassy-boot", features = [] }
-embassy-boot-nrf = { version = "0.9.0", path = "../../../../embassy-boot-nrf", features = [] }
+embassy-boot-nrf = { version = "0.10.0", path = "../../../../embassy-boot-nrf", features = [] }
 embassy-embedded-hal = { version = "0.5.0", path = "../../../../embassy-embedded-hal" }
 
 defmt = { version = "1.0.1", optional = true }
diff --git a/examples/mcxa/Cargo.toml b/examples/mcxa/Cargo.toml
index d07cc4272..347659f5b 100644
--- a/examples/mcxa/Cargo.toml
+++ b/examples/mcxa/Cargo.toml
@@ -21,6 +21,7 @@ embassy-time-driver = "0.2.1"
 embedded-io-async = "0.6.1"
 heapless = "0.9.2"
 panic-probe = { version = "1.0", features = ["print-defmt"] }
+rand_core = "0.9"
 static_cell = "2.1.1"
 tmp108 = "0.4.0"
 
diff --git a/examples/mcxa/src/bin/trng.rs b/examples/mcxa/src/bin/trng.rs
new file mode 100644
index 000000000..5f6e2408c
--- /dev/null
+++ b/examples/mcxa/src/bin/trng.rs
@@ -0,0 +1,106 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use hal::bind_interrupts;
+use hal::config::Config;
+use hal::trng::{self, InterruptHandler, Trng};
+use rand_core::RngCore;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+bind_interrupts!(
+    struct Irqs {
+        TRNG0 => InterruptHandler;
+    }
+);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let config = Config::default();
+    let mut p = hal::init(config);
+
+    defmt::info!("TRNG example");
+
+    let mut trng = Trng::new_blocking_128(p.TRNG0.reborrow());
+    let rand = trng.blocking_next_u32();
+    defmt::info!("128-bit {}", rand);
+
+    drop(trng);
+
+    let mut trng = Trng::new_blocking_256(p.TRNG0.reborrow());
+    let rand = trng.blocking_next_u32();
+    defmt::info!("256-bit {}", rand);
+
+    drop(trng);
+
+    let mut trng = Trng::new_blocking_512(p.TRNG0.reborrow());
+    let rand = trng.blocking_next_u32();
+    defmt::info!("512-bit {}", rand);
+
+    drop(trng);
+
+    let config = trng::Config::default();
+    let mut trng = Trng::new_blocking_with_custom_config(p.TRNG0.reborrow(), config);
+
+    defmt::info!("========== BLOCKING ==========");
+
+    defmt::info!("Generate 10 u32");
+    for _ in 0..10 {
+        let rand = trng.blocking_next_u32();
+        defmt::info!("{}", rand);
+    }
+
+    defmt::info!("Generate 10 u64");
+    for _ in 0..10 {
+        let rand = trng.blocking_next_u64();
+        defmt::info!("{}", rand);
+    }
+
+    let mut buf = [0_u8; 256];
+
+    defmt::info!("Generate 10 256-byte buffers");
+    for _ in 0..10 {
+        trng.blocking_fill_bytes(&mut buf);
+        defmt::info!("{:02x}", buf);
+    }
+
+    defmt::info!("RngCore");
+
+    for _ in 0..10 {
+        defmt::info!("u32: {}", trng.next_u32());
+        defmt::info!("u64: {}", trng.next_u64());
+    }
+
+    drop(trng);
+
+    defmt::info!("========== ASYNC ==========");
+
+    let mut trng = Trng::new_with_custom_config(p.TRNG0.reborrow(), Irqs, config);
+
+    defmt::info!("Generate 10 u32");
+    for _ in 0..10 {
+        let rand = trng.async_next_u32().await.unwrap();
+        defmt::info!("{}", rand);
+    }
+
+    defmt::info!("Generate 10 u64");
+    for _ in 0..10 {
+        let rand = trng.async_next_u64().await.unwrap();
+        defmt::info!("{}", rand);
+    }
+
+    let mut buf = [0_u8; 256];
+
+    defmt::info!("Generate 10 256-byte buffers");
+    for _ in 0..10 {
+        trng.async_fill_bytes(&mut buf).await.unwrap();
+        defmt::info!("{:02x}", buf);
+    }
+
+    defmt::info!("RngCore");
+
+    for _ in 0..10 {
+        defmt::info!("u32: {}", trng.next_u32());
+        defmt::info!("u64: {}", trng.next_u64());
+    }
+}
diff --git a/examples/mimxrt6/Cargo.toml b/examples/mimxrt6/Cargo.toml
index dc09e97e7..ada112833 100644
--- a/examples/mimxrt6/Cargo.toml
+++ b/examples/mimxrt6/Cargo.toml
@@ -21,6 +21,8 @@ embedded-hal-async = "1.0.0"
 
 mimxrt600-fcb = "0.2.2"
 panic-probe = { version = "1.0.0", features = ["print-defmt"] }
+embedded-hal-bus = "0.3.0"
+is31fl3743b-driver = { version = "0.1.1", features = ["is_blocking"] }
 
 # cargo build/run
 [profile.dev]
diff --git a/examples/mimxrt6/src/bin/dma.rs b/examples/mimxrt6/src/bin/dma.rs
new file mode 100644
index 000000000..b490efc6b
--- /dev/null
+++ b/examples/mimxrt6/src/bin/dma.rs
@@ -0,0 +1,26 @@
+#![no_std]
+#![no_main]
+
+extern crate embassy_imxrt_examples;
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_imxrt::dma::copy;
+use {defmt_rtt as _, panic_probe as _};
+
+const BUFLEN: usize = 1024;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_imxrt::init(Default::default());
+
+    info!("Test memory-to-memory DMA transfers");
+
+    let src = [0x55u8; BUFLEN];
+    let mut dst = [0u8; BUFLEN];
+
+    unsafe { copy(p.DMA0_CH0, &src, &mut dst) }.await;
+    assert!(dst == src);
+
+    info!("DMA copy succeeded");
+}
diff --git a/examples/mimxrt6/src/bin/spi-async.rs b/examples/mimxrt6/src/bin/spi-async.rs
new file mode 100644
index 000000000..aa56f7c42
--- /dev/null
+++ b/examples/mimxrt6/src/bin/spi-async.rs
@@ -0,0 +1,35 @@
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_imxrt::bind_interrupts;
+use embassy_imxrt::flexcomm::spi::{InterruptHandler, Spi};
+use embassy_imxrt::peripherals::FLEXCOMM5;
+use {defmt_rtt as _, embassy_imxrt_examples as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    FLEXCOMM5 => InterruptHandler<FLEXCOMM5>;
+});
+
+const BUFLEN: usize = 1024;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_imxrt::init(Default::default());
+
+    info!("Initializing SPI");
+
+    let mut spi = Spi::new_async(p.FLEXCOMM5, p.PIO1_3, p.PIO1_5, p.PIO1_4, Irqs, Default::default());
+
+    let mut rxbuf = [0x55; BUFLEN];
+    let txbuf = [0xaa; BUFLEN];
+
+    for _ in 0..10 {
+        spi.async_transfer(&mut rxbuf, &txbuf).await.unwrap();
+        assert!(rxbuf.iter().all(|b| *b == 0xaa));
+        rxbuf.fill(0x55);
+    }
+
+    info!("SPI transfers succeeded");
+}
diff --git a/examples/mimxrt6/src/bin/spi.rs b/examples/mimxrt6/src/bin/spi.rs
new file mode 100644
index 000000000..4854432e8
--- /dev/null
+++ b/examples/mimxrt6/src/bin/spi.rs
@@ -0,0 +1,51 @@
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_imxrt::flexcomm::spi::Spi;
+use embassy_imxrt::gpio;
+use embassy_time::{Delay, Timer};
+use embedded_hal_bus::spi::ExclusiveDevice;
+use is31fl3743b_driver::{CSy, Is31fl3743b, SWx};
+use {defmt_rtt as _, embassy_imxrt_examples as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_imxrt::init(Default::default());
+
+    info!("Initializing SPI");
+
+    let cs = gpio::Output::new(
+        p.PIO1_6,
+        gpio::Level::Low,
+        gpio::DriveMode::PushPull,
+        gpio::DriveStrength::Normal,
+        gpio::SlewRate::Standard,
+    );
+
+    let spi = Spi::new_blocking(p.FLEXCOMM5, p.PIO1_3, p.PIO1_5, p.PIO1_4, Default::default());
+    let delay = Delay;
+
+    // One SPI device only on the SPI bus
+    let spi_dev = ExclusiveDevice::new(spi, cs, delay).unwrap();
+
+    // Instantiate IS31FL3743B device
+    let mut driver = Is31fl3743b::new(spi_dev).unwrap();
+
+    // Enable phase delay to help reduce power noise
+    let _ = driver.enable_phase_delay();
+    // Set global current, check method documentation for more info
+    let _ = driver.set_global_current(90);
+
+    let _ = driver.set_led_peak_current_bulk(SWx::SW1, CSy::CS1, &[100; 11 * 18]);
+
+    // Driver is fully set up, we can now start turning on LEDs!
+    // Create a white breathing effect
+    loop {
+        for brightness in (0..=255_u8).chain((0..=255).rev()) {
+            let _ = driver.set_led_brightness_bulk(SWx::SW1, CSy::CS1, &[brightness; 11 * 18]);
+            Timer::after_micros(1).await;
+        }
+    }
+}
diff --git a/examples/mspm0g5187/.cargo/config.toml b/examples/mspm0g5187/.cargo/config.toml
new file mode 100644
index 000000000..ea407b411
--- /dev/null
+++ b/examples/mspm0g5187/.cargo/config.toml
@@ -0,0 +1,9 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# replace MSPM0G5187 with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --restore-unwritten --verify --chip MSPM0G5187 --protocol=swd"
+
+[build]
+target = "thumbv6m-none-eabi"
+
+[env]
+DEFMT_LOG = "trace"
diff --git a/examples/mspm0g5187/Cargo.toml b/examples/mspm0g5187/Cargo.toml
new file mode 100644
index 000000000..3d64a127a
--- /dev/null
+++ b/examples/mspm0g5187/Cargo.toml
@@ -0,0 +1,27 @@
+[package]
+edition = "2024"
+name = "embassy-mspm0-g5187-examples"
+version = "0.1.0"
+license = "MIT OR Apache-2.0"
+publish = false
+
+[dependencies]
+embassy-mspm0 = { version = "0.1.0", path = "../../embassy-mspm0", features = ["mspm0g5187pm", "defmt", "rt", "time-driver-any"] }
+embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt"] }
+embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
+embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt"] }
+panic-halt = "1.0.0"
+cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = { version = "0.7.0"}
+defmt = "1.0.1"
+defmt-rtt = "1.0.0"
+panic-probe = { version = "1.0.0", features = ["print-defmt"] }
+panic-semihosting = "0.6.0"
+
+[profile.release]
+debug = 2
+
+[package.metadata.embassy]
+build = [
+  { target = "thumbv6m-none-eabi", artifact-dir = "out/examples/mspm0g5187" }
+]
diff --git a/examples/mspm0g5187/README.md b/examples/mspm0g5187/README.md
new file mode 100644
index 000000000..12e7846fb
--- /dev/null
+++ b/examples/mspm0g5187/README.md
@@ -0,0 +1,27 @@
+# Examples for MSPM0G5187
+
+Run individual examples with
+```
+cargo run --bin <module-name>
+```
+for example
+```
+cargo run --bin blinky
+```
+
+## Checklist before running examples
+A large number of the examples are written for the [LP-MSPM0G5187](https://www.ti.com/tool/LP-MSPM0G5187) board.
+
+You might need to adjust `.cargo/config.toml`, `Cargo.toml` and possibly update pin numbers or peripherals to match the specific MCU or board you are using.
+
+* [ ] Update .cargo/config.toml with the correct probe-rs command to use your specific MCU. For example for G5187 it should be `probe-rs run --chip MSPM0G5187`. (use `probe-rs chip list` to find your chip)
+* [ ] Update Cargo.toml to have the correct `embassy-mspm0` feature. For the LP-MSPM0G3519 it should be `mspm0g3519pz`. Look in the `Cargo.toml` file of the `embassy-mspm0` project to find the correct feature flag for your chip.
+* [ ] If your board has a special clock or power configuration, make sure that it is set up appropriately.
+* [ ] If your board has different pin mapping, update any pin numbers or peripherals in the given example code to match your schematic
+
+If you are unsure, please drop by the Embassy Matrix chat for support, and let us know:
+
+* Which example you are trying to run
+* Which chip and board you are using
+
+Embassy Chat: https://matrix.to/#/#embassy-rs:matrix.org
diff --git a/examples/mspm0g5187/build.rs b/examples/mspm0g5187/build.rs
new file mode 100644
index 000000000..2d777c2d3
--- /dev/null
+++ b/examples/mspm0g5187/build.rs
@@ -0,0 +1,37 @@
+//! This build script copies the `memory.x` file from the crate root into
+//! a directory where the linker can always find it at build time.
+//! For many projects this is optional, as the linker always searches the
+//! project root directory -- wherever `Cargo.toml` is. However, if you
+//! are using a workspace or have a more complicated build setup, this
+//! build script becomes required. Additionally, by requesting that
+//! Cargo re-run the build script whenever `memory.x` is changed,
+//! updating `memory.x` ensures a rebuild of the application with the
+//! new memory settings.
+
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put `memory.x` in our output directory and ensure it's
+    // on the linker search path.
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // By default, Cargo will re-run a build script whenever
+    // any file in the project changes. By specifying `memory.x`
+    // here, we ensure the build script is only re-run when
+    // `memory.x` is changed.
+    println!("cargo:rerun-if-changed=memory.x");
+
+    println!("cargo:rustc-link-arg-bins=--nmagic");
+    println!("cargo:rustc-link-arg-bins=-Tlink.x");
+    println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+    // You must tell cargo to link interrupt groups if the rt feature is enabled.
+    println!("cargo:rustc-link-arg-bins=-Tinterrupt_group.x");
+}
diff --git a/examples/mspm0g5187/memory.x b/examples/mspm0g5187/memory.x
new file mode 100644
index 000000000..37e381fbd
--- /dev/null
+++ b/examples/mspm0g5187/memory.x
@@ -0,0 +1,6 @@
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 128K
+  /* Select non-parity range of SRAM due to SRAM_ERR_01 errata in SLAZ758 */
+  RAM   : ORIGIN = 0x20200000, LENGTH = 32K
+}
diff --git a/examples/mspm0g5187/src/bin/blinky.rs b/examples/mspm0g5187/src/bin/blinky.rs
new file mode 100644
index 000000000..47eaf1535
--- /dev/null
+++ b/examples/mspm0g5187/src/bin/blinky.rs
@@ -0,0 +1,25 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_mspm0::Config;
+use embassy_mspm0::gpio::{Level, Output};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_halt as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    info!("Hello world!");
+    let p = embassy_mspm0::init(Config::default());
+
+    let mut led1 = Output::new(p.PA0, Level::Low);
+    led1.set_inversion(true);
+
+    loop {
+        Timer::after_millis(400).await;
+
+        info!("Toggle");
+        led1.toggle();
+    }
+}
diff --git a/examples/mspm0g5187/src/bin/button.rs b/examples/mspm0g5187/src/bin/button.rs
new file mode 100644
index 000000000..2ed15e354
--- /dev/null
+++ b/examples/mspm0g5187/src/bin/button.rs
@@ -0,0 +1,33 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_mspm0::Config;
+use embassy_mspm0::gpio::{Input, Level, Output, Pull};
+use {defmt_rtt as _, panic_halt as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    info!("Hello world!");
+
+    let p = embassy_mspm0::init(Config::default());
+
+    let led1 = p.PA0;
+    let s2 = p.PA7;
+
+    let mut led1 = Output::new(led1, Level::Low);
+
+    let mut s2 = Input::new(s2, Pull::Up);
+
+    // led1 is active low
+    led1.set_high();
+
+    loop {
+        s2.wait_for_falling_edge().await;
+
+        info!("Switch 2 was pressed");
+
+        led1.toggle();
+    }
+}
diff --git a/examples/mspm0g5187/src/bin/wwdt.rs b/examples/mspm0g5187/src/bin/wwdt.rs
new file mode 100644
index 000000000..a5de781f3
--- /dev/null
+++ b/examples/mspm0g5187/src/bin/wwdt.rs
@@ -0,0 +1,54 @@
+//! Example of using window watchdog timer in the MSPM0G5187 chip.
+//!
+//! It tests the use case when watchdog timer is expired and when watchdog is pet too early.
+
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_mspm0::gpio::{Level, Output};
+use embassy_mspm0::wwdt::{ClosedWindowPercentage, Config, Timeout, Watchdog};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_halt as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    info!("Hello world!");
+
+    let p = embassy_mspm0::init(Default::default());
+    let mut conf = Config::default();
+    conf.timeout = Timeout::Sec1;
+
+    // watchdog also resets the system if the pet comes too early,
+    // less than 250 msec == 25% from 1 sec
+    conf.closed_window = ClosedWindowPercentage::TwentyFive;
+    let mut wdt = Watchdog::new(p.WWDT0, conf);
+    info!("Started the watchdog timer");
+
+    let mut led1 = Output::new(p.PA0, Level::High);
+    led1.set_inversion(true);
+    Timer::after_millis(900).await;
+
+    for _ in 1..=5 {
+        info!("pet watchdog");
+        led1.toggle();
+        wdt.pet();
+        Timer::after_millis(500).await;
+    }
+
+    // watchdog timeout test
+    info!("Stopped the pet command, device will reset in less than 1 second");
+    loop {
+        led1.toggle();
+        Timer::after_millis(500).await;
+    }
+
+    // watchdog "too early" test
+    // info!("Device will reset when the pet comes too early");
+    // loop {
+    //     led1.toggle();
+    //     wdt.pet();
+    //     Timer::after_millis(200).await;
+    // }
+}
diff --git a/examples/nrf-rtos-trace/Cargo.toml b/examples/nrf-rtos-trace/Cargo.toml
index 5caabf228..3d6b5e60a 100644
--- a/examples/nrf-rtos-trace/Cargo.toml
+++ b/examples/nrf-rtos-trace/Cargo.toml
@@ -19,7 +19,7 @@ log = [
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync" }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "rtos-trace"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time" }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = ["nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac"] }
 
 cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
 cortex-m-rt = "0.7.0"
diff --git a/examples/nrf51/Cargo.toml b/examples/nrf51/Cargo.toml
index c7492f562..e8375952b 100644
--- a/examples/nrf51/Cargo.toml
+++ b/examples/nrf51/Cargo.toml
@@ -8,7 +8,7 @@ publish = false
 [dependencies]
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "gpiote", "time-driver-rtc1", "unstable-pac", "time", "rt"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "gpiote", "time-driver-rtc1", "unstable-pac", "time", "rt"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf52810/Cargo.toml b/examples/nrf52810/Cargo.toml
index 1711a3d8d..73d129f91 100644
--- a/examples/nrf52810/Cargo.toml
+++ b/examples/nrf52810/Cargo.toml
@@ -10,7 +10,7 @@ embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["defmt", "nrf52810", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = ["defmt", "nrf52810", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf52840-edf/Cargo.toml b/examples/nrf52840-edf/Cargo.toml
index 8b1db4652..8066a1150 100644
--- a/examples/nrf52840-edf/Cargo.toml
+++ b/examples/nrf52840-edf/Cargo.toml
@@ -9,7 +9,7 @@ publish = false
 # NOTE: "scheduler-deadline" and "embassy-time-driver" features are enabled
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "scheduler-deadline", "embassy-time-driver"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf52840-rtic/Cargo.toml b/examples/nrf52840-rtic/Cargo.toml
index 26b21598f..13a7724fa 100644
--- a/examples/nrf52840-rtic/Cargo.toml
+++ b/examples/nrf52840-rtic/Cargo.toml
@@ -12,7 +12,7 @@ embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = [ "defmt", "defmt-timestamp-uptime"] }
 embassy-time-queue-utils = { version = "0.3.0", path = "../../embassy-time-queue-utils", features = ["generic-queue-8"] }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = [ "defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = [ "defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf52840/Cargo.toml b/examples/nrf52840/Cargo.toml
index 1fe3d2419..a57bd7b24 100644
--- a/examples/nrf52840/Cargo.toml
+++ b/examples/nrf52840/Cargo.toml
@@ -10,7 +10,7 @@ embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time", "net-driver"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time", "net-driver"] }
 embassy-net = { version = "0.7.1", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet","udp", "medium-ieee802154", "proto-ipv6"] }
 embassy-usb = { version = "0.5.1", path = "../../embassy-usb", features = ["defmt"] }
 embedded-io = { version = "0.6.0", features = ["defmt-03"]  }
diff --git a/examples/nrf5340/Cargo.toml b/examples/nrf5340/Cargo.toml
index 97efe58e8..b8d5dbfb1 100644
--- a/examples/nrf5340/Cargo.toml
+++ b/examples/nrf5340/Cargo.toml
@@ -10,7 +10,7 @@ embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["defmt", "nrf5340-app-s", "time-driver-rtc1", "gpiote", "unstable-pac"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = ["defmt", "nrf5340-app-s", "time-driver-rtc1", "gpiote", "unstable-pac"] }
 embassy-net = { version = "0.7.1", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet"] }
 embassy-usb = { version = "0.5.1", path = "../../embassy-usb", features = ["defmt"] }
 embedded-io-async = { version = "0.6.1" }
diff --git a/examples/nrf54l15/Cargo.toml b/examples/nrf54l15/Cargo.toml
index f34df0f26..353d1b46e 100644
--- a/examples/nrf54l15/Cargo.toml
+++ b/examples/nrf54l15/Cargo.toml
@@ -10,7 +10,7 @@ embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["defmt", "nrf54l15-app-s", "time-driver-grtc", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = ["defmt", "nrf54l15-app-s", "time-driver-grtc", "gpiote", "unstable-pac", "time"] }
 embedded-io = { version = "0.6.0", features = ["defmt-03"]  }
 embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
 
diff --git a/examples/nrf54l15/src/bin/nvmc.rs b/examples/nrf54l15/src/bin/rramc.rs
index f990604cd..f990604cd 100644
--- a/examples/nrf54l15/src/bin/nvmc.rs
+++ b/examples/nrf54l15/src/bin/rramc.rs
diff --git a/examples/nrf54l15/src/bin/rramc_buffered.rs b/examples/nrf54l15/src/bin/rramc_buffered.rs
new file mode 100644
index 000000000..06c9585ed
--- /dev/null
+++ b/examples/nrf54l15/src/bin/rramc_buffered.rs
@@ -0,0 +1,59 @@
+#![no_std]
+#![no_main]
+
+use defmt::{info, unwrap};
+use embassy_executor::Spawner;
+use embassy_nrf::rramc::{Buffered, PAGE_SIZE, Rramc};
+use embedded_storage::nor_flash::{NorFlash, ReadNorFlash};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_nrf::init(Default::default());
+    info!("Hello RRAMC NVMC!");
+
+    // Buffer 8 word lines
+    let mut f: Rramc<'_, Buffered<128>> = Rramc::new_buffered(p.RRAMC);
+
+    const ADDR: u32 = 0x80000;
+    let mut buf = [0u8; 4];
+
+    info!("Reading...");
+    unwrap!(f.read(ADDR, &mut buf));
+    info!("Read: {=[u8]:x}", buf);
+
+    info!("Erasing...");
+    unwrap!(f.erase(ADDR, ADDR + PAGE_SIZE as u32));
+
+    info!("Reading...");
+    unwrap!(f.read(ADDR, &mut buf));
+    info!("Read: {=[u8]:x}", buf);
+
+    info!("Writing...");
+    // 16 B (128-bit) write minimum
+    let out: [u8; 256] = [
+        0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa,
+        0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa,
+        0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb,
+        0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb,
+        0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc,
+        0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc,
+        0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd,
+        0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd,
+        0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa,
+        0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa,
+        0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb,
+        0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb,
+        0xcc, 0xcc, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc,
+        0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd, 0xaa, 0xaa, 0xaa, 0xaa, 0xbb, 0xbb, 0xbb, 0xbb, 0xcc, 0xcc, 0xcc, 0xcc,
+        0xdd, 0xdd, 0xdd, 0xdd,
+    ];
+    unwrap!(f.write(ADDR, &out));
+
+    info!("Reading...");
+    // Can read arbitrary sizes
+    for addr in (ADDR..ADDR + 256).step_by(4) {
+        unwrap!(f.read(addr, &mut buf));
+        info!("Read: {=[u8]:x}", buf);
+    }
+}
diff --git a/examples/nrf54lm20/Cargo.toml b/examples/nrf54lm20/Cargo.toml
index 5482fc77a..e3bf22b25 100644
--- a/examples/nrf54lm20/Cargo.toml
+++ b/examples/nrf54lm20/Cargo.toml
@@ -10,7 +10,7 @@ embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["defmt", "nrf54lm20-app-s", "time-driver-grtc", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = ["defmt", "nrf54lm20-app-s", "time-driver-grtc", "gpiote", "unstable-pac", "time"] }
 embedded-io = { version = "0.6.0", features = ["defmt-03"]  }
 embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
 
diff --git a/examples/nrf9151/ns/Cargo.toml b/examples/nrf9151/ns/Cargo.toml
index 7f1f5239a..f6d6aab6f 100644
--- a/examples/nrf9151/ns/Cargo.toml
+++ b/examples/nrf9151/ns/Cargo.toml
@@ -8,7 +8,7 @@ publish = false
 [dependencies]
 embassy-executor = { version = "0.9.0", path = "../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.8.0", path = "../../../embassy-nrf", features = ["defmt", "nrf9120-ns", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.9.0", path = "../../../embassy-nrf", features = ["defmt", "nrf9120-ns", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf9151/s/Cargo.toml b/examples/nrf9151/s/Cargo.toml
index ce71cc456..1c9e7fb35 100644
--- a/examples/nrf9151/s/Cargo.toml
+++ b/examples/nrf9151/s/Cargo.toml
@@ -8,7 +8,7 @@ publish = false
 [dependencies]
 embassy-executor = { version = "0.9.0", path = "../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.8.0", path = "../../../embassy-nrf", features = ["defmt", "nrf9120-s", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.9.0", path = "../../../embassy-nrf", features = ["defmt", "nrf9120-s", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf9160/Cargo.toml b/examples/nrf9160/Cargo.toml
index ae3b2eeb1..907b06e6d 100644
--- a/examples/nrf9160/Cargo.toml
+++ b/examples/nrf9160/Cargo.toml
@@ -8,7 +8,7 @@ publish = false
 [dependencies]
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["defmt", "nrf9160-s", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = ["defmt", "nrf9160-s", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 embassy-net-nrf91 = { version = "0.1.0", path = "../../embassy-net-nrf91", features = ["defmt"] }
 embassy-net = { version = "0.7.1", path = "../../embassy-net", features = ["defmt", "tcp", "proto-ipv4", "medium-ip"] }
 
diff --git a/examples/rp/src/bin/usb_webusb.rs b/examples/rp/src/bin/usb_webusb.rs
index 5cecb92f0..edc9a0c52 100644
--- a/examples/rp/src/bin/usb_webusb.rs
+++ b/examples/rp/src/bin/usb_webusb.rs
@@ -26,6 +26,7 @@ use embassy_rp::usb::{Driver as UsbDriver, InterruptHandler};
 use embassy_usb::class::web_usb::{Config as WebUsbConfig, State, Url, WebUsb};
 use embassy_usb::driver::{Driver, Endpoint, EndpointIn, EndpointOut};
 use embassy_usb::msos::{self, windows_version};
+use embassy_usb::types::InterfaceNumber;
 use embassy_usb::{Builder, Config};
 use {defmt_rtt as _, panic_probe as _};
 
@@ -56,7 +57,7 @@ async fn main(_spawner: Spawner) {
     let mut config_descriptor = [0; 256];
     let mut bos_descriptor = [0; 256];
     let mut control_buf = [0; 64];
-    let mut msos_descriptor = [0; 256];
+    let mut msos_descriptor = [0; 512];
 
     let webusb_config = WebUsbConfig {
         max_packet_size: 64,
@@ -83,6 +84,14 @@ async fn main(_spawner: Spawner) {
     // In principle you might want to call msos_feature() just on a specific function,
     // if your device also has other functions that still use standard class drivers.
     builder.msos_descriptor(windows_version::WIN8_1, 0);
+    builder.msos_writer().configuration(0);
+    builder.msos_writer().function(InterfaceNumber(0));
+    builder.msos_feature(msos::CompatibleIdFeatureDescriptor::new("WINUSB", ""));
+    builder.msos_feature(msos::RegistryPropertyFeatureDescriptor::new(
+        "DeviceInterfaceGUIDs",
+        msos::PropertyData::RegMultiSz(DEVICE_INTERFACE_GUIDS),
+    ));
+    builder.msos_writer().function(InterfaceNumber(1));
     builder.msos_feature(msos::CompatibleIdFeatureDescriptor::new("WINUSB", ""));
     builder.msos_feature(msos::RegistryPropertyFeatureDescriptor::new(
         "DeviceInterfaceGUIDs",
diff --git a/examples/std/Cargo.toml b/examples/std/Cargo.toml
index 6dc6a353d..0e3b3c6d5 100644
--- a/examples/std/Cargo.toml
+++ b/examples/std/Cargo.toml
@@ -10,7 +10,7 @@ embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["lo
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-std", "executor-thread", "log"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["log", "std", ] }
 embassy-net = { version = "0.7.1", path = "../../embassy-net", features=[ "log", "medium-ethernet", "medium-ip", "tcp", "udp", "dns", "dhcpv4", "proto-ipv6"] }
-embassy-net-tuntap = { version = "0.1.0", path = "../../embassy-net-tuntap" }
+embassy-net-tuntap = { version = "0.1.1", path = "../../embassy-net-tuntap" }
 embassy-net-ppp = { version = "0.2.1", path = "../../embassy-net-ppp", features = ["log"]}
 embedded-io-async = { version = "0.6.1" }
 embedded-io-adapters = { version = "0.6.1", features = ["futures-03"] }
diff --git a/examples/std/src/bin/net_ppp.rs b/examples/std/src/bin/net_ppp.rs
index 82272c798..685dbf3d3 100644
--- a/examples/std/src/bin/net_ppp.rs
+++ b/examples/std/src/bin/net_ppp.rs
@@ -52,7 +52,7 @@ async fn ppp_task(stack: Stack<'static>, mut runner: Runner<'static>, port: Seri
         password: b"mypass",
     };
 
-    runner
+    let r = runner
         .run(port, config, |ipv4| {
             let Some(addr) = ipv4.address else {
                 warn!("PPP did not provide an IP address.");
@@ -69,9 +69,10 @@ async fn ppp_task(stack: Stack<'static>, mut runner: Runner<'static>, port: Seri
             });
             stack.set_config_v4(config);
         })
-        .await
-        .unwrap();
-    unreachable!()
+        .await;
+    match r {
+        Err(e) => panic!("{:?}", e),
+    }
 }
 
 #[embassy_executor::task]
diff --git a/examples/std/src/bin/tick_cancel.rs b/examples/std/src/bin/tick_cancel.rs
new file mode 100644
index 000000000..54e44790f
--- /dev/null
+++ b/examples/std/src/bin/tick_cancel.rs
@@ -0,0 +1,47 @@
+use std::sync::atomic::{AtomicBool, Ordering};
+use std::thread;
+use std::time::Duration;
+
+use embassy_executor::Executor;
+use embassy_time::Timer;
+use log::*;
+use static_cell::StaticCell;
+
+#[embassy_executor::task]
+async fn run() {
+    loop {
+        info!("tick");
+        Timer::after_secs(1).await;
+    }
+}
+
+static DONE: StaticCell<AtomicBool> = StaticCell::new();
+static EXECUTOR: StaticCell<Executor> = StaticCell::new();
+
+fn main() {
+    env_logger::builder()
+        .filter_level(log::LevelFilter::Debug)
+        .format_timestamp_nanos()
+        .init();
+
+    let done = DONE.init(AtomicBool::new(false));
+    let done_cb = || done.load(Ordering::Relaxed);
+
+    let server_thread = thread::spawn(move || {
+        let executor = EXECUTOR.init(Executor::new());
+        executor.run_until(
+            |spawner| {
+                spawner.spawn(run().unwrap());
+            },
+            done_cb,
+        );
+        info!("Executor finished");
+    });
+
+    thread::sleep(Duration::from_secs(5));
+
+    info!("Cancelling executor");
+    done.store(true, Ordering::Relaxed);
+
+    server_thread.join().unwrap();
+}
diff --git a/examples/stm32wb/Cargo.toml b/examples/stm32wb/Cargo.toml
index 83f7cb56b..496500f75 100644
--- a/examples/stm32wb/Cargo.toml
+++ b/examples/stm32wb/Cargo.toml
@@ -7,10 +7,10 @@ publish = false
 
 [dependencies]
 # Change stm32wb55rg to your chip name in both dependencies, if necessary.
-embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "stm32wb55rg", "time-driver-any", "memory-x", "exti", "low-power"]  }
+embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "stm32wb55rg", "time-driver-any", "memory-x", "exti", "low-power-pender"]  }
 embassy-stm32-wpan = { version = "0.1.0", path = "../../embassy-stm32-wpan", features = ["defmt", "stm32wb55rg"] }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
+embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.7.1", path = "../../embassy-net", features = ["defmt", "udp", "proto-ipv6", "medium-ieee802154", ], optional = true }
 
diff --git a/examples/stm32wb/src/bin/blinky.rs b/examples/stm32wb/src/bin/blinky.rs
index f37e8b1d8..e2737fcd5 100644
--- a/examples/stm32wb/src/bin/blinky.rs
+++ b/examples/stm32wb/src/bin/blinky.rs
@@ -7,7 +7,7 @@ use embassy_stm32::gpio::{Level, Output, Speed};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
-#[embassy_executor::main]
+#[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
diff --git a/examples/stm32wb/src/bin/button_exti.rs b/examples/stm32wb/src/bin/button_exti.rs
index 3c58eb556..37a207519 100644
--- a/examples/stm32wb/src/bin/button_exti.rs
+++ b/examples/stm32wb/src/bin/button_exti.rs
@@ -13,7 +13,7 @@ bind_interrupts!(
         EXTI4 => exti::InterruptHandler<interrupt::typelevel::EXTI4>;
 });
 
-#[embassy_executor::main]
+#[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
diff --git a/examples/stm32wb/src/bin/eddystone_beacon.rs b/examples/stm32wb/src/bin/eddystone_beacon.rs
index 413b1ac8f..a679e6fb1 100644
--- a/examples/stm32wb/src/bin/eddystone_beacon.rs
+++ b/examples/stm32wb/src/bin/eddystone_beacon.rs
@@ -26,7 +26,7 @@ bind_interrupts!(struct Irqs{
 
 const BLE_GAP_DEVICE_NAME_LENGTH: u8 = 7;
 
-#[embassy_executor::main]
+#[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
 async fn main(_spawner: Spawner) {
     /*
         How to make this work:
diff --git a/examples/stm32wb/src/bin/gatt_server.rs b/examples/stm32wb/src/bin/gatt_server.rs
index 3484f1844..10c7fd0ba 100644
--- a/examples/stm32wb/src/bin/gatt_server.rs
+++ b/examples/stm32wb/src/bin/gatt_server.rs
@@ -38,7 +38,7 @@ bind_interrupts!(struct Irqs{
 
 const BLE_GAP_DEVICE_NAME_LENGTH: u8 = 7;
 
-#[embassy_executor::main]
+#[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
 async fn main(spawner: Spawner) {
     /*
         How to make this work:
diff --git a/examples/stm32wb/src/bin/mac_ffd.rs b/examples/stm32wb/src/bin/mac_ffd.rs
index 4bab6ea9f..cd15968d2 100644
--- a/examples/stm32wb/src/bin/mac_ffd.rs
+++ b/examples/stm32wb/src/bin/mac_ffd.rs
@@ -23,7 +23,7 @@ async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
     memory_manager.run_queue().await;
 }
 
-#[embassy_executor::main]
+#[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
 async fn main(spawner: Spawner) {
     /*
         How to make this work:
diff --git a/examples/stm32wb/src/bin/mac_ffd_net.rs b/examples/stm32wb/src/bin/mac_ffd_net.rs
index b4789e3ee..244b35243 100644
--- a/examples/stm32wb/src/bin/mac_ffd_net.rs
+++ b/examples/stm32wb/src/bin/mac_ffd_net.rs
@@ -41,7 +41,7 @@ async fn run_net(mut runner: embassy_net::Runner<'static, Driver<'static>>) -> !
     runner.run().await
 }
 
-#[embassy_executor::main]
+#[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
 async fn main(spawner: Spawner) {
     /*
         How to make this work:
diff --git a/examples/stm32wb/src/bin/mac_rfd.rs b/examples/stm32wb/src/bin/mac_rfd.rs
index dae3c5200..f3e65c66b 100644
--- a/examples/stm32wb/src/bin/mac_rfd.rs
+++ b/examples/stm32wb/src/bin/mac_rfd.rs
@@ -25,7 +25,7 @@ async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
     memory_manager.run_queue().await;
 }
 
-#[embassy_executor::main]
+#[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
 async fn main(spawner: Spawner) {
     /*
         How to make this work:
diff --git a/examples/stm32wb/src/bin/tl_mbox.rs b/examples/stm32wb/src/bin/tl_mbox.rs
index 0902e28e8..adb6eff7b 100644
--- a/examples/stm32wb/src/bin/tl_mbox.rs
+++ b/examples/stm32wb/src/bin/tl_mbox.rs
@@ -15,7 +15,7 @@ bind_interrupts!(struct Irqs{
     IPCC_C1_TX => TransmitInterruptHandler;
 });
 
-#[embassy_executor::main]
+#[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
 async fn main(_spawner: Spawner) {
     /*
         How to make this work:
diff --git a/examples/stm32wb/src/bin/tl_mbox_ble.rs b/examples/stm32wb/src/bin/tl_mbox_ble.rs
index 763dc32cd..376b808de 100644
--- a/examples/stm32wb/src/bin/tl_mbox_ble.rs
+++ b/examples/stm32wb/src/bin/tl_mbox_ble.rs
@@ -20,7 +20,7 @@ async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
     memory_manager.run_queue().await;
 }
 
-#[embassy_executor::main]
+#[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
 async fn main(spawner: Spawner) {
     /*
         How to make this work:
diff --git a/examples/stm32wb/src/bin/tl_mbox_mac.rs b/examples/stm32wb/src/bin/tl_mbox_mac.rs
index 235a48241..697e061c1 100644
--- a/examples/stm32wb/src/bin/tl_mbox_mac.rs
+++ b/examples/stm32wb/src/bin/tl_mbox_mac.rs
@@ -20,7 +20,7 @@ async fn run_mm_queue(mut memory_manager: mm::MemoryManager<'static>) {
     memory_manager.run_queue().await;
 }
 
-#[embassy_executor::main]
+#[embassy_executor::main(executor = "embassy_stm32::Executor", entry = "cortex_m_rt::entry")]
 async fn main(spawner: Spawner) {
     /*
         How to make this work:
diff --git a/examples/stm32wba/src/bin/mac_ffd.rs b/examples/stm32wba/src/bin/mac_ffd.rs
index b15fb3452..329a73c6d 100644
--- a/examples/stm32wba/src/bin/mac_ffd.rs
+++ b/examples/stm32wba/src/bin/mac_ffd.rs
@@ -5,7 +5,7 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::Config;
 use embassy_stm32::rcc::{Sysclk, mux};
-use embassy_stm32_wpan::bindings::mac::ST_MAC_callbacks_t;
+use embassy_stm32_wpan::bindings::mac::{ST_MAC_callbacks_t, ST_MAC_init};
 use {defmt_rtt as _, panic_probe as _};
 
 static _MAC_CALLBACKS: ST_MAC_callbacks_t = ST_MAC_callbacks_t {
@@ -50,9 +50,9 @@ async fn main(_spawner: Spawner) {
     let _p = embassy_stm32::init(config);
     info!("Hello World!");
 
-    //    let status = unsafe { ST_MAC_init(&_MAC_CALLBACKS as *const _ as *mut _) };
-    //
-    //    info!("mac init: {}", status);
+    let status = unsafe { ST_MAC_init(&_MAC_CALLBACKS as *const _ as *mut _) };
+
+    info!("mac init: {}", status);
 
     cortex_m::asm::bkpt();
 }
diff --git a/examples/stm32wle5/src/bin/adc.rs b/examples/stm32wle5/src/bin/adc.rs
index ea91fb063..8cc84ccdf 100644
--- a/examples/stm32wle5/src/bin/adc.rs
+++ b/examples/stm32wle5/src/bin/adc.rs
@@ -34,24 +34,6 @@ async fn async_main(_spawner: Spawner) {
     // Initialize STM32WL peripherals (use default config like wio-e5-async example)
     let p = embassy_stm32::init(config);
 
-    // start with all GPIOs as analog to reduce power consumption
-    for r in [
-        embassy_stm32::pac::GPIOA,
-        embassy_stm32::pac::GPIOB,
-        embassy_stm32::pac::GPIOC,
-        embassy_stm32::pac::GPIOH,
-    ] {
-        r.moder().modify(|w| {
-            for i in 0..16 {
-                // don't reset these if probe-rs should stay connected!
-                #[cfg(feature = "defmt-rtt")]
-                if config.enable_debug_during_sleep && r == embassy_stm32::pac::GPIOA && [13, 14].contains(&i) {
-                    continue;
-                }
-                w.set_moder(i, embassy_stm32::pac::gpio::vals::Moder::ANALOG);
-            }
-        });
-    }
     #[cfg(feature = "defmt-serial")]
     {
         use embassy_stm32::mode::Blocking;
diff --git a/examples/stm32wle5/src/bin/blinky.rs b/examples/stm32wle5/src/bin/blinky.rs
index 9f0c04672..3b7eb7761 100644
--- a/examples/stm32wle5/src/bin/blinky.rs
+++ b/examples/stm32wle5/src/bin/blinky.rs
@@ -32,24 +32,6 @@ async fn async_main(_spawner: Spawner) {
     // Initialize STM32WL peripherals (use default config like wio-e5-async example)
     let p = embassy_stm32::init(config);
 
-    // start with all GPIOs as analog to reduce power consumption
-    for r in [
-        embassy_stm32::pac::GPIOA,
-        embassy_stm32::pac::GPIOB,
-        embassy_stm32::pac::GPIOC,
-        embassy_stm32::pac::GPIOH,
-    ] {
-        r.moder().modify(|w| {
-            for i in 0..16 {
-                // don't reset these if probe-rs should stay connected!
-                #[cfg(feature = "defmt-rtt")]
-                if config.enable_debug_during_sleep && r == embassy_stm32::pac::GPIOA && [13, 14].contains(&i) {
-                    continue;
-                }
-                w.set_moder(i, embassy_stm32::pac::gpio::vals::Moder::ANALOG);
-            }
-        });
-    }
     #[cfg(feature = "defmt-serial")]
     {
         use embassy_stm32::mode::Blocking;
@@ -67,10 +49,10 @@ async fn async_main(_spawner: Spawner) {
     loop {
         info!("low");
         led.set_low();
-        Timer::after_millis(500).await;
+        Timer::after_millis(15000).await;
 
         info!("high");
         led.set_high();
-        Timer::after_millis(500).await;
+        Timer::after_millis(15000).await;
     }
 }
diff --git a/examples/stm32wle5/src/bin/button_exti.rs b/examples/stm32wle5/src/bin/button_exti.rs
index f248b6147..9ffc39948 100644
--- a/examples/stm32wle5/src/bin/button_exti.rs
+++ b/examples/stm32wle5/src/bin/button_exti.rs
@@ -39,24 +39,6 @@ async fn async_main(_spawner: Spawner) {
     // Initialize STM32WL peripherals (use default config like wio-e5-async example)
     let p = embassy_stm32::init(config);
 
-    // start with all GPIOs as analog to reduce power consumption
-    for r in [
-        embassy_stm32::pac::GPIOA,
-        embassy_stm32::pac::GPIOB,
-        embassy_stm32::pac::GPIOC,
-        embassy_stm32::pac::GPIOH,
-    ] {
-        r.moder().modify(|w| {
-            for i in 0..16 {
-                // don't reset these if probe-rs should stay connected!
-                #[cfg(feature = "defmt-rtt")]
-                if config.enable_debug_during_sleep && r == embassy_stm32::pac::GPIOA && [13, 14].contains(&i) {
-                    continue;
-                }
-                w.set_moder(i, embassy_stm32::pac::gpio::vals::Moder::ANALOG);
-            }
-        });
-    }
     #[cfg(feature = "defmt-serial")]
     {
         use embassy_stm32::mode::Blocking;
diff --git a/examples/stm32wle5/src/bin/i2c.rs b/examples/stm32wle5/src/bin/i2c.rs
index 68c17a672..8e7a6e2d8 100644
--- a/examples/stm32wle5/src/bin/i2c.rs
+++ b/examples/stm32wle5/src/bin/i2c.rs
@@ -40,24 +40,6 @@ async fn async_main(_spawner: Spawner) {
     // Initialize STM32WL peripherals (use default config like wio-e5-async example)
     let p = embassy_stm32::init(config);
 
-    // start with all GPIOs as analog to reduce power consumption
-    for r in [
-        embassy_stm32::pac::GPIOA,
-        embassy_stm32::pac::GPIOB,
-        embassy_stm32::pac::GPIOC,
-        embassy_stm32::pac::GPIOH,
-    ] {
-        r.moder().modify(|w| {
-            for i in 0..16 {
-                // don't reset these if probe-rs should stay connected!
-                #[cfg(feature = "defmt-rtt")]
-                if config.enable_debug_during_sleep && r == embassy_stm32::pac::GPIOA && [13, 14].contains(&i) {
-                    continue;
-                }
-                w.set_moder(i, embassy_stm32::pac::gpio::vals::Moder::ANALOG);
-            }
-        });
-    }
     #[cfg(feature = "defmt-serial")]
     {
         use embassy_stm32::mode::Blocking;
@@ -79,7 +61,7 @@ async fn async_main(_spawner: Spawner) {
     let mut i2c = I2c::new(p.I2C2, p.PB15, p.PA15, IrqsI2C, p.DMA1_CH6, p.DMA1_CH7, {
         let mut config = i2c::Config::default();
         config.frequency = Hertz::khz(100);
-        config.timeout = Duration::from_millis(500);
+        config.timeout = Duration::from_millis(1000);
         config
     });
 
diff --git a/rust-toolchain-nightly.toml b/rust-toolchain-nightly.toml
index dde431bba..2a46473b7 100644
--- a/rust-toolchain-nightly.toml
+++ b/rust-toolchain-nightly.toml
@@ -1,5 +1,5 @@
 [toolchain]
-channel = "nightly-2025-09-26"
+channel = "nightly-2025-12-11"
 components = [ "rust-src", "rustfmt", "llvm-tools", "miri" ]
 targets = [
     "thumbv7em-none-eabi",
diff --git a/rust-toolchain.toml b/rust-toolchain.toml
index 5d925c934..1f47bee1e 100644
--- a/rust-toolchain.toml
+++ b/rust-toolchain.toml
@@ -1,5 +1,5 @@
 [toolchain]
-channel = "1.90"
+channel = "1.92"
 components = [ "rust-src", "rustfmt", "llvm-tools" ]
 targets = [
     "thumbv7em-none-eabi",
diff --git a/tests/nrf/Cargo.toml b/tests/nrf/Cargo.toml
index 3a9b86cef..50f059b34 100644
--- a/tests/nrf/Cargo.toml
+++ b/tests/nrf/Cargo.toml
@@ -12,7 +12,7 @@ embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt", ] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt",  "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["defmt",  "time-driver-rtc1", "gpiote", "unstable-pac"] }
+embassy-nrf = { version = "0.9.0", path = "../../embassy-nrf", features = ["defmt",  "time-driver-rtc1", "gpiote", "unstable-pac"] }
 embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
 embassy-net = { version = "0.7.1", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", ] }
 embassy-net-esp-hosted = { version = "0.2.1", path = "../../embassy-net-esp-hosted", features = ["defmt"] }