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* Update STM32 RCC U5 to support P and Q dividersTyler Gilbert2024-01-031-0/+2
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* ci: use beta, add secondary nightly ci.Dario Nieuwenhuis2023-12-213-3/+0
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* stm32/rcc: consistent casing and naming for PLL enums.Dario Nieuwenhuis2023-11-131-1/+1
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* usb: remove msos-descriptor feature.Dario Nieuwenhuis2023-11-081-0/+1
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* stm32/rcc: add shared code for hsi48 with crs support.Dario Nieuwenhuis2023-11-051-2/+1
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* stm32: rename HSI16 -> HSIDario Nieuwenhuis2023-10-221-2/+2
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* time: Update examples, tests, and other code to use new Timer::after_x ↵Adam Greig2023-10-151-3/+3
| | | | convenience methods
* stm32/rcc: use PLL enums from PAC.Dario Nieuwenhuis2023-10-091-3/+3
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* stm32: u5: implement >55 MHz clock speedsWill Glynn2023-10-051-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows STM32U5 devices to operate at 160 MHz. On STM32U5, MSIS can run at 48 MHz and HSE can reach 50 MHz. Faster clocks require using PLL1's R output, though PLL1 can serve other functions besides using the R output for the system clock. This commit extracts a public `PllConfig` struct, primarily to place associated constructors on that type, but also with an eye towards enabling the P and Q outputs in a later commit. STM32U5 PLLs have various frequency requirements on each stage: after the `m` prescaler, after the `n` multiplier, and after the `r` divider. This commit implements the associated checks as assertions. This commit fixes clock calculation and PLL register configuration errors in PLL initialization. STM32U5 has a PWR peripheral which can be configured to push Vcore into different voltage ranges. System clocks exceeding 55 MHz require range 2, and system clocks exceeding 110 MHz require range 1. This commit adds `voltage_range` to `Config` and configures PWR as directed. The voltage range implies different performance limits on various clock signals, including inside a PLL. This commit implements voltage range <-> frequency range checks as assertions, and extracts the otherwise-repeated MSIS, HSI16, and HSE initialization into private methods on `Config`. STM32U5 frequencies above 55 MHz require using the PWR EPOD booster. The EPOD booster requires configuring a second `m` term for PLL1, `mboost`, such that it falls in a particular range. (Recall that >50 MHz cannot be reached without PLL1, so there is no scenario where EPOD is needed but PLL1 is not.) This commit configures and enables the EPOD booster automatically as required.
* stm32/otg: add VBUS detection.Dario Nieuwenhuis2023-06-271-1/+3
| | | | Fixes #1442.
* stm32: move to bind_interruptsxoviat2023-05-241-3/+6
| | | | disable lora functionality for now
* Fix some typosDirk Stolle2023-05-081-1/+1
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* usb: unify ControlHandler+DeviceStateHandler, route all control requests to ↵Dario Nieuwenhuis2023-02-081-1/+0
| | | | | | | | all handlers. - Allows classes to handle vendor requests. - Allows classes to use a single handler for multiple interfaces. - Allows classes to access the other events (previously only `reset` was available).
* stm32 otg: add examples.chemicstry2023-01-111-0/+108
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* Split embassy-time from embassy-executor.Dario Nieuwenhuis2022-08-181-2/+2
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* Remove HAL initialization from #[embassy::main] macro.Dario Nieuwenhuis2022-08-171-2/+2
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* Split embassy crate into embassy-executor, embassy-util.Dario Nieuwenhuis2022-07-291-3/+3
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* Run rustfmt.Dario Nieuwenhuis2022-06-122-7/+2
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* stm32: add stm32u5 GPDMA, SPIv4 support, add HIL tests.Dario Nieuwenhuis2022-04-271-0/+29
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* Use embassy/defmt-timestamp-uptime in all examples.Dario Nieuwenhuis2022-04-021-3/+3
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* Update to defmt 3.0ish.Bob McWhirter2021-11-151-1/+3
| | | | Lots of gitrevs deps.
* Omg. More formatting.Bob McWhirter2021-11-021-1/+0
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* Need to include a bit of embassy for the NVIC.Bob McWhirter2021-11-021-0/+3
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* Remove unused imports.Bob McWhirter2021-11-021-14/+0
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* Formatting, per usual.Bob McWhirter2021-11-021-5/+5
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* Add STM32U5 example.Bob McWhirter2021-11-021-0/+28