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* HIL test for STM32 FDCAN support.Corey Schuhen2024-01-311-0/+243
* tests/stm32: fix h7 wrong smps config.Dario Nieuwenhuis2024-01-201-0/+4
* fix changed import pathsUlf Lilleengen2024-01-121-5/+3
* Change GPIO inherent methods back to `&self`.Dario Nieuwenhuis2024-01-101-6/+6
* ci: use beta, add secondary nightly ci.Dario Nieuwenhuis2023-12-212-2/+0
* chore: replace make_static! macro usage with non-macro versionUlf Lilleengen2023-12-212-7/+11
* Update embedded-hal to 1.0.0-rc.3Dario Nieuwenhuis2023-12-141-6/+6
* tests/stm32: add L1 DAC/ADC test.Dario Nieuwenhuis2023-12-083-6/+94
* tests: use executor task arena instead of TAIT.Dario Nieuwenhuis2023-11-2714-14/+0
* stm32/test: add stm32f446 (board not in HIL rig yet)Dario Nieuwenhuis2023-11-274-25/+54
* STM32 DAC: Rework DAC driver, support all families.Adam Greig2023-11-251-6/+4
* stm32/rcc: unify f2 into f4/f7.Dario Nieuwenhuis2023-11-131-10/+11
* stm32/rcc: fix pll enum naming on f4, f7.Dario Nieuwenhuis2023-11-131-2/+2
* stm32/rcc: unify l0l1 and l4l5.Dario Nieuwenhuis2023-11-131-2/+2
* stm32/rcc: consistent casing and naming for PLL enums.Dario Nieuwenhuis2023-11-131-15/+15
* stm32/rcc: add shared code for hsi48 with crs support.Dario Nieuwenhuis2023-11-051-3/+3
* stm32/rcc: switch to modern api for l0, l1.Dario Nieuwenhuis2023-11-051-12/+14
* stm32/low-power: refactor refcountxoviat2023-10-251-4/+4
* Merge pull request #2106 from xoviat/fix-stop-2xoviat2023-10-231-1/+3
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| * stm32: fix low-power testxoviat2023-10-231-1/+3
* | stm32/rcc: misc cleanups.Dario Nieuwenhuis2023-10-231-8/+10
* | stm32/rcc: merge wb into l4/l5.Dario Nieuwenhuis2023-10-231-0/+6
* | stm32/rcc: merge wl into l4/l5.Dario Nieuwenhuis2023-10-231-3/+12
* | stm32/tests: add stm32wba52cg, stm32u5a9zjDario Nieuwenhuis2023-10-221-1/+34
* | stm32: rename HSI16 -> HSIDario Nieuwenhuis2023-10-221-4/+4
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* Merge pull request #2097 from embassy-rs/rcc-no-spaghettiDario Nieuwenhuis2023-10-214-6/+54
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| * stm32/tests: add stm32h753zi, stm32h7a3zi.Dario Nieuwenhuis2023-10-214-6/+54
* | stm32: update metapacxoviat2023-10-201-8/+1
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* stm32/rcc: refactor and unify f4 into f7.Dario Nieuwenhuis2023-10-181-5/+17
* stm32/rcc: refactor f7.Dario Nieuwenhuis2023-10-181-1/+17
* stm32: update metapacxoviat2023-10-171-3/+10
* stm32/tests: add stm32wl hil.Dario Nieuwenhuis2023-10-171-0/+17
* stm32: update metapacxoviat2023-10-161-1/+1
* stm32/rng: add test.Dario Nieuwenhuis2023-10-161-0/+50
* stm32/rcc: unify L4 and L5.Dario Nieuwenhuis2023-10-161-7/+10
* stm32/rcc: add better support for L4/L4+ differences.Dario Nieuwenhuis2023-10-161-1/+1
* stm32/rcc: port L4 to the "flattened" API like h5/h7.Dario Nieuwenhuis2023-10-151-9/+11
* time: Update examples, tests, and other code to use new Timer::after_x conven...Adam Greig2023-10-155-14/+14
* stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.Dario Nieuwenhuis2023-10-112-19/+4
* stm32/rcc: unify L0 and L1.Dario Nieuwenhuis2023-10-111-1/+1
* stm32/rcc: use more PLL etc enums from PAC.Dario Nieuwenhuis2023-10-111-4/+4
* Patch tests & examplesGabriel Górski2023-10-091-2/+1
* stm32/rcc: use PLL enums from PAC.Dario Nieuwenhuis2023-10-091-21/+21
* h7: enable rtc testMatt Ickstadt2023-10-061-4/+13
* Remove a few ultra-verbose logs.Dario Nieuwenhuis2023-10-031-1/+1
* stm32/hil: add f2, f3, f7, l49Dario Nieuwenhuis2023-10-032-3/+78
* tests/stm32: use default clock configxoviat2023-10-021-1/+4
* tests/stm32: add eth test.Dario Nieuwenhuis2023-10-022-0/+148
* tests/stm32: add L0, L1, L4, L4+, L5Dario Nieuwenhuis2023-09-261-1/+90
* stm32/usart: enable fifo mode on usartv4.Dario Nieuwenhuis2023-09-261-16/+26