From 00db482c2b701b6e8f7013ba63d6e1efe3b5c62d Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sat, 27 Sep 2025 19:20:11 +0200 Subject: nrf/twis: erase instance generics --- embassy-nrf/src/twis.rs | 65 ++++++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/embassy-nrf/src/twis.rs b/embassy-nrf/src/twis.rs index c77d0f048..dd4978b3e 100644 --- a/embassy-nrf/src/twis.rs +++ b/embassy-nrf/src/twis.rs @@ -140,14 +140,16 @@ impl interrupt::typelevel::Handler for InterruptHandl } /// TWIS driver. -pub struct Twis<'d, T: Instance> { - _p: Peri<'d, T>, +pub struct Twis<'d> { + r: pac::twis::Twis, + state: &'static State, + _p: PhantomData<&'d ()>, } -impl<'d, T: Instance> Twis<'d, T> { +impl<'d> Twis<'d> { /// Create a new TWIS driver. - pub fn new( - twis: Peri<'d, T>, + pub fn new( + _twis: Peri<'d, T>, _irq: impl interrupt::typelevel::Binding> + 'd, sda: Peri<'d, impl GpioPin>, scl: Peri<'d, impl GpioPin>, @@ -206,7 +208,11 @@ impl<'d, T: Instance> Twis<'d, T> { T::Interrupt::unpend(); unsafe { T::Interrupt::enable() }; - Self { _p: twis } + Self { + r: T::regs(), + state: T::state(), + _p: PhantomData, + } } /// Set TX buffer, checking that it is in RAM and has suitable length. @@ -217,7 +223,7 @@ impl<'d, T: Instance> Twis<'d, T> { return Err(Error::TxBufferTooLong); } - let r = T::regs(); + let r = self.r; // We're giving the register a pointer to the stack. Since we're // waiting for the I2C transaction to end before this stack pointer @@ -244,7 +250,7 @@ impl<'d, T: Instance> Twis<'d, T> { return Err(Error::RxBufferTooLong); } - let r = T::regs(); + let r = self.r; // We're giving the register a pointer to the stack. Since we're // waiting for the I2C transaction to end before this stack pointer @@ -266,7 +272,7 @@ impl<'d, T: Instance> Twis<'d, T> { } fn clear_errorsrc(&mut self) { - let r = T::regs(); + let r = self.r; r.errorsrc().write(|w| { w.set_overflow(true); w.set_overread(true); @@ -276,18 +282,18 @@ impl<'d, T: Instance> Twis<'d, T> { /// Returns matched address for latest command. pub fn address_match(&self) -> u8 { - let r = T::regs(); + let r = self.r; r.address(r.match_().read().0 as usize).read().address() } /// Returns the index of the address matched in the latest command. pub fn address_match_index(&self) -> usize { - T::regs().match_().read().0 as _ + self.r.match_().read().0 as _ } /// Wait for read, write, stop or error fn blocking_listen_wait(&mut self) -> Result { - let r = T::regs(); + let r = self.r; loop { if r.events_error().read() != 0 { r.events_error().write_value(0); @@ -312,7 +318,7 @@ impl<'d, T: Instance> Twis<'d, T> { /// Wait for stop, repeated start or error fn blocking_listen_wait_end(&mut self, status: Status) -> Result { - let r = T::regs(); + let r = self.r; loop { // stop if an error occurred if r.events_error().read() != 0 { @@ -338,7 +344,7 @@ impl<'d, T: Instance> Twis<'d, T> { /// Wait for stop or error fn blocking_wait(&mut self) -> Result { - let r = T::regs(); + let r = self.r; loop { // stop if an error occurred if r.events_error().read() != 0 { @@ -363,7 +369,7 @@ impl<'d, T: Instance> Twis<'d, T> { /// Wait for stop or error with timeout #[cfg(feature = "time")] fn blocking_wait_timeout(&mut self, timeout: Duration) -> Result { - let r = T::regs(); + let r = self.r; let deadline = Instant::now() + timeout; loop { // stop if an error occurred @@ -392,7 +398,7 @@ impl<'d, T: Instance> Twis<'d, T> { /// Wait for read, write, stop or error with timeout #[cfg(feature = "time")] fn blocking_listen_wait_timeout(&mut self, timeout: Duration) -> Result { - let r = T::regs(); + let r = self.r; let deadline = Instant::now() + timeout; loop { if r.events_error().read() != 0 { @@ -423,7 +429,7 @@ impl<'d, T: Instance> Twis<'d, T> { /// Wait for stop, repeated start or error with timeout #[cfg(feature = "time")] fn blocking_listen_wait_end_timeout(&mut self, status: Status, timeout: Duration) -> Result { - let r = T::regs(); + let r = self.r; let deadline = Instant::now() + timeout; loop { // stop if an error occurred @@ -453,10 +459,9 @@ impl<'d, T: Instance> Twis<'d, T> { /// Wait for stop or error fn async_wait(&mut self) -> impl Future> { + let r = self.r; + let s = self.state; poll_fn(move |cx| { - let r = T::regs(); - let s = T::state(); - s.waker.register(cx.waker()); // stop if an error occurred @@ -483,10 +488,9 @@ impl<'d, T: Instance> Twis<'d, T> { /// Wait for read or write fn async_listen_wait(&mut self) -> impl Future> { + let r = self.r; + let s = self.state; poll_fn(move |cx| { - let r = T::regs(); - let s = T::state(); - s.waker.register(cx.waker()); // stop if an error occurred @@ -510,10 +514,9 @@ impl<'d, T: Instance> Twis<'d, T> { /// Wait for stop, repeated start or error fn async_listen_wait_end(&mut self, status: Status) -> impl Future> { + let r = self.r; + let s = self.state; poll_fn(move |cx| { - let r = T::regs(); - let s = T::state(); - s.waker.register(cx.waker()); // stop if an error occurred @@ -540,7 +543,7 @@ impl<'d, T: Instance> Twis<'d, T> { } fn setup_respond_from_ram(&mut self, buffer: &[u8], inten: bool) -> Result<(), Error> { - let r = T::regs(); + let r = self.r; compiler_fence(SeqCst); @@ -584,7 +587,7 @@ impl<'d, T: Instance> Twis<'d, T> { } fn setup_listen(&mut self, buffer: &mut [u8], inten: bool) -> Result<(), Error> { - let r = T::regs(); + let r = self.r; compiler_fence(SeqCst); // Set up the DMA read. @@ -620,7 +623,7 @@ impl<'d, T: Instance> Twis<'d, T> { } fn setup_listen_end(&mut self, inten: bool) -> Result<(), Error> { - let r = T::regs(); + let r = self.r; compiler_fence(SeqCst); // Clear events @@ -753,14 +756,14 @@ impl<'d, T: Instance> Twis<'d, T> { } } -impl<'a, T: Instance> Drop for Twis<'a, T> { +impl<'a> Drop for Twis<'a> { fn drop(&mut self) { trace!("twis drop"); // TODO: check for abort // disable! - let r = T::regs(); + let r = self.r; r.enable().write(|w| w.set_enable(vals::Enable::DISABLED)); gpio::deconfigure_pin(r.psel().sda().read()); -- cgit