From 03ecc91d552328f625c3ed13088291272123784f Mon Sep 17 00:00:00 2001 From: xoviat Date: Fri, 19 Mar 2021 15:26:20 -0500 Subject: stm32: consolidate functionality into new pkg --- Cargo.toml | 1 + embassy-stm32/Cargo.toml | 46 ++ embassy-stm32/src/fmt.rs | 114 ++++ embassy-stm32/src/interrupt.rs | 1127 ++++++++++++++++++++++++++++++++++++++ embassy-stm32/src/lib.rs | 35 ++ embassy-stm32f4/Cargo.toml | 36 +- embassy-stm32f4/src/fmt.rs | 114 ---- embassy-stm32f4/src/interrupt.rs | 1025 ---------------------------------- embassy-stm32f4/src/lib.rs | 7 +- embassy-stm32l0/Cargo.toml | 7 +- embassy-stm32l0/src/fmt.rs | 119 ---- embassy-stm32l0/src/interrupt.rs | 162 ------ embassy-stm32l0/src/lib.rs | 7 +- 13 files changed, 1347 insertions(+), 1453 deletions(-) create mode 100644 embassy-stm32/Cargo.toml create mode 100644 embassy-stm32/src/fmt.rs create mode 100644 embassy-stm32/src/interrupt.rs create mode 100644 embassy-stm32/src/lib.rs delete mode 100644 embassy-stm32f4/src/fmt.rs delete mode 100644 embassy-stm32f4/src/interrupt.rs delete mode 100644 embassy-stm32l0/src/fmt.rs delete mode 100644 embassy-stm32l0/src/interrupt.rs diff --git a/Cargo.toml b/Cargo.toml index 31fe26476..d9fbeaf45 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -4,6 +4,7 @@ members = [ "embassy", "embassy-traits", "embassy-nrf", + "embassy-stm32", "embassy-stm32f4", "embassy-stm32l0", "embassy-nrf-examples", diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml new file mode 100644 index 000000000..6701ff8f3 --- /dev/null +++ b/embassy-stm32/Cargo.toml @@ -0,0 +1,46 @@ +[package] +name = "embassy-stm32" +version = "0.1.0" +authors = ["Dario Nieuwenhuis "] +edition = "2018" + +[features] +defmt-trace = [ ] +defmt-debug = [ ] +defmt-info = [ ] +defmt-warn = [ ] +defmt-error = [ ] + +stm32f401 = ["stm32f4xx-hal/stm32f401"] +stm32f405 = ["stm32f4xx-hal/stm32f405"] +stm32f407 = ["stm32f4xx-hal/stm32f407"] +stm32f410 = ["stm32f4xx-hal/stm32f410"] +stm32f411 = ["stm32f4xx-hal/stm32f411"] +stm32f412 = ["stm32f4xx-hal/stm32f412"] +stm32f413 = ["stm32f4xx-hal/stm32f413"] +stm32f415 = ["stm32f4xx-hal/stm32f405"] +stm32f417 = ["stm32f4xx-hal/stm32f407"] +stm32f423 = ["stm32f4xx-hal/stm32f413"] +stm32f427 = ["stm32f4xx-hal/stm32f427"] +stm32f429 = ["stm32f4xx-hal/stm32f429"] +stm32f437 = ["stm32f4xx-hal/stm32f427"] +stm32f439 = ["stm32f4xx-hal/stm32f429"] +stm32f446 = ["stm32f4xx-hal/stm32f446"] +stm32f469 = ["stm32f4xx-hal/stm32f469"] +stm32f479 = ["stm32f4xx-hal/stm32f469"] + +stm32l0x1 = ["stm32l0xx-hal/stm32l0x1"] +stm32l0x2 = ["stm32l0xx-hal/stm32l0x2"] +stm32l0x3 = ["stm32l0xx-hal/stm32l0x3"] + +[dependencies] +embassy = { version = "0.1.0", path = "../embassy" } + +defmt = { version = "0.2.0", optional = true } +log = { version = "0.4.11", optional = true } +cortex-m-rt = "0.6.13" +cortex-m = "0.7.1" +embedded-hal = { version = "0.2.4" } +embedded-dma = { version = "0.1.2" } +stm32f4xx-hal = { version = "0.8.3", features = ["rt", "can"], git = "https://github.com/stm32-rs/stm32f4xx-hal.git", optional = true } +stm32l0xx-hal = { version = "0.7.0", features = ["rt"], git = "https://github.com/stm32-rs/stm32l0xx-hal.git", optional = true } \ No newline at end of file diff --git a/embassy-stm32/src/fmt.rs b/embassy-stm32/src/fmt.rs new file mode 100644 index 000000000..160642ccd --- /dev/null +++ b/embassy-stm32/src/fmt.rs @@ -0,0 +1,114 @@ +#![macro_use] +#![allow(clippy::module_inception)] +#![allow(unused)] + +#[cfg(all(feature = "defmt", feature = "log"))] +compile_error!("You may not enable both `defmt` and `log` features."); + +pub use fmt::*; + +#[cfg(feature = "defmt")] +mod fmt { + pub use defmt::{ + assert, assert_eq, assert_ne, debug, debug_assert, debug_assert_eq, debug_assert_ne, error, + info, panic, todo, trace, unreachable, unwrap, warn, + }; +} + +#[cfg(feature = "log")] +mod fmt { + pub use core::{ + assert, assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, panic, todo, + unreachable, + }; + pub use log::{debug, error, info, trace, warn}; +} + +#[cfg(not(any(feature = "defmt", feature = "log")))] +mod fmt { + #![macro_use] + + pub use core::{ + assert, assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, panic, todo, + unreachable, + }; + + macro_rules! trace { + ($($msg:expr),+ $(,)?) => { + () + }; + } + + macro_rules! debug { + ($($msg:expr),+ $(,)?) => { + () + }; + } + + macro_rules! info { + ($($msg:expr),+ $(,)?) => { + () + }; + } + + macro_rules! warn { + ($($msg:expr),+ $(,)?) => { + () + }; + } + + macro_rules! error { + ($($msg:expr),+ $(,)?) => { + () + }; + } +} + +#[cfg(not(feature = "defmt"))] +macro_rules! unwrap { + ($arg:expr) => { + match $crate::fmt::Try::into_result($arg) { + ::core::result::Result::Ok(t) => t, + ::core::result::Result::Err(e) => { + ::core::panic!("unwrap of `{}` failed: {:?}", ::core::stringify!($arg), e); + } + } + }; + ($arg:expr, $($msg:expr),+ $(,)? ) => { + match $crate::fmt::Try::into_result($arg) { + ::core::result::Result::Ok(t) => t, + ::core::result::Result::Err(e) => { + ::core::panic!("unwrap of `{}` failed: {}: {:?}", ::core::stringify!($arg), ::core::format_args!($($msg,)*), e); + } + } + } +} + +#[derive(Debug, Copy, Clone, Eq, PartialEq)] +pub struct NoneError; + +pub trait Try { + type Ok; + type Error; + fn into_result(self) -> Result; +} + +impl Try for Option { + type Ok = T; + type Error = NoneError; + + #[inline] + fn into_result(self) -> Result { + self.ok_or(NoneError) + } +} + +impl Try for Result { + type Ok = T; + type Error = E; + + #[inline] + fn into_result(self) -> Self { + self + } +} diff --git a/embassy-stm32/src/interrupt.rs b/embassy-stm32/src/interrupt.rs new file mode 100644 index 000000000..5ad7ef8ef --- /dev/null +++ b/embassy-stm32/src/interrupt.rs @@ -0,0 +1,1127 @@ +//! Interrupt management +//! +//! This module implements an API for managing interrupts compatible with +//! nrf_softdevice::interrupt. Intended for switching between the two at compile-time. + +use core::sync::atomic::{compiler_fence, Ordering}; + +use crate::pac::NVIC_PRIO_BITS; + +// Re-exports +pub use cortex_m::interrupt::{CriticalSection, Mutex}; +pub use embassy::interrupt::{declare, take, Interrupt}; + +#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[repr(u8)] +pub enum Priority { + Level0 = 0, + Level1 = 1, + Level2 = 2, + Level3 = 3, + Level4 = 4, + Level5 = 5, + Level6 = 6, + Level7 = 7, + Level8 = 8, + Level9 = 9, + Level10 = 10, + Level11 = 11, + Level12 = 12, + Level13 = 13, + Level14 = 14, + Level15 = 15, +} + +impl From for Priority { + fn from(priority: u8) -> Self { + match priority >> (8 - NVIC_PRIO_BITS) { + 0 => Self::Level0, + 1 => Self::Level1, + 2 => Self::Level2, + 3 => Self::Level3, + 4 => Self::Level4, + 5 => Self::Level5, + 6 => Self::Level6, + 7 => Self::Level7, + 8 => Self::Level8, + 9 => Self::Level9, + 10 => Self::Level10, + 11 => Self::Level11, + 12 => Self::Level12, + 13 => Self::Level13, + 14 => Self::Level14, + 15 => Self::Level15, + _ => unreachable!(), + } + } +} + +impl From for u8 { + fn from(p: Priority) -> Self { + (p as u8) << (8 - NVIC_PRIO_BITS) + } +} + +#[inline] +pub fn free(f: F) -> R +where + F: FnOnce(&CriticalSection) -> R, +{ + unsafe { + // TODO: assert that we're in privileged level + // Needed because disabling irqs in non-privileged level is a noop, which would break safety. + + let primask: u32; + asm!("mrs {}, PRIMASK", out(reg) primask); + + asm!("cpsid i"); + + // Prevent compiler from reordering operations inside/outside the critical section. + compiler_fence(Ordering::SeqCst); + + let r = f(&CriticalSection::new()); + + compiler_fence(Ordering::SeqCst); + + if primask & 1 == 0 { + asm!("cpsie i"); + } + + r + } +} + +#[cfg(feature = "stm32f401")] +mod irqs { + use super::*; + declare!(PVD); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + declare!(FLASH); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_UP_TIM10); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(I2C1_EV); + declare!(I2C1_ER); + declare!(I2C2_EV); + declare!(I2C2_ER); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(EXTI15_10); + declare!(RTC_ALARM); + declare!(OTG_FS_WKUP); + declare!(DMA1_STREAM7); + declare!(SDIO); + declare!(TIM5); + declare!(SPI3); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(OTG_FS); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(I2C3_EV); + declare!(I2C3_ER); + declare!(FPU); + declare!(SPI4); +} + +#[cfg(feature = "stm32f405")] +mod irqs { + use super::*; + declare!(WWDG); + declare!(PVD); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + // declare!(FLASH); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(CAN1_TX); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_UP_TIM10); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(I2C1_EV); + declare!(I2C1_ER); + declare!(I2C2_EV); + declare!(I2C2_ER); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(EXTI15_10); + declare!(RTC_ALARM); + declare!(OTG_FS_WKUP); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_UP_TIM13); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_CC); + declare!(DMA1_STREAM7); + // declare!(FMC); + declare!(SDIO); + declare!(TIM5); + declare!(SPI3); + declare!(UART4); + declare!(UART5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(ETH); + declare!(ETH_WKUP); + declare!(CAN2_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(OTG_FS); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(I2C3_EV); + declare!(I2C3_ER); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_WKUP); + declare!(OTG_HS); + declare!(DCMI); + declare!(CRYP); + declare!(HASH_RNG); + declare!(FPU); + // declare!(UART7); + // declare!(UART8); + // declare!(SPI4); + // declare!(SPI5); + // declare!(SPI6); + // declare!(SAI1); + declare!(LCD_TFT); + declare!(LCD_TFT_1); + // declare!(DMA2D); +} + +#[cfg(feature = "stm32f407")] +mod irqs { + use super::*; + + declare!(WWDG); + declare!(PVD); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(CAN1_TX); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_UP_TIM10); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(I2C1_EV); + declare!(I2C1_ER); + declare!(I2C2_EV); + declare!(I2C2_ER); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(EXTI15_10); + declare!(RTC_ALARM); + declare!(OTG_FS_WKUP); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_UP_TIM13); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_CC); + declare!(DMA1_STREAM7); + declare!(FSMC); + declare!(SDIO); + declare!(TIM5); + declare!(SPI3); + declare!(UART4); + declare!(UART5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(ETH); + declare!(ETH_WKUP); + declare!(CAN2_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(OTG_FS); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(I2C3_EV); + declare!(I2C3_ER); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_WKUP); + declare!(OTG_HS); + declare!(DCMI); + declare!(CRYP); + declare!(HASH_RNG); + declare!(FPU); + declare!(LCD_TFT); + declare!(LCD_TFT_1); +} + +#[cfg(feature = "stm32f410")] +mod irqs { + use super::*; + + declare!(WWDG); + declare!(PVD); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + declare!(FLASH); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(PWM1_UP); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(I2C1_EV); + declare!(I2C1_ER); + declare!(I2C2_EV); + declare!(I2C2_ER); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(EXTI15_10); + declare!(RTC_ALARM); + declare!(DMA1_STREAM7); + declare!(TIM5); + declare!(TIM6_DAC1); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(EXTI19); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(EXTI20); + declare!(RNG); + declare!(FPU); + declare!(SPI5); + declare!(I2C4_EV); + declare!(I2C4_ER); + declare!(LPTIM1); +} + +#[cfg(feature = "stm32f411")] +mod irqs { + use super::*; + + declare!(WWDG); + declare!(PVD); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + declare!(FLASH); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_UP_TIM10); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(I2C1_EV); + declare!(I2C1_ER); + declare!(I2C2_EV); + declare!(I2C2_ER); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(EXTI15_10); + declare!(RTC_ALARM); + declare!(OTG_FS_WKUP); + declare!(DMA1_STREAM7); + declare!(SDIO); + declare!(TIM5); + declare!(SPI3); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(OTG_FS); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(I2C3_EV); + declare!(I2C3_ER); + declare!(FPU); + declare!(SPI4); + declare!(SPI5); +} + +#[cfg(feature = "stm32f412")] +mod irqs { + use super::*; + + declare!(WWDG); + declare!(PVD); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + declare!(FLASH); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(CAN1_TX); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_UP_TIM10); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(I2C1_EV); + declare!(I2C1_ER); + declare!(I2C2_EV); + declare!(I2C2_ER); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(EXTI15_10); + declare!(RTC_ALARM); + declare!(OTG_FS_WKUP); + declare!(TIM12); + declare!(TIM13); + declare!(TIM14); + declare!(TIM8_CC); + declare!(DMA1_STREAM7); + declare!(FSMC); + declare!(SDIO); + declare!(TIM5); + declare!(SPI3); + declare!(TIM6_DACUNDER); + declare!(TIM7); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(CAN2_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(OTG_FS); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(I2C3_EV); + declare!(I2C3_ER); + declare!(HASH_RNG); + declare!(FPU); + declare!(SPI4); + declare!(SPI5); + declare!(QUAD_SPI); + declare!(I2CFMP1_EVENT); + declare!(I2CFMP1_ERROR); +} + +#[cfg(feature = "stm32f413")] +mod irqs { + use super::*; + + declare!(PVD); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + declare!(FLASH); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(CAN1_TX); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_UP_TIM10); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(I2C1_EVT); + declare!(I2C1_ERR); + declare!(I2C2_EVT); + declare!(I2C2_ERR); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(EXTI15_10); + declare!(EXTI17_RTC_ALARM); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_UP_TIM13); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_CC); + declare!(DMA1_STREAM7); + declare!(FSMC); + declare!(SDIO); + declare!(TIM5); + declare!(SPI3); + declare!(USART4); + declare!(UART5); + declare!(TIM6_GLB_IT_DAC1_DAC2); + declare!(TIM7); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(CAN2_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(OTG_FS); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(I2C3_EV); + declare!(I2C3_ER); + declare!(CAN3_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CRYPTO); + declare!(RNG); + declare!(FPU); + declare!(USART7); + declare!(USART8); + declare!(SPI4); + declare!(SPI5); + declare!(SAI1); + declare!(UART9); + declare!(UART10); + declare!(QUADSPI); + declare!(I2CFMP1EVENT); + declare!(I2CFMP1ERROR); + declare!(LPTIM1_OR_IT_EIT_23); + declare!(DFSDM2_FILTER1); + declare!(DFSDM2_FILTER2); + declare!(DFSDM2_FILTER3); + declare!(DFSDM2_FILTER4); +} + +#[cfg(feature = "stm32f427")] +mod irqs { + use super::*; + + declare!(WWDG); + declare!(PVD); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + declare!(FLASH); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(CAN1_TX); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_UP_TIM10); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(I2C1_EV); + declare!(I2C1_ER); + declare!(I2C2_EV); + declare!(I2C2_ER); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(EXTI15_10); + declare!(RTC_ALARM); + declare!(OTG_FS_WKUP); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_UP_TIM13); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_CC); + declare!(DMA1_STREAM7); + declare!(FMC); + declare!(SDIO); + declare!(TIM5); + declare!(SPI3); + declare!(UART4); + declare!(UART5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(ETH); + declare!(ETH_WKUP); + declare!(CAN2_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(OTG_FS); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(I2C3_EV); + declare!(I2C3_ER); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_WKUP); + declare!(OTG_HS); + declare!(DCMI); + declare!(CRYP); + declare!(HASH_RNG); + declare!(FPU); + declare!(UART7); + declare!(UART8); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(LCD_TFT); + declare!(LCD_TFT_1); +} + +#[cfg(feature = "stm32f429")] +mod irqs { + use super::*; + + declare!(WWDG); + declare!(PVD); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + declare!(FLASH); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(CAN1_TX); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_UP_TIM10); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(I2C1_EV); + declare!(I2C1_ER); + declare!(I2C2_EV); + declare!(I2C2_ER); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(EXTI15_10); + declare!(RTC_ALARM); + declare!(OTG_FS_WKUP); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_UP_TIM13); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_CC); + declare!(DMA1_STREAM7); + declare!(FMC); + declare!(SDIO); + declare!(TIM5); + declare!(SPI3); + declare!(UART4); + declare!(UART5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(ETH); + declare!(ETH_WKUP); + declare!(CAN2_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(OTG_FS); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(I2C3_EV); + declare!(I2C3_ER); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_WKUP); + declare!(OTG_HS); + declare!(DCMI); + declare!(CRYP); + declare!(HASH_RNG); + declare!(FPU); + declare!(UART7); + declare!(UART8); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SAI1); + declare!(LCD_TFT); + declare!(LCD_TFT_1); + declare!(DMA2D); +} + +#[cfg(feature = "stm32f446")] +mod irqs { + use super::*; + + declare!(WWDG); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + declare!(FLASH); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(CAN1_TX); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_UP_TIM10); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(I2C1_EV); + declare!(I2C1_ER); + declare!(I2C2_EV); + declare!(I2C2_ER); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(EXTI15_10); + declare!(RTC_ALARM); + declare!(OTG_FS_WKUP); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_UP_TIM13); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_CC); + declare!(DMA1_STREAM7); + declare!(FMC); + declare!(SDIO); + declare!(TIM5); + declare!(SPI3); + declare!(UART4); + declare!(UART5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(ETH); + declare!(ETH_WKUP); + declare!(CAN2_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(OTG_FS); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(I2C3_EV); + declare!(I2C3_ER); + declare!(DCMI); + declare!(FPU); + declare!(UART7); + declare!(UART8); + declare!(SPI4); + declare!(LCD_TFT); + declare!(LCD_TFT_1); +} + +#[cfg(feature = "stm32f469")] +mod irqs { + use super::*; + + declare!(WWDG); + declare!(PVD); + declare!(TAMP_STAMP); + declare!(RTC_WKUP); + declare!(FLASH); + declare!(RCC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(DMA1_STREAM0); + declare!(DMA1_STREAM1); + declare!(DMA1_STREAM2); + declare!(DMA1_STREAM3); + declare!(DMA1_STREAM4); + declare!(DMA1_STREAM5); + declare!(DMA1_STREAM6); + declare!(ADC); + declare!(CAN1_TX); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(EXTI9_5); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_UP_TIM10); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_CC); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(I2C1_EV); + declare!(I2C1_ER); + declare!(I2C2_EV); + declare!(I2C2_ER); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(EXTI15_10); + declare!(RTC_ALARM); + declare!(OTG_FS_WKUP); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_UP_TIM13); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_CC); + declare!(DMA1_STREAM7); + declare!(FMC); + declare!(SDIO); + declare!(TIM5); + declare!(SPI3); + declare!(UART4); + declare!(UART5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(DMA2_STREAM0); + declare!(DMA2_STREAM1); + declare!(DMA2_STREAM2); + declare!(DMA2_STREAM3); + declare!(DMA2_STREAM4); + declare!(ETH); + declare!(ETH_WKUP); + declare!(CAN2_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(OTG_FS); + declare!(DMA2_STREAM5); + declare!(DMA2_STREAM6); + declare!(DMA2_STREAM7); + declare!(USART6); + declare!(I2C3_EV); + declare!(I2C3_ER); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_WKUP); + declare!(OTG_HS); + declare!(DCMI); + declare!(CRYP); + declare!(HASH_RNG); + declare!(FPU); + declare!(UART7); + declare!(UART8); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SAI1); + declare!(LCD_TFT); + declare!(LCD_TFT_1); + declare!(DMA2D); + declare!(QUADSPI); + declare!(DSIHOST); +} + +#[cfg(feature = "stm32l0x1")] +mod irqs { + use super::*; + declare!(WWDG); + declare!(PVD); + declare!(RTC); + declare!(FLASH); + declare!(RCC); + declare!(EXTI0_1); + declare!(EXTI2_3); + declare!(EXTI4_15); + declare!(DMA1_CHANNEL1); + declare!(DMA1_CHANNEL2_3); + declare!(DMA1_CHANNEL4_7); + declare!(ADC_COMP); + declare!(LPTIM1); + declare!(USART4_USART5); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6); + declare!(TIM7); + declare!(TIM21); + declare!(I2C3); + declare!(TIM22); + declare!(I2C1); + declare!(I2C2); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(AES_RNG_LPUART1); +} + +#[cfg(feature = "stm32l0x2")] +mod irqs { + use super::*; + declare!(WWDG); + declare!(PVD); + declare!(RTC); + declare!(RCC); + declare!(EXTI0_1); + declare!(EXTI2_3); + declare!(EXTI4_15); + declare!(TSC); + declare!(DMA1_CHANNEL1); + declare!(DMA1_CHANNEL2_3); + declare!(DMA1_CHANNEL4_7); + declare!(ADC_COMP); + declare!(LPTIM1); + declare!(USART4_USART5); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM21); + declare!(I2C3); + declare!(TIM22); + declare!(I2C1); + declare!(I2C2); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(AES_RNG_LPUART1); + declare!(USB); +} + +#[cfg(feature = "stm32l0x3")] +mod irqs { + use super::*; + declare!(WWDG); + declare!(PVD); + declare!(RTC); + declare!(RCC); + declare!(EXTI0_1); + declare!(EXTI2_3); + declare!(EXTI4_15); + declare!(TSC); + declare!(DMA1_CHANNEL1); + declare!(DMA1_CHANNEL2_3); + declare!(DMA1_CHANNEL4_7); + declare!(ADC_COMP); + declare!(LPTIM1); + declare!(USART4_USART5); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM21); + declare!(I2C3); + declare!(TIM22); + declare!(I2C1); + declare!(I2C2); + declare!(SPI1); + declare!(SPI2); + declare!(USART1); + declare!(USART2); + declare!(AES_RNG_LPUART1); + declare!(LCD); + declare!(USB); +} + +pub use irqs::*; diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs new file mode 100644 index 000000000..a1f40b2c7 --- /dev/null +++ b/embassy-stm32/src/lib.rs @@ -0,0 +1,35 @@ +#![no_std] +#![feature(generic_associated_types)] +#![feature(asm)] +#![feature(min_type_alias_impl_trait)] +#![feature(impl_trait_in_bindings)] +#![feature(type_alias_impl_trait)] +#![allow(incomplete_features)] + +#[cfg(any( + feature = "stm32f401", + feature = "stm32f405", + feature = "stm32f407", + feature = "stm32f410", + feature = "stm32f411", + feature = "stm32f412", + feature = "stm32f413", + feature = "stm32f415", + feature = "stm32f417", + feature = "stm32f423", + feature = "stm32f427", + feature = "stm32f429", + feature = "stm32f437", + feature = "stm32f439", + feature = "stm32f446", + feature = "stm32f469", + feature = "stm32f479", +))] +pub use {stm32f4xx_hal as hal, stm32f4xx_hal::stm32 as pac}; + +#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))] +pub use {stm32l0xx_hal as hal, stm32l0xx_hal::pac}; + +pub mod fmt; + +pub mod interrupt; diff --git a/embassy-stm32f4/Cargo.toml b/embassy-stm32f4/Cargo.toml index 935b4a2b0..ae3273d67 100644 --- a/embassy-stm32f4/Cargo.toml +++ b/embassy-stm32f4/Cargo.toml @@ -11,27 +11,27 @@ defmt-info = [ ] defmt-warn = [ ] defmt-error = [ ] -stm32f401 = ["stm32f4xx-hal/stm32f401"] -stm32f405 = ["stm32f4xx-hal/stm32f405"] -stm32f407 = ["stm32f4xx-hal/stm32f407"] -stm32f410 = ["stm32f4xx-hal/stm32f410"] -stm32f411 = ["stm32f4xx-hal/stm32f411"] -stm32f412 = ["stm32f4xx-hal/stm32f412"] -stm32f413 = ["stm32f4xx-hal/stm32f413"] -stm32f415 = ["stm32f4xx-hal/stm32f405"] -stm32f417 = ["stm32f4xx-hal/stm32f407"] -stm32f423 = ["stm32f4xx-hal/stm32f413"] -stm32f427 = ["stm32f4xx-hal/stm32f427"] -stm32f429 = ["stm32f4xx-hal/stm32f429"] -stm32f437 = ["stm32f4xx-hal/stm32f427"] -stm32f439 = ["stm32f4xx-hal/stm32f429"] -stm32f446 = ["stm32f4xx-hal/stm32f446"] -stm32f469 = ["stm32f4xx-hal/stm32f469"] -stm32f479 = ["stm32f4xx-hal/stm32f469"] +stm32f401 = ["stm32f4xx-hal/stm32f401", "embassy-stm32/stm32f401"] +stm32f405 = ["stm32f4xx-hal/stm32f405", "embassy-stm32/stm32f405"] +stm32f407 = ["stm32f4xx-hal/stm32f407", "embassy-stm32/stm32f407"] +stm32f410 = ["stm32f4xx-hal/stm32f410", "embassy-stm32/stm32f410"] +stm32f411 = ["stm32f4xx-hal/stm32f411", "embassy-stm32/stm32f411"] +stm32f412 = ["stm32f4xx-hal/stm32f412", "embassy-stm32/stm32f412"] +stm32f413 = ["stm32f4xx-hal/stm32f413", "embassy-stm32/stm32f413"] +stm32f415 = ["stm32f4xx-hal/stm32f405", "embassy-stm32/stm32f415"] +stm32f417 = ["stm32f4xx-hal/stm32f407", "embassy-stm32/stm32f417"] +stm32f423 = ["stm32f4xx-hal/stm32f413", "embassy-stm32/stm32f423"] +stm32f427 = ["stm32f4xx-hal/stm32f427", "embassy-stm32/stm32f427"] +stm32f429 = ["stm32f4xx-hal/stm32f429", "embassy-stm32/stm32f429"] +stm32f437 = ["stm32f4xx-hal/stm32f427", "embassy-stm32/stm32f437"] +stm32f439 = ["stm32f4xx-hal/stm32f429", "embassy-stm32/stm32f439"] +stm32f446 = ["stm32f4xx-hal/stm32f446", "embassy-stm32/stm32f446"] +stm32f469 = ["stm32f4xx-hal/stm32f469", "embassy-stm32/stm32f469"] +stm32f479 = ["stm32f4xx-hal/stm32f469", "embassy-stm32/stm32f479"] [dependencies] embassy = { version = "0.1.0", path = "../embassy" } - +embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32" } defmt = { version = "0.2.0", optional = true } log = { version = "0.4.11", optional = true } cortex-m-rt = "0.6.13" diff --git a/embassy-stm32f4/src/fmt.rs b/embassy-stm32f4/src/fmt.rs deleted file mode 100644 index 160642ccd..000000000 --- a/embassy-stm32f4/src/fmt.rs +++ /dev/null @@ -1,114 +0,0 @@ -#![macro_use] -#![allow(clippy::module_inception)] -#![allow(unused)] - -#[cfg(all(feature = "defmt", feature = "log"))] -compile_error!("You may not enable both `defmt` and `log` features."); - -pub use fmt::*; - -#[cfg(feature = "defmt")] -mod fmt { - pub use defmt::{ - assert, assert_eq, assert_ne, debug, debug_assert, debug_assert_eq, debug_assert_ne, error, - info, panic, todo, trace, unreachable, unwrap, warn, - }; -} - -#[cfg(feature = "log")] -mod fmt { - pub use core::{ - assert, assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, panic, todo, - unreachable, - }; - pub use log::{debug, error, info, trace, warn}; -} - -#[cfg(not(any(feature = "defmt", feature = "log")))] -mod fmt { - #![macro_use] - - pub use core::{ - assert, assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, panic, todo, - unreachable, - }; - - macro_rules! trace { - ($($msg:expr),+ $(,)?) => { - () - }; - } - - macro_rules! debug { - ($($msg:expr),+ $(,)?) => { - () - }; - } - - macro_rules! info { - ($($msg:expr),+ $(,)?) => { - () - }; - } - - macro_rules! warn { - ($($msg:expr),+ $(,)?) => { - () - }; - } - - macro_rules! error { - ($($msg:expr),+ $(,)?) => { - () - }; - } -} - -#[cfg(not(feature = "defmt"))] -macro_rules! unwrap { - ($arg:expr) => { - match $crate::fmt::Try::into_result($arg) { - ::core::result::Result::Ok(t) => t, - ::core::result::Result::Err(e) => { - ::core::panic!("unwrap of `{}` failed: {:?}", ::core::stringify!($arg), e); - } - } - }; - ($arg:expr, $($msg:expr),+ $(,)? ) => { - match $crate::fmt::Try::into_result($arg) { - ::core::result::Result::Ok(t) => t, - ::core::result::Result::Err(e) => { - ::core::panic!("unwrap of `{}` failed: {}: {:?}", ::core::stringify!($arg), ::core::format_args!($($msg,)*), e); - } - } - } -} - -#[derive(Debug, Copy, Clone, Eq, PartialEq)] -pub struct NoneError; - -pub trait Try { - type Ok; - type Error; - fn into_result(self) -> Result; -} - -impl Try for Option { - type Ok = T; - type Error = NoneError; - - #[inline] - fn into_result(self) -> Result { - self.ok_or(NoneError) - } -} - -impl Try for Result { - type Ok = T; - type Error = E; - - #[inline] - fn into_result(self) -> Self { - self - } -} diff --git a/embassy-stm32f4/src/interrupt.rs b/embassy-stm32f4/src/interrupt.rs deleted file mode 100644 index 402aee582..000000000 --- a/embassy-stm32f4/src/interrupt.rs +++ /dev/null @@ -1,1025 +0,0 @@ -//! Interrupt management -//! -//! This module implements an API for managing interrupts compatible with -//! nrf_softdevice::interrupt. Intended for switching between the two at compile-time. - -use core::sync::atomic::{compiler_fence, Ordering}; - -use crate::pac::NVIC_PRIO_BITS; - -// Re-exports -pub use cortex_m::interrupt::{CriticalSection, Mutex}; -pub use embassy::interrupt::{declare, take, Interrupt}; - -#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[repr(u8)] -pub enum Priority { - Level0 = 0, - Level1 = 1, - Level2 = 2, - Level3 = 3, - Level4 = 4, - Level5 = 5, - Level6 = 6, - Level7 = 7, - Level8 = 8, - Level9 = 9, - Level10 = 10, - Level11 = 11, - Level12 = 12, - Level13 = 13, - Level14 = 14, - Level15 = 15, -} - -impl From for Priority { - fn from(priority: u8) -> Self { - match priority >> (8 - NVIC_PRIO_BITS) { - 0 => Self::Level0, - 1 => Self::Level1, - 2 => Self::Level2, - 3 => Self::Level3, - 4 => Self::Level4, - 5 => Self::Level5, - 6 => Self::Level6, - 7 => Self::Level7, - 8 => Self::Level8, - 9 => Self::Level9, - 10 => Self::Level10, - 11 => Self::Level11, - 12 => Self::Level12, - 13 => Self::Level13, - 14 => Self::Level14, - 15 => Self::Level15, - _ => unreachable!(), - } - } -} - -impl From for u8 { - fn from(p: Priority) -> Self { - (p as u8) << (8 - NVIC_PRIO_BITS) - } -} - -#[inline] -pub fn free(f: F) -> R -where - F: FnOnce(&CriticalSection) -> R, -{ - unsafe { - // TODO: assert that we're in privileged level - // Needed because disabling irqs in non-privileged level is a noop, which would break safety. - - let primask: u32; - asm!("mrs {}, PRIMASK", out(reg) primask); - - asm!("cpsid i"); - - // Prevent compiler from reordering operations inside/outside the critical section. - compiler_fence(Ordering::SeqCst); - - let r = f(&CriticalSection::new()); - - compiler_fence(Ordering::SeqCst); - - if primask & 1 == 0 { - asm!("cpsie i"); - } - - r - } -} - -#[cfg(feature = "stm32f401")] -mod irqs { - use super::*; - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(DMA1_STREAM7); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(FPU); - declare!(SPI4); -} - -#[cfg(feature = "stm32f405")] -mod irqs { - use super::*; - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - // declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - // declare!(FMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_WKUP); - declare!(OTG_HS); - declare!(DCMI); - declare!(CRYP); - declare!(HASH_RNG); - declare!(FPU); - // declare!(UART7); - // declare!(UART8); - // declare!(SPI4); - // declare!(SPI5); - // declare!(SPI6); - // declare!(SAI1); - declare!(LCD_TFT); - declare!(LCD_TFT_1); - // declare!(DMA2D); -} - -#[cfg(feature = "stm32f407")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FSMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_WKUP); - declare!(OTG_HS); - declare!(DCMI); - declare!(CRYP); - declare!(HASH_RNG); - declare!(FPU); - declare!(LCD_TFT); - declare!(LCD_TFT_1); -} - -#[cfg(feature = "stm32f410")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(PWM1_UP); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(DMA1_STREAM7); - declare!(TIM5); - declare!(TIM6_DAC1); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(EXTI19); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(EXTI20); - declare!(RNG); - declare!(FPU); - declare!(SPI5); - declare!(I2C4_EV); - declare!(I2C4_ER); - declare!(LPTIM1); -} - -#[cfg(feature = "stm32f411")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(DMA1_STREAM7); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(FPU); - declare!(SPI4); - declare!(SPI5); -} - -#[cfg(feature = "stm32f412")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM12); - declare!(TIM13); - declare!(TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FSMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(TIM6_DACUNDER); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(HASH_RNG); - declare!(FPU); - declare!(SPI4); - declare!(SPI5); - declare!(QUAD_SPI); - declare!(I2CFMP1_EVENT); - declare!(I2CFMP1_ERROR); -} - -#[cfg(feature = "stm32f413")] -mod irqs { - use super::*; - - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EVT); - declare!(I2C1_ERR); - declare!(I2C2_EVT); - declare!(I2C2_ERR); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(EXTI17_RTC_ALARM); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FSMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(USART4); - declare!(UART5); - declare!(TIM6_GLB_IT_DAC1_DAC2); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(CAN3_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CRYPTO); - declare!(RNG); - declare!(FPU); - declare!(USART7); - declare!(USART8); - declare!(SPI4); - declare!(SPI5); - declare!(SAI1); - declare!(UART9); - declare!(UART10); - declare!(QUADSPI); - declare!(I2CFMP1EVENT); - declare!(I2CFMP1ERROR); - declare!(LPTIM1_OR_IT_EIT_23); - declare!(DFSDM2_FILTER1); - declare!(DFSDM2_FILTER2); - declare!(DFSDM2_FILTER3); - declare!(DFSDM2_FILTER4); -} - -#[cfg(feature = "stm32f427")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_WKUP); - declare!(OTG_HS); - declare!(DCMI); - declare!(CRYP); - declare!(HASH_RNG); - declare!(FPU); - declare!(UART7); - declare!(UART8); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(LCD_TFT); - declare!(LCD_TFT_1); -} - -#[cfg(feature = "stm32f429")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_WKUP); - declare!(OTG_HS); - declare!(DCMI); - declare!(CRYP); - declare!(HASH_RNG); - declare!(FPU); - declare!(UART7); - declare!(UART8); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(SAI1); - declare!(LCD_TFT); - declare!(LCD_TFT_1); - declare!(DMA2D); -} - -#[cfg(feature = "stm32f446")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(DCMI); - declare!(FPU); - declare!(UART7); - declare!(UART8); - declare!(SPI4); - declare!(LCD_TFT); - declare!(LCD_TFT_1); -} - -#[cfg(feature = "stm32f469")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_WKUP); - declare!(OTG_HS); - declare!(DCMI); - declare!(CRYP); - declare!(HASH_RNG); - declare!(FPU); - declare!(UART7); - declare!(UART8); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(SAI1); - declare!(LCD_TFT); - declare!(LCD_TFT_1); - declare!(DMA2D); - declare!(QUADSPI); - declare!(DSIHOST); -} - -pub use irqs::*; diff --git a/embassy-stm32f4/src/lib.rs b/embassy-stm32f4/src/lib.rs index 82d26d952..0d490525c 100644 --- a/embassy-stm32f4/src/lib.rs +++ b/embassy-stm32f4/src/lib.rs @@ -307,16 +307,11 @@ compile_error!( "Multile chip features activated. You must activate exactly one of the following features: " ); -pub use stm32f4xx_hal as hal; -pub use stm32f4xx_hal::stm32 as pac; - -// This mod MUST go first, so that the others see its macros. -pub(crate) mod fmt; +pub use embassy_stm32::{fmt, hal, interrupt, pac}; #[cfg(not(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411",)))] pub mod can; pub mod exti; -pub mod interrupt; #[cfg(not(feature = "stm32f410"))] pub mod qei; pub mod rtc; diff --git a/embassy-stm32l0/Cargo.toml b/embassy-stm32l0/Cargo.toml index c74d14076..8926763d2 100644 --- a/embassy-stm32l0/Cargo.toml +++ b/embassy-stm32l0/Cargo.toml @@ -11,12 +11,13 @@ defmt-info = [ ] defmt-warn = [ ] defmt-error = [ ] -stm32l0x1 = ["stm32l0xx-hal/stm32l0x1"] -stm32l0x2 = ["stm32l0xx-hal/stm32l0x2"] -stm32l0x3 = ["stm32l0xx-hal/stm32l0x3"] +stm32l0x1 = ["stm32l0xx-hal/stm32l0x1", "embassy-stm32/stm32l0x1"] +stm32l0x2 = ["stm32l0xx-hal/stm32l0x2", "embassy-stm32/stm32l0x2"] +stm32l0x3 = ["stm32l0xx-hal/stm32l0x3", "embassy-stm32/stm32l0x3"] [dependencies] embassy = { version = "0.1.0", path = "../embassy" } +embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32" } defmt = { version = "0.2.0", optional = true } futures = { version = "0.3.5", default-features = false, features = [ "cfg-target-has-atomic", "unstable" ] } log = { version = "0.4.11", optional = true } diff --git a/embassy-stm32l0/src/fmt.rs b/embassy-stm32l0/src/fmt.rs deleted file mode 100644 index 1be1057a7..000000000 --- a/embassy-stm32l0/src/fmt.rs +++ /dev/null @@ -1,119 +0,0 @@ -#![macro_use] -#![allow(clippy::module_inception)] - -#[cfg(all(feature = "defmt", feature = "log"))] -compile_error!("You may not enable both `defmt` and `log` features."); - -pub use fmt::*; - -#[cfg(feature = "defmt")] -mod fmt { - pub use defmt::{ - assert, assert_eq, assert_ne, debug, debug_assert, debug_assert_eq, debug_assert_ne, error, - info, panic, todo, trace, unreachable, unwrap, warn, - }; -} - -#[cfg(feature = "log")] -mod fmt { - pub use core::{ - assert, assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, panic, todo, - unreachable, - }; - pub use log::{debug, error, info, trace, warn}; -} - -#[cfg(not(any(feature = "defmt", feature = "log")))] -mod fmt { - #![macro_use] - - pub use core::{ - assert, assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, panic, todo, - unreachable, - }; - - #[macro_export] - macro_rules! trace { - ($($msg:expr),+ $(,)?) => { - () - }; - } - - #[macro_export] - macro_rules! debug { - ($($msg:expr),+ $(,)?) => { - () - }; - } - - #[macro_export] - macro_rules! info { - ($($msg:expr),+ $(,)?) => { - () - }; - } - - #[macro_export] - macro_rules! warn { - ($($msg:expr),+ $(,)?) => { - () - }; - } - - #[macro_export] - macro_rules! error { - ($($msg:expr),+ $(,)?) => { - () - }; - } -} - -#[cfg(not(feature = "defmt"))] -#[macro_export] -macro_rules! unwrap { - ($arg:expr) => { - match $crate::fmt::Try::into_result($arg) { - ::core::result::Result::Ok(t) => t, - ::core::result::Result::Err(e) => { - ::core::panic!("unwrap of `{}` failed: {:?}", ::core::stringify!($arg), e); - } - } - }; - ($arg:expr, $($msg:expr),+ $(,)? ) => { - match $crate::fmt::Try::into_result($arg) { - ::core::result::Result::Ok(t) => t, - ::core::result::Result::Err(e) => { - ::core::panic!("unwrap of `{}` failed: {}: {:?}", ::core::stringify!($arg), ::core::format_args!($($msg,)*), e); - } - } - } -} - -#[derive(Debug, Copy, Clone, Eq, PartialEq)] -pub struct NoneError; - -pub trait Try { - type Ok; - type Error; - fn into_result(self) -> Result; -} - -impl Try for Option { - type Ok = T; - type Error = NoneError; - - #[inline] - fn into_result(self) -> Result { - self.ok_or(NoneError) - } -} - -impl Try for Result { - type Ok = T; - type Error = E; - - #[inline] - fn into_result(self) -> Self { - self - } -} diff --git a/embassy-stm32l0/src/interrupt.rs b/embassy-stm32l0/src/interrupt.rs deleted file mode 100644 index 499f3f275..000000000 --- a/embassy-stm32l0/src/interrupt.rs +++ /dev/null @@ -1,162 +0,0 @@ -//! Interrupt management -use crate::pac::NVIC_PRIO_BITS; - -// Re-exports -pub use cortex_m::interrupt::{CriticalSection, Mutex}; -pub use embassy::interrupt::{declare, take, Interrupt}; - -#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[repr(u8)] -pub enum Priority { - Level0 = 0, - Level1 = 1, - Level2 = 2, - Level3 = 3, - Level4 = 4, - Level5 = 5, - Level6 = 6, - Level7 = 7, - Level8 = 8, - Level9 = 9, - Level10 = 10, - Level11 = 11, - Level12 = 12, - Level13 = 13, - Level14 = 14, - Level15 = 15, -} - -impl From for Priority { - fn from(priority: u8) -> Self { - match priority >> (8 - NVIC_PRIO_BITS) { - 0 => Self::Level0, - 1 => Self::Level1, - 2 => Self::Level2, - 3 => Self::Level3, - 4 => Self::Level4, - 5 => Self::Level5, - 6 => Self::Level6, - 7 => Self::Level7, - 8 => Self::Level8, - 9 => Self::Level9, - 10 => Self::Level10, - 11 => Self::Level11, - 12 => Self::Level12, - 13 => Self::Level13, - 14 => Self::Level14, - 15 => Self::Level15, - _ => unreachable!(), - } - } -} - -impl From for u8 { - fn from(p: Priority) -> Self { - (p as u8) << (8 - NVIC_PRIO_BITS) - } -} - -#[cfg(feature = "stm32l0x1")] -mod irqs { - use super::*; - declare!(WWDG); - declare!(PVD); - declare!(RTC); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0_1); - declare!(EXTI2_3); - declare!(EXTI4_15); - declare!(DMA1_CHANNEL1); - declare!(DMA1_CHANNEL2_3); - declare!(DMA1_CHANNEL4_7); - declare!(ADC_COMP); - declare!(LPTIM1); - declare!(USART4_USART5); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6); - declare!(TIM7); - declare!(TIM21); - declare!(I2C3); - declare!(TIM22); - declare!(I2C1); - declare!(I2C2); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(AES_RNG_LPUART1); -} - -#[cfg(feature = "stm32l0x2")] -mod irqs { - use super::*; - declare!(WWDG); - declare!(PVD); - declare!(RTC); - declare!(RCC); - declare!(EXTI0_1); - declare!(EXTI2_3); - declare!(EXTI4_15); - declare!(TSC); - declare!(DMA1_CHANNEL1); - declare!(DMA1_CHANNEL2_3); - declare!(DMA1_CHANNEL4_7); - declare!(ADC_COMP); - declare!(LPTIM1); - declare!(USART4_USART5); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM21); - declare!(I2C3); - declare!(TIM22); - declare!(I2C1); - declare!(I2C2); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(AES_RNG_LPUART1); - declare!(USB); -} - -#[cfg(feature = "stm32l0x3")] -mod irqs { - use super::*; - declare!(WWDG); - declare!(PVD); - declare!(RTC); - declare!(RCC); - declare!(EXTI0_1); - declare!(EXTI2_3); - declare!(EXTI4_15); - declare!(TSC); - declare!(DMA1_CHANNEL1); - declare!(DMA1_CHANNEL2_3); - declare!(DMA1_CHANNEL4_7); - declare!(ADC_COMP); - declare!(LPTIM1); - declare!(USART4_USART5); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM21); - declare!(I2C3); - declare!(TIM22); - declare!(I2C1); - declare!(I2C2); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(AES_RNG_LPUART1); - declare!(LCD); - declare!(USB); -} - -pub use irqs::*; diff --git a/embassy-stm32l0/src/lib.rs b/embassy-stm32l0/src/lib.rs index d030713ca..e80fe6cb4 100644 --- a/embassy-stm32l0/src/lib.rs +++ b/embassy-stm32l0/src/lib.rs @@ -19,11 +19,6 @@ compile_error!( "Multile chip features activated. You must activate exactly one of the following features: " ); -pub use stm32l0xx_hal as hal; -pub use stm32l0xx_hal::pac; - -// This mod MUST go first, so that the others see its macros. -pub(crate) mod fmt; +pub use embassy_stm32::{fmt, hal, interrupt, pac}; pub mod exti; -pub mod interrupt; -- cgit