From 0941a76be60a3c95aed9a3e1835ec1de6f03ac12 Mon Sep 17 00:00:00 2001
From: Jakob <jakob.laurell@wattstep.com>
Date: Wed, 6 Aug 2025 15:04:48 +0200
Subject: Add get methods for meo, ossi and ossr

---
 embassy-stm32/src/timer/complementary_pwm.rs | 15 +++++++++++++++
 embassy-stm32/src/timer/low_level.rs         | 15 +++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 1178e7d83..bf76155dd 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -100,11 +100,21 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         self.inner.set_ossi(val);
     }
 
+    /// Get state of OSSR-bit in BDTR register
+    pub fn get_off_state_selection_idle(&self) -> Ossi {
+        self.inner.get_ossi()
+    }
+
     /// Set state of OSSR-bit in BDTR register
     pub fn set_off_state_selection_run(&self, val: Ossr) {
         self.inner.set_ossr(val);
     }
 
+    /// Get state of OSSR-bit in BDTR register
+    pub fn get_off_state_selection_run(&self) -> Ossr {
+        self.inner.get_ossr()
+    }
+
     /// Trigger break input from software
     pub fn trigger_software_break(&self, n: usize) {
         self.inner.trigger_software_break(n);
@@ -115,6 +125,11 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         self.inner.set_moe(enable);
     }
 
+    /// Get Master Output Enable
+    pub fn get_master_output_enable(&mut self) -> bool {
+        self.inner.get_moe()
+    }
+
     /// Set Master Slave Mode 2
     pub fn set_mms2(&mut self, mms2: Mms2) {
         self.inner.set_mms2_selection(mms2);
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index 01bf60869..ac039bb0d 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -691,15 +691,30 @@ impl<'d, T: AdvancedInstance1Channel> Timer<'d, T> {
         self.regs_1ch_cmp().bdtr().modify(|w| w.set_ossi(val));
     }
 
+    /// Get state of OSSI-bit in BDTR register
+    pub fn get_ossi(&self) -> vals::Ossi {
+        self.regs_1ch_cmp().bdtr().read().ossi()
+    }
+
     /// Set state of OSSR-bit in BDTR register
     pub fn set_ossr(&self, val: vals::Ossr) {
         self.regs_1ch_cmp().bdtr().modify(|w| w.set_ossr(val));
     }
 
+    /// Get state of OSSR-bit in BDTR register
+    pub fn get_ossr(&self) -> vals::Ossr {
+        self.regs_1ch_cmp().bdtr().read().ossr()
+    }
+
     /// Set state of MOE-bit in BDTR register to en-/disable output
     pub fn set_moe(&self, enable: bool) {
         self.regs_1ch_cmp().bdtr().modify(|w| w.set_moe(enable));
     }
+
+    /// Get state of MOE-bit in BDTR register
+    pub fn get_moe(&self) -> bool {
+        self.regs_1ch_cmp().bdtr().read().moe()
+    }
 }
 
 #[cfg(not(stm32l0))]
-- 
cgit