From 230237b73cbe6f31780ea407ed13bee1adf8eaa2 Mon Sep 17 00:00:00 2001 From: Bogdan Petru Chircu Mare Date: Mon, 1 Dec 2025 09:08:03 -0800 Subject: Apply rustfmt formatting fixes --- examples/src/bin/dma_channel_link.rs | 88 ++++++++++++++++---------- examples/src/bin/dma_interleave_transfer.rs | 38 ++++++----- examples/src/bin/dma_mem_to_mem.rs | 12 ++-- examples/src/bin/dma_memset.rs | 37 ++++++----- examples/src/bin/dma_ping_pong_transfer.rs | 52 ++++++++------- examples/src/bin/dma_scatter_gather.rs | 42 ++++++------ examples/src/bin/dma_scatter_gather_builder.rs | 17 +++-- examples/src/bin/dma_wrap_transfer.rs | 46 ++++++++------ examples/src/bin/lpuart_dma.rs | 4 +- examples/src/bin/lpuart_ring_buffer.rs | 12 ++-- src/dma.rs | 5 +- 11 files changed, 204 insertions(+), 149 deletions(-) diff --git a/examples/src/bin/dma_channel_link.rs b/examples/src/bin/dma_channel_link.rs index d541dc7f4..34162d931 100644 --- a/examples/src/bin/dma_channel_link.rs +++ b/examples/src/bin/dma_channel_link.rs @@ -18,10 +18,9 @@ use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::dma::{self, DmaChannel, DmaCh0InterruptHandler, DmaCh1InterruptHandler, DmaCh2InterruptHandler}; -use embassy_mcxa::bind_interrupts; +use embassy_mcxa::dma::{self, DmaCh0InterruptHandler, DmaCh1InterruptHandler, DmaCh2InterruptHandler, DmaChannel}; use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx}; -use embassy_mcxa::pac; +use embassy_mcxa::{bind_interrupts, pac}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Buffers @@ -104,10 +103,14 @@ async fn main(_spawner: Spawner) { // Clear Global Halt/Error state dma0.mp_csr().modify(|_, w| { - w.halt().normal_operation() - .hae().normal_operation() - .ecx().normal_operation() - .cx().normal_operation() + w.halt() + .normal_operation() + .hae() + .normal_operation() + .ecx() + .normal_operation() + .cx() + .normal_operation() }); unsafe { @@ -126,8 +129,7 @@ async fn main(_spawner: Spawner) { let lpuart = Lpuart::new_blocking(p.LPUART2, p.P2_2, p.P2_3, config).unwrap(); let (mut tx, _rx) = lpuart.split(); - tx.blocking_write(b"EDMA channel link example begin.\r\n\r\n") - .unwrap(); + tx.blocking_write(b"EDMA channel link example begin.\r\n\r\n").unwrap(); // Initialize buffers unsafe { @@ -180,11 +182,16 @@ async fn main(_spawner: Spawner) { // Reset channel state t.ch_csr().write(|w| { - w.erq().disable() - .earq().disable() - .eei().no_error() - .ebw().disable() - .done().clear_bit_by_one() + w.erq() + .disable() + .earq() + .disable() + .eei() + .no_error() + .ebw() + .disable() + .done() + .clear_bit_by_one() }); t.ch_es().write(|w| w.bits(0)); t.ch_int().write(|w| w.int().clear_bit_by_one()); @@ -211,8 +218,10 @@ async fn main(_spawner: Spawner) { // Major loop: reset source address after major loop let total_bytes = nbytes * count as u32; - t.tcd_slast_sda().write(|w| w.slast_sda().bits(-(total_bytes as i32) as u32)); - t.tcd_dlast_sga().write(|w| w.dlast_sga().bits(-(total_bytes as i32) as u32)); + t.tcd_slast_sda() + .write(|w| w.slast_sda().bits(-(total_bytes as i32) as u32)); + t.tcd_dlast_sga() + .write(|w| w.dlast_sga().bits(-(total_bytes as i32) as u32)); // Major loop count t.tcd_biter_elinkno().write(|w| w.biter().bits(count)); @@ -229,7 +238,6 @@ async fn main(_spawner: Spawner) { } unsafe { - // Channel 0: Transfer 16 bytes total (8 bytes per minor loop, 2 major iterations) // Minor Link -> Channel 1 // Major Link -> Channel 2 @@ -265,34 +273,44 @@ async fn main(_spawner: Spawner) { core::ptr::addr_of!(SRC_BUFFER) as u32, core::ptr::addr_of_mut!(DEST_BUFFER2) as u32, 4, - 16, // full buffer in one minor loop - 1, // 1 major iteration + 16, // full buffer in one minor loop + 1, // 1 major iteration true, // enable interrupt ); } - tx.blocking_write(b"Triggering Channel 0 (1st minor loop)...\r\n").unwrap(); + tx.blocking_write(b"Triggering Channel 0 (1st minor loop)...\r\n") + .unwrap(); // Trigger first minor loop of CH0 - unsafe { ch0.trigger_start(); } + unsafe { + ch0.trigger_start(); + } // Wait for CH1 to complete (triggered by CH0 minor link) while !ch1.is_done() { cortex_m::asm::nop(); } - unsafe { ch1.clear_done(); } + unsafe { + ch1.clear_done(); + } tx.blocking_write(b"CH1 done (via minor link).\r\n").unwrap(); - tx.blocking_write(b"Triggering Channel 0 (2nd minor loop)...\r\n").unwrap(); + tx.blocking_write(b"Triggering Channel 0 (2nd minor loop)...\r\n") + .unwrap(); // Trigger second minor loop of CH0 - unsafe { ch0.trigger_start(); } + unsafe { + ch0.trigger_start(); + } // Wait for CH0 major loop to complete while !ch0.is_done() { cortex_m::asm::nop(); } - unsafe { ch0.clear_done(); } + unsafe { + ch0.clear_done(); + } tx.blocking_write(b"CH0 major loop done.\r\n").unwrap(); @@ -302,12 +320,13 @@ async fn main(_spawner: Spawner) { while !ch2.is_done() { cortex_m::asm::nop(); } - unsafe { ch2.clear_done(); } + unsafe { + ch2.clear_done(); + } tx.blocking_write(b"CH2 done (via major link).\r\n\r\n").unwrap(); - tx.blocking_write(b"EDMA channel link example finish.\r\n\r\n") - .unwrap(); + tx.blocking_write(b"EDMA channel link example finish.\r\n\r\n").unwrap(); tx.blocking_write(b"DEST0 (after): ").unwrap(); print_buffer(&mut tx, core::ptr::addr_of!(DEST_BUFFER0) as *const u32, 4); @@ -330,9 +349,15 @@ async fn main(_spawner: Spawner) { let dst2_ptr = core::ptr::addr_of!(DEST_BUFFER2) as *const u32; for i in 0..4 { - if *dst0_ptr.add(i) != *src_ptr.add(i) { success = false; } - if *dst1_ptr.add(i) != *src_ptr.add(i) { success = false; } - if *dst2_ptr.add(i) != *src_ptr.add(i) { success = false; } + if *dst0_ptr.add(i) != *src_ptr.add(i) { + success = false; + } + if *dst1_ptr.add(i) != *src_ptr.add(i) { + success = false; + } + if *dst2_ptr.add(i) != *src_ptr.add(i) { + success = false; + } } } @@ -348,4 +373,3 @@ async fn main(_spawner: Spawner) { cortex_m::asm::wfe(); } } - diff --git a/examples/src/bin/dma_interleave_transfer.rs b/examples/src/bin/dma_interleave_transfer.rs index 949ea0605..c0ebb0a46 100644 --- a/examples/src/bin/dma_interleave_transfer.rs +++ b/examples/src/bin/dma_interleave_transfer.rs @@ -12,10 +12,9 @@ use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::dma::{DmaChannel, DmaCh0InterruptHandler}; -use embassy_mcxa::bind_interrupts; +use embassy_mcxa::dma::{DmaCh0InterruptHandler, DmaChannel}; use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx}; -use embassy_mcxa::pac; +use embassy_mcxa::{bind_interrupts, pac}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Bind DMA channel 0 interrupt using Embassy-style macro @@ -125,22 +124,29 @@ async fn main(_spawner: Spawner) { // Reset channel state t.ch_csr().write(|w| { - w.erq().disable() - .earq().disable() - .eei().no_error() - .ebw().disable() - .done().clear_bit_by_one() + w.erq() + .disable() + .earq() + .disable() + .eei() + .no_error() + .ebw() + .disable() + .done() + .clear_bit_by_one() }); t.ch_es().write(|w| w.bits(0)); t.ch_int().write(|w| w.int().clear_bit_by_one()); // Source/destination addresses - t.tcd_saddr().write(|w| w.saddr().bits(core::ptr::addr_of_mut!(SRC_BUFFER) as u32)); - t.tcd_daddr().write(|w| w.daddr().bits(core::ptr::addr_of_mut!(DEST_BUFFER) as u32)); + t.tcd_saddr() + .write(|w| w.saddr().bits(core::ptr::addr_of_mut!(SRC_BUFFER) as u32)); + t.tcd_daddr() + .write(|w| w.daddr().bits(core::ptr::addr_of_mut!(DEST_BUFFER) as u32)); // Custom offsets for interleaving - t.tcd_soff().write(|w| w.soff().bits(4)); // src: +4 bytes per read - t.tcd_doff().write(|w| w.doff().bits(8)); // dst: +8 bytes per write + t.tcd_soff().write(|w| w.soff().bits(4)); // src: +4 bytes per read + t.tcd_doff().write(|w| w.doff().bits(8)); // dst: +8 bytes per write // Attributes: 32-bit transfers (size = 2) t.tcd_attr().write(|w| w.ssize().bits(2).dsize().bits(2)); @@ -153,7 +159,8 @@ async fn main(_spawner: Spawner) { t.tcd_slast_sda().write(|w| w.slast_sda().bits(-(nbytes as i32) as u32)); // Destination uses 2x offset, so adjust accordingly let dst_total = (HALF_BUFF_LENGTH * 8) as u32; - t.tcd_dlast_sga().write(|w| w.dlast_sga().bits(-(dst_total as i32) as u32)); + t.tcd_dlast_sga() + .write(|w| w.dlast_sga().bits(-(dst_total as i32) as u32)); // Major loop count = 1 t.tcd_biter_elinkno().write(|w| w.biter().bits(1)); @@ -172,7 +179,9 @@ async fn main(_spawner: Spawner) { while !dma_ch0.is_done() { cortex_m::asm::nop(); } - unsafe { dma_ch0.clear_done(); } + unsafe { + dma_ch0.clear_done(); + } tx.blocking_write(b"\r\nEDMA interleave transfer example finish.\r\n\r\n") .unwrap(); @@ -206,4 +215,3 @@ async fn main(_spawner: Spawner) { cortex_m::asm::wfe(); } } - diff --git a/examples/src/bin/dma_mem_to_mem.rs b/examples/src/bin/dma_mem_to_mem.rs index 01e5edb1e..72916384f 100644 --- a/examples/src/bin/dma_mem_to_mem.rs +++ b/examples/src/bin/dma_mem_to_mem.rs @@ -15,10 +15,9 @@ use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::dma::{DmaChannel, DmaCh0InterruptHandler, TransferOptions}; -use embassy_mcxa::bind_interrupts; +use embassy_mcxa::dma::{DmaCh0InterruptHandler, DmaChannel, TransferOptions}; use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx}; -use embassy_mcxa::pac; +use embassy_mcxa::{bind_interrupts, pac}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Bind DMA channel 0 interrupt using Embassy-style macro @@ -147,8 +146,7 @@ async fn main(_spawner: Spawner) { transfer.await; } - tx.blocking_write(b"DMA mem-to-mem transfer complete!\r\n\r\n") - .unwrap(); + tx.blocking_write(b"DMA mem-to-mem transfer complete!\r\n\r\n").unwrap(); tx.blocking_write(b"Destination Buffer (after): ").unwrap(); print_buffer(&mut tx, &raw const DEST_BUFFER); tx.blocking_write(b"\r\n").unwrap(); @@ -181,7 +179,8 @@ async fn main(_spawner: Spawner) { // - Incrementing destination address // - Uses the same Transfer future pattern - tx.blocking_write(b"--- Demonstrating memset() feature ---\r\n\r\n").unwrap(); + tx.blocking_write(b"--- Demonstrating memset() feature ---\r\n\r\n") + .unwrap(); tx.blocking_write(b"Memset Buffer (before): ").unwrap(); print_buffer(&mut tx, &raw const MEMSET_BUFFER); @@ -230,4 +229,3 @@ async fn main(_spawner: Spawner) { cortex_m::asm::wfe(); } } - diff --git a/examples/src/bin/dma_memset.rs b/examples/src/bin/dma_memset.rs index 8a1636e57..9fbba85e9 100644 --- a/examples/src/bin/dma_memset.rs +++ b/examples/src/bin/dma_memset.rs @@ -12,10 +12,9 @@ use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::dma::{DmaChannel, DmaCh0InterruptHandler}; -use embassy_mcxa::bind_interrupts; +use embassy_mcxa::dma::{DmaCh0InterruptHandler, DmaChannel}; use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx}; -use embassy_mcxa::pac; +use embassy_mcxa::{bind_interrupts, pac}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Bind DMA channel 0 interrupt using Embassy-style macro @@ -92,8 +91,7 @@ async fn main(_spawner: Spawner) { let lpuart = Lpuart::new_blocking(p.LPUART2, p.P2_2, p.P2_3, config).unwrap(); let (mut tx, _rx) = lpuart.split(); - tx.blocking_write(b"EDMA memset example begin.\r\n\r\n") - .unwrap(); + tx.blocking_write(b"EDMA memset example begin.\r\n\r\n").unwrap(); // Initialize buffers unsafe { @@ -133,19 +131,26 @@ async fn main(_spawner: Spawner) { // Reset channel state t.ch_csr().write(|w| { - w.erq().disable() - .earq().disable() - .eei().no_error() - .ebw().disable() - .done().clear_bit_by_one() + w.erq() + .disable() + .earq() + .disable() + .eei() + .no_error() + .ebw() + .disable() + .done() + .clear_bit_by_one() }); t.ch_es().write(|w| w.bits(0)); t.ch_int().write(|w| w.int().clear_bit_by_one()); // Source address (pattern) - fixed - t.tcd_saddr().write(|w| w.saddr().bits(core::ptr::addr_of_mut!(PATTERN) as u32)); + t.tcd_saddr() + .write(|w| w.saddr().bits(core::ptr::addr_of_mut!(PATTERN) as u32)); // Destination address - increments - t.tcd_daddr().write(|w| w.daddr().bits(core::ptr::addr_of_mut!(DEST_BUFFER) as u32)); + t.tcd_daddr() + .write(|w| w.daddr().bits(core::ptr::addr_of_mut!(DEST_BUFFER) as u32)); // Source offset = 0 (stays fixed), Dest offset = 4 (increments) t.tcd_soff().write(|w| w.soff().bits(0)); @@ -180,10 +185,11 @@ async fn main(_spawner: Spawner) { while !dma_ch0.is_done() { cortex_m::asm::nop(); } - unsafe { dma_ch0.clear_done(); } + unsafe { + dma_ch0.clear_done(); + } - tx.blocking_write(b"\r\nEDMA memset example finish.\r\n\r\n") - .unwrap(); + tx.blocking_write(b"\r\nEDMA memset example finish.\r\n\r\n").unwrap(); tx.blocking_write(b"Destination Buffer (after): ").unwrap(); print_buffer(&mut tx, core::ptr::addr_of!(DEST_BUFFER) as *const u32, BUFFER_LENGTH); tx.blocking_write(b"\r\n\r\n").unwrap(); @@ -212,4 +218,3 @@ async fn main(_spawner: Spawner) { cortex_m::asm::wfe(); } } - diff --git a/examples/src/bin/dma_ping_pong_transfer.rs b/examples/src/bin/dma_ping_pong_transfer.rs index d765ea575..692515441 100644 --- a/examples/src/bin/dma_ping_pong_transfer.rs +++ b/examples/src/bin/dma_ping_pong_transfer.rs @@ -24,12 +24,12 @@ #![no_main] use core::sync::atomic::{AtomicBool, Ordering}; + use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::dma::{self, DmaChannel, DmaCh1InterruptHandler, Tcd, TransferOptions}; -use embassy_mcxa::bind_interrupts; +use embassy_mcxa::dma::{self, DmaCh1InterruptHandler, DmaChannel, Tcd, TransferOptions}; use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx}; -use embassy_mcxa::pac; +use embassy_mcxa::{bind_interrupts, pac}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Source and destination buffers for Approach 1 (scatter/gather) @@ -44,19 +44,21 @@ static mut DST2: [u32; 8] = [0; 8]; #[repr(C, align(32))] struct TcdPool([Tcd; 2]); -static mut TCD_POOL: TcdPool = TcdPool([Tcd { - saddr: 0, - soff: 0, - attr: 0, - nbytes: 0, - slast: 0, - daddr: 0, - doff: 0, - citer: 0, - dlast_sga: 0, - csr: 0, - biter: 0, -}; 2]); +static mut TCD_POOL: TcdPool = TcdPool( + [Tcd { + saddr: 0, + soff: 0, + attr: 0, + nbytes: 0, + slast: 0, + daddr: 0, + doff: 0, + citer: 0, + dlast_sga: 0, + csr: 0, + biter: 0, + }; 2], +); // AtomicBool to track scatter/gather completion // Note: With ESG=1, DONE bit is cleared by hardware when next TCD loads, @@ -289,7 +291,8 @@ async fn main(_spawner: Spawner) { // - True async/await support // - Good for streaming data processing - tx.blocking_write(b"--- Approach 2: wait_half() demo ---\r\n\r\n").unwrap(); + tx.blocking_write(b"--- Approach 2: wait_half() demo ---\r\n\r\n") + .unwrap(); // Enable DMA CH1 interrupt unsafe { @@ -310,10 +313,11 @@ async fn main(_spawner: Spawner) { // Configure transfer with half-transfer interrupt enabled let mut options = TransferOptions::default(); - options.half_transfer_interrupt = true; // Enable half-transfer interrupt + options.half_transfer_interrupt = true; // Enable half-transfer interrupt options.complete_transfer_interrupt = true; - tx.blocking_write(b"Starting transfer with half_transfer_interrupt...\r\n").unwrap(); + tx.blocking_write(b"Starting transfer with half_transfer_interrupt...\r\n") + .unwrap(); unsafe { let src = &*core::ptr::addr_of!(SRC2); @@ -327,10 +331,12 @@ async fn main(_spawner: Spawner) { let half_ok = transfer.wait_half().await; if half_ok { - tx.blocking_write(b"Half-transfer complete! First half of DST2: ").unwrap(); + tx.blocking_write(b"Half-transfer complete! First half of DST2: ") + .unwrap(); print_buffer(&mut tx, core::ptr::addr_of!(DST2) as *const u32, 4); tx.blocking_write(b"\r\n").unwrap(); - tx.blocking_write(b"(Processing first half while second half transfers...)\r\n").unwrap(); + tx.blocking_write(b"(Processing first half while second half transfers...)\r\n") + .unwrap(); } // Wait for complete transfer @@ -363,10 +369,10 @@ async fn main(_spawner: Spawner) { defmt::info!("PASS: Approach 2 verified."); } - tx.blocking_write(b"\r\n=== All ping-pong demos complete ===\r\n").unwrap(); + tx.blocking_write(b"\r\n=== All ping-pong demos complete ===\r\n") + .unwrap(); loop { cortex_m::asm::wfe(); } } - diff --git a/examples/src/bin/dma_scatter_gather.rs b/examples/src/bin/dma_scatter_gather.rs index d78605acc..b5ae00057 100644 --- a/examples/src/bin/dma_scatter_gather.rs +++ b/examples/src/bin/dma_scatter_gather.rs @@ -13,12 +13,12 @@ #![no_main] use core::sync::atomic::{AtomicBool, Ordering}; + use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; use embassy_mcxa::dma::{self, DmaChannel, Tcd}; -use embassy_mcxa::bind_interrupts; use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx}; -use embassy_mcxa::pac; +use embassy_mcxa::{bind_interrupts, pac}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Source and destination buffers @@ -29,19 +29,21 @@ static mut DST: [u32; 8] = [0; 8]; #[repr(C, align(32))] struct TcdPool([Tcd; 2]); -static mut TCD_POOL: TcdPool = TcdPool([Tcd { - saddr: 0, - soff: 0, - attr: 0, - nbytes: 0, - slast: 0, - daddr: 0, - doff: 0, - citer: 0, - dlast_sga: 0, - csr: 0, - biter: 0, -}; 2]); +static mut TCD_POOL: TcdPool = TcdPool( + [Tcd { + saddr: 0, + soff: 0, + attr: 0, + nbytes: 0, + slast: 0, + daddr: 0, + doff: 0, + citer: 0, + dlast_sga: 0, + csr: 0, + biter: 0, + }; 2], +); // AtomicBool to track scatter/gather completion // Note: With ESG=1, DONE bit is cleared by hardware when next TCD loads, @@ -53,7 +55,9 @@ static TRANSFER_DONE: AtomicBool = AtomicBool::new(false); // (delegates to HAL + sets a flag) and the main task does the actual processing pub struct ScatterGatherDmaHandler; -impl embassy_mcxa::interrupt::typelevel::Handler for ScatterGatherDmaHandler { +impl embassy_mcxa::interrupt::typelevel::Handler + for ScatterGatherDmaHandler +{ unsafe fn on_interrupt() { // Delegate to HAL's on_interrupt() which clears INT flag and wakes wakers dma::on_interrupt(0); @@ -161,10 +165,7 @@ async fn main(_spawner: Spawner) { // TCD0 transfers first half (SRC[0..4] -> DST[0..4]), then loads TCD1. // TCD1 transfers second half (SRC[4..8] -> DST[4..8]), last TCD. unsafe { - let tcds = core::slice::from_raw_parts_mut( - core::ptr::addr_of_mut!(TCD_POOL.0) as *mut Tcd, - 2, - ); + let tcds = core::slice::from_raw_parts_mut(core::ptr::addr_of_mut!(TCD_POOL.0) as *mut Tcd, 2); let src_ptr = core::ptr::addr_of!(SRC) as *const u32; let dst_ptr = core::ptr::addr_of_mut!(DST) as *mut u32; @@ -262,4 +263,3 @@ async fn main(_spawner: Spawner) { cortex_m::asm::wfe(); } } - diff --git a/examples/src/bin/dma_scatter_gather_builder.rs b/examples/src/bin/dma_scatter_gather_builder.rs index 51bfbeb67..d42ff841e 100644 --- a/examples/src/bin/dma_scatter_gather_builder.rs +++ b/examples/src/bin/dma_scatter_gather_builder.rs @@ -22,10 +22,9 @@ use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::dma::{DmaChannel, DmaCh0InterruptHandler, ScatterGatherBuilder}; -use embassy_mcxa::bind_interrupts; +use embassy_mcxa::dma::{DmaCh0InterruptHandler, DmaChannel, ScatterGatherBuilder}; use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx}; -use embassy_mcxa::pac; +use embassy_mcxa::{bind_interrupts, pac}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Bind DMA channel 0 interrupt @@ -97,7 +96,8 @@ async fn main(_spawner: Spawner) { let (mut tx, _rx) = lpuart.split(); tx.blocking_write(b"DMA Scatter-Gather Builder Example\r\n").unwrap(); - tx.blocking_write(b"===================================\r\n\r\n").unwrap(); + tx.blocking_write(b"===================================\r\n\r\n") + .unwrap(); // Show source buffers tx.blocking_write(b"Source buffers:\r\n").unwrap(); @@ -125,7 +125,8 @@ async fn main(_spawner: Spawner) { // Create DMA channel let dma_ch0 = DmaChannel::new(p.DMA_CH0); - tx.blocking_write(b"Building scatter-gather chain with builder API...\r\n").unwrap(); + tx.blocking_write(b"Building scatter-gather chain with builder API...\r\n") + .unwrap(); // ========================================================================= // ScatterGatherBuilder API demonstration @@ -159,7 +160,8 @@ async fn main(_spawner: Spawner) { } tx.blocking_write(b"Added 3 transfer segments to chain.\r\n").unwrap(); - tx.blocking_write(b"Starting scatter-gather transfer with .await...\r\n\r\n").unwrap(); + tx.blocking_write(b"Starting scatter-gather transfer with .await...\r\n\r\n") + .unwrap(); // Build and execute the scatter-gather chain // The build() method: @@ -222,7 +224,8 @@ async fn main(_spawner: Spawner) { defmt::error!("FAIL: Mismatch detected!"); } - tx.blocking_write(b"\r\n=== Scatter-Gather Builder example complete ===\r\n").unwrap(); + tx.blocking_write(b"\r\n=== Scatter-Gather Builder example complete ===\r\n") + .unwrap(); loop { cortex_m::asm::wfe(); diff --git a/examples/src/bin/dma_wrap_transfer.rs b/examples/src/bin/dma_wrap_transfer.rs index 8e9aedbfb..0babf4c20 100644 --- a/examples/src/bin/dma_wrap_transfer.rs +++ b/examples/src/bin/dma_wrap_transfer.rs @@ -12,10 +12,9 @@ use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::dma::{DmaChannel, DmaCh0InterruptHandler}; -use embassy_mcxa::bind_interrupts; +use embassy_mcxa::dma::{DmaCh0InterruptHandler, DmaChannel}; use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx}; -use embassy_mcxa::pac; +use embassy_mcxa::{bind_interrupts, pac}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Bind DMA channel 0 interrupt using Embassy-style macro @@ -93,8 +92,7 @@ async fn main(_spawner: Spawner) { let lpuart = Lpuart::new_blocking(p.LPUART2, p.P2_2, p.P2_3, config).unwrap(); let (mut tx, _rx) = lpuart.split(); - tx.blocking_write(b"EDMA wrap transfer example begin.\r\n\r\n") - .unwrap(); + tx.blocking_write(b"EDMA wrap transfer example begin.\r\n\r\n").unwrap(); // Initialize buffers unsafe { @@ -127,18 +125,25 @@ async fn main(_spawner: Spawner) { // Reset channel state t.ch_csr().write(|w| { - w.erq().disable() - .earq().disable() - .eei().no_error() - .ebw().disable() - .done().clear_bit_by_one() + w.erq() + .disable() + .earq() + .disable() + .eei() + .no_error() + .ebw() + .disable() + .done() + .clear_bit_by_one() }); t.ch_es().write(|w| w.bits(0)); t.ch_int().write(|w| w.int().clear_bit_by_one()); // Source/destination addresses - t.tcd_saddr().write(|w| w.saddr().bits(core::ptr::addr_of!(SRC.0) as u32)); - t.tcd_daddr().write(|w| w.daddr().bits(core::ptr::addr_of_mut!(DST) as u32)); + t.tcd_saddr() + .write(|w| w.saddr().bits(core::ptr::addr_of!(SRC.0) as u32)); + t.tcd_daddr() + .write(|w| w.daddr().bits(core::ptr::addr_of_mut!(DST) as u32)); // Offsets: both increment by 4 bytes t.tcd_soff().write(|w| w.soff().bits(4)); @@ -147,10 +152,14 @@ async fn main(_spawner: Spawner) { // Attributes: 32-bit transfers (size = 2) // SMOD = 4 (2^4 = 16 byte modulo for source), DMOD = 0 (disabled) t.tcd_attr().write(|w| { - w.ssize().bits(2) - .dsize().bits(2) - .smod().bits(4) // Source modulo: 2^4 = 16 bytes - .dmod().bits(0) // Dest modulo: disabled + w.ssize() + .bits(2) + .dsize() + .bits(2) + .smod() + .bits(4) // Source modulo: 2^4 = 16 bytes + .dmod() + .bits(0) // Dest modulo: disabled }); // Transfer 32 bytes total in one minor loop @@ -179,7 +188,9 @@ async fn main(_spawner: Spawner) { while !dma_ch0.is_done() { cortex_m::asm::nop(); } - unsafe { dma_ch0.clear_done(); } + unsafe { + dma_ch0.clear_done(); + } tx.blocking_write(b"\r\nEDMA wrap transfer example finish.\r\n\r\n") .unwrap(); @@ -211,4 +222,3 @@ async fn main(_spawner: Spawner) { cortex_m::asm::wfe(); } } - diff --git a/examples/src/bin/lpuart_dma.rs b/examples/src/bin/lpuart_dma.rs index 4e321b111..f4dfbcf39 100644 --- a/examples/src/bin/lpuart_dma.rs +++ b/examples/src/bin/lpuart_dma.rs @@ -48,8 +48,7 @@ async fn main(_spawner: Spawner) { // Create UART instance with DMA channels let mut lpuart = LpuartDma::new( - p.LPUART2, - p.P2_2, // TX pin + p.LPUART2, p.P2_2, // TX pin p.P2_3, // RX pin p.DMA_CH0, // TX DMA channel p.DMA_CH1, // RX DMA channel @@ -82,4 +81,3 @@ async fn main(_spawner: Spawner) { defmt::info!("Example complete"); } - diff --git a/examples/src/bin/lpuart_ring_buffer.rs b/examples/src/bin/lpuart_ring_buffer.rs index d71876ade..6cc14f1c7 100644 --- a/examples/src/bin/lpuart_ring_buffer.rs +++ b/examples/src/bin/lpuart_ring_buffer.rs @@ -20,7 +20,7 @@ use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::dma::{DmaChannel, DmaCh0InterruptHandler, DmaCh1InterruptHandler, DMA_REQ_LPUART2_RX}; +use embassy_mcxa::dma::{DmaCh0InterruptHandler, DmaCh1InterruptHandler, DmaChannel, DMA_REQ_LPUART2_RX}; use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx}; use embassy_mcxa::{bind_interrupts, pac}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; @@ -91,7 +91,8 @@ async fn main(_spawner: Spawner) { dma_ch_rx.set_request_source(DMA_REQ_LPUART2_RX); } - tx.blocking_write(b"Setting up circular DMA for UART RX...\r\n").unwrap(); + tx.blocking_write(b"Setting up circular DMA for UART RX...\r\n") + .unwrap(); // Set up the ring buffer with circular DMA // This configures the DMA for continuous reception @@ -105,8 +106,10 @@ async fn main(_spawner: Spawner) { dma_ch_rx.enable_request(); } - tx.blocking_write(b"Ring buffer ready! Type characters to see them echoed.\r\n").unwrap(); - tx.blocking_write(b"The DMA continuously receives in the background.\r\n\r\n").unwrap(); + tx.blocking_write(b"Ring buffer ready! Type characters to see them echoed.\r\n") + .unwrap(); + tx.blocking_write(b"The DMA continuously receives in the background.\r\n\r\n") + .unwrap(); // Main loop: read from ring buffer and echo back let mut read_buf = [0u8; 16]; @@ -144,4 +147,3 @@ async fn main(_spawner: Spawner) { } } } - diff --git a/src/dma.rs b/src/dma.rs index 66b610d93..7bfc95752 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -107,12 +107,13 @@ use core::ptr::NonNull; use core::sync::atomic::{fence, AtomicBool, AtomicUsize, Ordering}; use core::task::{Context, Poll}; +use embassy_hal_internal::PeripheralType; +use embassy_sync::waitqueue::AtomicWaker; + use crate::clocks::Gate; use crate::pac; use crate::pac::Interrupt; use crate::peripherals::DMA0; -use embassy_hal_internal::PeripheralType; -use embassy_sync::waitqueue::AtomicWaker; /// Static flag to track whether DMA has been initialized. static DMA_INITIALIZED: AtomicBool = AtomicBool::new(false); -- cgit