From 23ca2f9174b170c6f6cfc7bab708c4ac7cc4a247 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Thu, 6 May 2021 03:43:46 +0200 Subject: Autogenerate the tailored PAC for each chip --- .vscode/settings.json | 13 - embassy-stm32/Cargo.toml | 581 ++-- embassy-stm32/build.rs | 4 +- embassy-stm32/gen.py | 198 +- embassy-stm32/src/chip/mod.rs | 292 -- embassy-stm32/src/chip/stm32f401cb.rs | 466 --- embassy-stm32/src/chip/stm32f401cc.rs | 466 --- embassy-stm32/src/chip/stm32f401cd.rs | 466 --- embassy-stm32/src/chip/stm32f401ce.rs | 466 --- embassy-stm32/src/chip/stm32f401rb.rs | 466 --- embassy-stm32/src/chip/stm32f401rc.rs | 466 --- embassy-stm32/src/chip/stm32f401rd.rs | 466 --- embassy-stm32/src/chip/stm32f401re.rs | 466 --- embassy-stm32/src/chip/stm32f401vb.rs | 466 --- embassy-stm32/src/chip/stm32f401vc.rs | 466 --- embassy-stm32/src/chip/stm32f401vd.rs | 466 --- embassy-stm32/src/chip/stm32f401ve.rs | 466 --- embassy-stm32/src/chip/stm32f405oe.rs | 613 ---- embassy-stm32/src/chip/stm32f405og.rs | 613 ---- embassy-stm32/src/chip/stm32f405rg.rs | 613 ---- embassy-stm32/src/chip/stm32f405vg.rs | 613 ---- embassy-stm32/src/chip/stm32f405zg.rs | 613 ---- embassy-stm32/src/chip/stm32f407ie.rs | 622 ---- embassy-stm32/src/chip/stm32f407ig.rs | 622 ---- embassy-stm32/src/chip/stm32f407ve.rs | 622 ---- embassy-stm32/src/chip/stm32f407vg.rs | 622 ---- embassy-stm32/src/chip/stm32f407ze.rs | 622 ---- embassy-stm32/src/chip/stm32f407zg.rs | 622 ---- embassy-stm32/src/chip/stm32f410c8.rs | 431 --- embassy-stm32/src/chip/stm32f410cb.rs | 431 --- embassy-stm32/src/chip/stm32f410r8.rs | 431 --- embassy-stm32/src/chip/stm32f410rb.rs | 431 --- embassy-stm32/src/chip/stm32f410t8.rs | 416 --- embassy-stm32/src/chip/stm32f410tb.rs | 416 --- embassy-stm32/src/chip/stm32f411cc.rs | 472 --- embassy-stm32/src/chip/stm32f411ce.rs | 472 --- embassy-stm32/src/chip/stm32f411rc.rs | 472 --- embassy-stm32/src/chip/stm32f411re.rs | 472 --- embassy-stm32/src/chip/stm32f411vc.rs | 472 --- embassy-stm32/src/chip/stm32f411ve.rs | 472 --- embassy-stm32/src/chip/stm32f412ce.rs | 530 ---- embassy-stm32/src/chip/stm32f412cg.rs | 530 ---- embassy-stm32/src/chip/stm32f412re.rs | 560 ---- embassy-stm32/src/chip/stm32f412rg.rs | 560 ---- embassy-stm32/src/chip/stm32f412ve.rs | 618 ---- embassy-stm32/src/chip/stm32f412vg.rs | 618 ---- embassy-stm32/src/chip/stm32f412ze.rs | 618 ---- embassy-stm32/src/chip/stm32f412zg.rs | 618 ---- embassy-stm32/src/chip/stm32f413cg.rs | 664 ---- embassy-stm32/src/chip/stm32f413ch.rs | 664 ---- embassy-stm32/src/chip/stm32f413mg.rs | 679 ---- embassy-stm32/src/chip/stm32f413mh.rs | 679 ---- embassy-stm32/src/chip/stm32f413rg.rs | 679 ---- embassy-stm32/src/chip/stm32f413rh.rs | 679 ---- embassy-stm32/src/chip/stm32f413vg.rs | 680 ---- embassy-stm32/src/chip/stm32f413vh.rs | 680 ---- embassy-stm32/src/chip/stm32f413zg.rs | 680 ---- embassy-stm32/src/chip/stm32f413zh.rs | 680 ---- embassy-stm32/src/chip/stm32f415og.rs | 616 ---- embassy-stm32/src/chip/stm32f415rg.rs | 616 ---- embassy-stm32/src/chip/stm32f415vg.rs | 616 ---- embassy-stm32/src/chip/stm32f415zg.rs | 616 ---- embassy-stm32/src/chip/stm32f417ie.rs | 625 ---- embassy-stm32/src/chip/stm32f417ig.rs | 625 ---- embassy-stm32/src/chip/stm32f417ve.rs | 625 ---- embassy-stm32/src/chip/stm32f417vg.rs | 625 ---- embassy-stm32/src/chip/stm32f417ze.rs | 625 ---- embassy-stm32/src/chip/stm32f417zg.rs | 625 ---- embassy-stm32/src/chip/stm32f423ch.rs | 667 ---- embassy-stm32/src/chip/stm32f423mh.rs | 682 ---- embassy-stm32/src/chip/stm32f423rh.rs | 682 ---- embassy-stm32/src/chip/stm32f423vh.rs | 683 ---- embassy-stm32/src/chip/stm32f423zh.rs | 683 ---- embassy-stm32/src/chip/stm32f427ag.rs | 686 ---- embassy-stm32/src/chip/stm32f427ai.rs | 686 ---- embassy-stm32/src/chip/stm32f427ig.rs | 686 ---- embassy-stm32/src/chip/stm32f427ii.rs | 686 ---- embassy-stm32/src/chip/stm32f427vg.rs | 686 ---- embassy-stm32/src/chip/stm32f427vi.rs | 686 ---- embassy-stm32/src/chip/stm32f427zg.rs | 686 ---- embassy-stm32/src/chip/stm32f427zi.rs | 686 ---- embassy-stm32/src/chip/stm32f429ag.rs | 692 ----- embassy-stm32/src/chip/stm32f429ai.rs | 692 ----- embassy-stm32/src/chip/stm32f429be.rs | 692 ----- embassy-stm32/src/chip/stm32f429bg.rs | 692 ----- embassy-stm32/src/chip/stm32f429bi.rs | 692 ----- embassy-stm32/src/chip/stm32f429ie.rs | 692 ----- embassy-stm32/src/chip/stm32f429ig.rs | 692 ----- embassy-stm32/src/chip/stm32f429ii.rs | 692 ----- embassy-stm32/src/chip/stm32f429ne.rs | 692 ----- embassy-stm32/src/chip/stm32f429ng.rs | 692 ----- embassy-stm32/src/chip/stm32f429ni.rs | 692 ----- embassy-stm32/src/chip/stm32f429ve.rs | 692 ----- embassy-stm32/src/chip/stm32f429vg.rs | 692 ----- embassy-stm32/src/chip/stm32f429vi.rs | 692 ----- embassy-stm32/src/chip/stm32f429ze.rs | 692 ----- embassy-stm32/src/chip/stm32f429zg.rs | 692 ----- embassy-stm32/src/chip/stm32f429zi.rs | 692 ----- embassy-stm32/src/chip/stm32f437ai.rs | 689 ---- embassy-stm32/src/chip/stm32f437ig.rs | 690 ----- embassy-stm32/src/chip/stm32f437ii.rs | 690 ----- embassy-stm32/src/chip/stm32f437vg.rs | 689 ---- embassy-stm32/src/chip/stm32f437vi.rs | 689 ---- embassy-stm32/src/chip/stm32f437zg.rs | 690 ----- embassy-stm32/src/chip/stm32f437zi.rs | 690 ----- embassy-stm32/src/chip/stm32f439ai.rs | 696 ----- embassy-stm32/src/chip/stm32f439bg.rs | 696 ----- embassy-stm32/src/chip/stm32f439bi.rs | 696 ----- embassy-stm32/src/chip/stm32f439ig.rs | 696 ----- embassy-stm32/src/chip/stm32f439ii.rs | 696 ----- embassy-stm32/src/chip/stm32f439ng.rs | 696 ----- embassy-stm32/src/chip/stm32f439ni.rs | 696 ----- embassy-stm32/src/chip/stm32f439vg.rs | 695 ----- embassy-stm32/src/chip/stm32f439vi.rs | 695 ----- embassy-stm32/src/chip/stm32f439zg.rs | 696 ----- embassy-stm32/src/chip/stm32f439zi.rs | 696 ----- embassy-stm32/src/chip/stm32f446mc.rs | 640 ---- embassy-stm32/src/chip/stm32f446me.rs | 640 ---- embassy-stm32/src/chip/stm32f446rc.rs | 639 ---- embassy-stm32/src/chip/stm32f446re.rs | 639 ---- embassy-stm32/src/chip/stm32f446vc.rs | 640 ---- embassy-stm32/src/chip/stm32f446ve.rs | 640 ---- embassy-stm32/src/chip/stm32f446zc.rs | 640 ---- embassy-stm32/src/chip/stm32f446ze.rs | 640 ---- embassy-stm32/src/chip/stm32f469ae.rs | 700 ----- embassy-stm32/src/chip/stm32f469ag.rs | 700 ----- embassy-stm32/src/chip/stm32f469ai.rs | 700 ----- embassy-stm32/src/chip/stm32f469be.rs | 701 ----- embassy-stm32/src/chip/stm32f469bg.rs | 701 ----- embassy-stm32/src/chip/stm32f469bi.rs | 701 ----- embassy-stm32/src/chip/stm32f469ie.rs | 701 ----- embassy-stm32/src/chip/stm32f469ig.rs | 701 ----- embassy-stm32/src/chip/stm32f469ii.rs | 701 ----- embassy-stm32/src/chip/stm32f469ne.rs | 701 ----- embassy-stm32/src/chip/stm32f469ng.rs | 701 ----- embassy-stm32/src/chip/stm32f469ni.rs | 701 ----- embassy-stm32/src/chip/stm32f469ve.rs | 700 ----- embassy-stm32/src/chip/stm32f469vg.rs | 700 ----- embassy-stm32/src/chip/stm32f469vi.rs | 700 ----- embassy-stm32/src/chip/stm32f469ze.rs | 700 ----- embassy-stm32/src/chip/stm32f469zg.rs | 700 ----- embassy-stm32/src/chip/stm32f469zi.rs | 700 ----- embassy-stm32/src/chip/stm32f479ag.rs | 704 ----- embassy-stm32/src/chip/stm32f479ai.rs | 704 ----- embassy-stm32/src/chip/stm32f479bg.rs | 704 ----- embassy-stm32/src/chip/stm32f479bi.rs | 704 ----- embassy-stm32/src/chip/stm32f479ig.rs | 704 ----- embassy-stm32/src/chip/stm32f479ii.rs | 704 ----- embassy-stm32/src/chip/stm32f479ng.rs | 704 ----- embassy-stm32/src/chip/stm32f479ni.rs | 704 ----- embassy-stm32/src/chip/stm32f479vg.rs | 703 ----- embassy-stm32/src/chip/stm32f479vi.rs | 703 ----- embassy-stm32/src/chip/stm32f479zg.rs | 703 ----- embassy-stm32/src/chip/stm32f479zi.rs | 703 ----- embassy-stm32/src/chip/stm32l412c8.rs | 418 --- embassy-stm32/src/chip/stm32l412cb.rs | 418 --- embassy-stm32/src/chip/stm32l412k8.rs | 417 --- embassy-stm32/src/chip/stm32l412kb.rs | 417 --- embassy-stm32/src/chip/stm32l412r8.rs | 418 --- embassy-stm32/src/chip/stm32l412rb.rs | 418 --- embassy-stm32/src/chip/stm32l412t8.rs | 417 --- embassy-stm32/src/chip/stm32l412tb.rs | 417 --- embassy-stm32/src/chip/stm32l422cb.rs | 421 --- embassy-stm32/src/chip/stm32l422kb.rs | 420 --- embassy-stm32/src/chip/stm32l422rb.rs | 421 --- embassy-stm32/src/chip/stm32l422tb.rs | 420 --- embassy-stm32/src/chip/stm32l431cb.rs | 459 --- embassy-stm32/src/chip/stm32l431cc.rs | 459 --- embassy-stm32/src/chip/stm32l431kb.rs | 459 --- embassy-stm32/src/chip/stm32l431kc.rs | 459 --- embassy-stm32/src/chip/stm32l431rb.rs | 459 --- embassy-stm32/src/chip/stm32l431rc.rs | 459 --- embassy-stm32/src/chip/stm32l431vc.rs | 459 --- embassy-stm32/src/chip/stm32l432kb.rs | 413 --- embassy-stm32/src/chip/stm32l432kc.rs | 413 --- embassy-stm32/src/chip/stm32l433cb.rs | 465 --- embassy-stm32/src/chip/stm32l433cc.rs | 465 --- embassy-stm32/src/chip/stm32l433rb.rs | 465 --- embassy-stm32/src/chip/stm32l433rc.rs | 465 --- embassy-stm32/src/chip/stm32l433vc.rs | 465 --- embassy-stm32/src/chip/stm32l442kc.rs | 416 --- embassy-stm32/src/chip/stm32l443cc.rs | 468 --- embassy-stm32/src/chip/stm32l443rc.rs | 468 --- embassy-stm32/src/chip/stm32l443vc.rs | 468 --- embassy-stm32/src/chip/stm32l451cc.rs | 477 --- embassy-stm32/src/chip/stm32l451ce.rs | 477 --- embassy-stm32/src/chip/stm32l451rc.rs | 477 --- embassy-stm32/src/chip/stm32l451re.rs | 477 --- embassy-stm32/src/chip/stm32l451vc.rs | 477 --- embassy-stm32/src/chip/stm32l451ve.rs | 477 --- embassy-stm32/src/chip/stm32l452cc.rs | 480 --- embassy-stm32/src/chip/stm32l452ce.rs | 480 --- embassy-stm32/src/chip/stm32l452rc.rs | 480 --- embassy-stm32/src/chip/stm32l452re.rs | 480 --- embassy-stm32/src/chip/stm32l452vc.rs | 480 --- embassy-stm32/src/chip/stm32l452ve.rs | 480 --- embassy-stm32/src/chip/stm32l462ce.rs | 483 --- embassy-stm32/src/chip/stm32l462re.rs | 483 --- embassy-stm32/src/chip/stm32l462ve.rs | 483 --- embassy-stm32/src/chip/stm32l471qe.rs | 547 ---- embassy-stm32/src/chip/stm32l471qg.rs | 547 ---- embassy-stm32/src/chip/stm32l471re.rs | 547 ---- embassy-stm32/src/chip/stm32l471rg.rs | 547 ---- embassy-stm32/src/chip/stm32l471ve.rs | 547 ---- embassy-stm32/src/chip/stm32l471vg.rs | 547 ---- embassy-stm32/src/chip/stm32l471ze.rs | 547 ---- embassy-stm32/src/chip/stm32l471zg.rs | 547 ---- embassy-stm32/src/chip/stm32l475rc.rs | 551 ---- embassy-stm32/src/chip/stm32l475re.rs | 551 ---- embassy-stm32/src/chip/stm32l475rg.rs | 551 ---- embassy-stm32/src/chip/stm32l475vc.rs | 551 ---- embassy-stm32/src/chip/stm32l475ve.rs | 551 ---- embassy-stm32/src/chip/stm32l475vg.rs | 551 ---- embassy-stm32/src/chip/stm32l476je.rs | 554 ---- embassy-stm32/src/chip/stm32l476jg.rs | 554 ---- embassy-stm32/src/chip/stm32l476me.rs | 554 ---- embassy-stm32/src/chip/stm32l476mg.rs | 554 ---- embassy-stm32/src/chip/stm32l476qe.rs | 554 ---- embassy-stm32/src/chip/stm32l476qg.rs | 554 ---- embassy-stm32/src/chip/stm32l476rc.rs | 554 ---- embassy-stm32/src/chip/stm32l476re.rs | 554 ---- embassy-stm32/src/chip/stm32l476rg.rs | 554 ---- embassy-stm32/src/chip/stm32l476vc.rs | 554 ---- embassy-stm32/src/chip/stm32l476ve.rs | 554 ---- embassy-stm32/src/chip/stm32l476vg.rs | 554 ---- embassy-stm32/src/chip/stm32l476ze.rs | 554 ---- embassy-stm32/src/chip/stm32l476zg.rs | 554 ---- embassy-stm32/src/chip/stm32l485jc.rs | 554 ---- embassy-stm32/src/chip/stm32l485je.rs | 554 ---- embassy-stm32/src/chip/stm32l486jg.rs | 557 ---- embassy-stm32/src/chip/stm32l486qg.rs | 557 ---- embassy-stm32/src/chip/stm32l486rg.rs | 557 ---- embassy-stm32/src/chip/stm32l486vg.rs | 557 ---- embassy-stm32/src/chip/stm32l486zg.rs | 557 ---- embassy-stm32/src/chip/stm32l496ae.rs | 607 ---- embassy-stm32/src/chip/stm32l496ag.rs | 607 ---- embassy-stm32/src/chip/stm32l496qe.rs | 607 ---- embassy-stm32/src/chip/stm32l496qg.rs | 607 ---- embassy-stm32/src/chip/stm32l496re.rs | 607 ---- embassy-stm32/src/chip/stm32l496rg.rs | 607 ---- embassy-stm32/src/chip/stm32l496ve.rs | 607 ---- embassy-stm32/src/chip/stm32l496vg.rs | 607 ---- embassy-stm32/src/chip/stm32l496wg.rs | 607 ---- embassy-stm32/src/chip/stm32l496ze.rs | 607 ---- embassy-stm32/src/chip/stm32l496zg.rs | 607 ---- embassy-stm32/src/chip/stm32l4a6ag.rs | 610 ---- embassy-stm32/src/chip/stm32l4a6qg.rs | 610 ---- embassy-stm32/src/chip/stm32l4a6rg.rs | 610 ---- embassy-stm32/src/chip/stm32l4a6vg.rs | 610 ---- embassy-stm32/src/chip/stm32l4a6zg.rs | 610 ---- embassy-stm32/src/chip/stm32l4p5ae.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5ag.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5ce.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5cg.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5qe.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5qg.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5re.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5rg.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5ve.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5vg.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5ze.rs | 599 ---- embassy-stm32/src/chip/stm32l4p5zg.rs | 599 ---- embassy-stm32/src/chip/stm32l4q5ag.rs | 605 ---- embassy-stm32/src/chip/stm32l4q5cg.rs | 605 ---- embassy-stm32/src/chip/stm32l4q5qg.rs | 605 ---- embassy-stm32/src/chip/stm32l4q5rg.rs | 605 ---- embassy-stm32/src/chip/stm32l4q5vg.rs | 605 ---- embassy-stm32/src/chip/stm32l4q5zg.rs | 605 ---- embassy-stm32/src/chip/stm32l4r5ag.rs | 598 ---- embassy-stm32/src/chip/stm32l4r5ai.rs | 598 ---- embassy-stm32/src/chip/stm32l4r5qg.rs | 598 ---- embassy-stm32/src/chip/stm32l4r5qi.rs | 598 ---- embassy-stm32/src/chip/stm32l4r5vg.rs | 598 ---- embassy-stm32/src/chip/stm32l4r5vi.rs | 598 ---- embassy-stm32/src/chip/stm32l4r5zg.rs | 598 ---- embassy-stm32/src/chip/stm32l4r5zi.rs | 598 ---- embassy-stm32/src/chip/stm32l4r7ai.rs | 607 ---- embassy-stm32/src/chip/stm32l4r7vi.rs | 607 ---- embassy-stm32/src/chip/stm32l4r7zi.rs | 607 ---- embassy-stm32/src/chip/stm32l4r9ag.rs | 610 ---- embassy-stm32/src/chip/stm32l4r9ai.rs | 610 ---- embassy-stm32/src/chip/stm32l4r9vg.rs | 610 ---- embassy-stm32/src/chip/stm32l4r9vi.rs | 610 ---- embassy-stm32/src/chip/stm32l4r9zg.rs | 610 ---- embassy-stm32/src/chip/stm32l4r9zi.rs | 610 ---- embassy-stm32/src/chip/stm32l4s5ai.rs | 601 ---- embassy-stm32/src/chip/stm32l4s5qi.rs | 601 ---- embassy-stm32/src/chip/stm32l4s5vi.rs | 601 ---- embassy-stm32/src/chip/stm32l4s5zi.rs | 601 ---- embassy-stm32/src/chip/stm32l4s7ai.rs | 610 ---- embassy-stm32/src/chip/stm32l4s7vi.rs | 610 ---- embassy-stm32/src/chip/stm32l4s7zi.rs | 610 ---- embassy-stm32/src/chip/stm32l4s9ai.rs | 613 ---- embassy-stm32/src/chip/stm32l4s9vi.rs | 613 ---- embassy-stm32/src/chip/stm32l4s9zi.rs | 613 ---- embassy-stm32/src/exti.rs | 4 +- embassy-stm32/src/gpio.rs | 9 +- embassy-stm32/src/lib.rs | 19 +- embassy-stm32/src/pac/mod.rs | 292 ++ embassy-stm32/src/pac/regs.rs | 5517 +++++++++++++++++++++++++++++++++ embassy-stm32/src/pac/stm32f401cb.rs | 485 +++ embassy-stm32/src/pac/stm32f401cc.rs | 485 +++ embassy-stm32/src/pac/stm32f401cd.rs | 485 +++ embassy-stm32/src/pac/stm32f401ce.rs | 485 +++ embassy-stm32/src/pac/stm32f401rb.rs | 485 +++ embassy-stm32/src/pac/stm32f401rc.rs | 485 +++ embassy-stm32/src/pac/stm32f401rd.rs | 485 +++ embassy-stm32/src/pac/stm32f401re.rs | 485 +++ embassy-stm32/src/pac/stm32f401vb.rs | 485 +++ embassy-stm32/src/pac/stm32f401vc.rs | 485 +++ embassy-stm32/src/pac/stm32f401vd.rs | 485 +++ embassy-stm32/src/pac/stm32f401ve.rs | 485 +++ embassy-stm32/src/pac/stm32f405oe.rs | 637 ++++ embassy-stm32/src/pac/stm32f405og.rs | 637 ++++ embassy-stm32/src/pac/stm32f405rg.rs | 637 ++++ embassy-stm32/src/pac/stm32f405vg.rs | 637 ++++ embassy-stm32/src/pac/stm32f405zg.rs | 637 ++++ embassy-stm32/src/pac/stm32f407ie.rs | 646 ++++ embassy-stm32/src/pac/stm32f407ig.rs | 646 ++++ embassy-stm32/src/pac/stm32f407ve.rs | 646 ++++ embassy-stm32/src/pac/stm32f407vg.rs | 646 ++++ embassy-stm32/src/pac/stm32f407ze.rs | 646 ++++ embassy-stm32/src/pac/stm32f407zg.rs | 646 ++++ embassy-stm32/src/pac/stm32f410c8.rs | 450 +++ embassy-stm32/src/pac/stm32f410cb.rs | 450 +++ embassy-stm32/src/pac/stm32f410r8.rs | 450 +++ embassy-stm32/src/pac/stm32f410rb.rs | 450 +++ embassy-stm32/src/pac/stm32f410t8.rs | 434 +++ embassy-stm32/src/pac/stm32f410tb.rs | 434 +++ embassy-stm32/src/pac/stm32f411cc.rs | 491 +++ embassy-stm32/src/pac/stm32f411ce.rs | 491 +++ embassy-stm32/src/pac/stm32f411rc.rs | 491 +++ embassy-stm32/src/pac/stm32f411re.rs | 491 +++ embassy-stm32/src/pac/stm32f411vc.rs | 491 +++ embassy-stm32/src/pac/stm32f411ve.rs | 491 +++ embassy-stm32/src/pac/stm32f412ce.rs | 549 ++++ embassy-stm32/src/pac/stm32f412cg.rs | 549 ++++ embassy-stm32/src/pac/stm32f412re.rs | 580 ++++ embassy-stm32/src/pac/stm32f412rg.rs | 580 ++++ embassy-stm32/src/pac/stm32f412ve.rs | 641 ++++ embassy-stm32/src/pac/stm32f412vg.rs | 641 ++++ embassy-stm32/src/pac/stm32f412ze.rs | 641 ++++ embassy-stm32/src/pac/stm32f412zg.rs | 641 ++++ embassy-stm32/src/pac/stm32f413cg.rs | 686 ++++ embassy-stm32/src/pac/stm32f413ch.rs | 686 ++++ embassy-stm32/src/pac/stm32f413mg.rs | 702 +++++ embassy-stm32/src/pac/stm32f413mh.rs | 702 +++++ embassy-stm32/src/pac/stm32f413rg.rs | 702 +++++ embassy-stm32/src/pac/stm32f413rh.rs | 702 +++++ embassy-stm32/src/pac/stm32f413vg.rs | 702 +++++ embassy-stm32/src/pac/stm32f413vh.rs | 702 +++++ embassy-stm32/src/pac/stm32f413zg.rs | 702 +++++ embassy-stm32/src/pac/stm32f413zh.rs | 702 +++++ embassy-stm32/src/pac/stm32f415og.rs | 640 ++++ embassy-stm32/src/pac/stm32f415rg.rs | 640 ++++ embassy-stm32/src/pac/stm32f415vg.rs | 640 ++++ embassy-stm32/src/pac/stm32f415zg.rs | 640 ++++ embassy-stm32/src/pac/stm32f417ie.rs | 649 ++++ embassy-stm32/src/pac/stm32f417ig.rs | 649 ++++ embassy-stm32/src/pac/stm32f417ve.rs | 649 ++++ embassy-stm32/src/pac/stm32f417vg.rs | 649 ++++ embassy-stm32/src/pac/stm32f417ze.rs | 649 ++++ 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embassy-stm32/src/pac/stm32f446vc.rs create mode 100644 embassy-stm32/src/pac/stm32f446ve.rs create mode 100644 embassy-stm32/src/pac/stm32f446zc.rs create mode 100644 embassy-stm32/src/pac/stm32f446ze.rs create mode 100644 embassy-stm32/src/pac/stm32f469ae.rs create mode 100644 embassy-stm32/src/pac/stm32f469ag.rs create mode 100644 embassy-stm32/src/pac/stm32f469ai.rs create mode 100644 embassy-stm32/src/pac/stm32f469be.rs create mode 100644 embassy-stm32/src/pac/stm32f469bg.rs create mode 100644 embassy-stm32/src/pac/stm32f469bi.rs create mode 100644 embassy-stm32/src/pac/stm32f469ie.rs create mode 100644 embassy-stm32/src/pac/stm32f469ig.rs create mode 100644 embassy-stm32/src/pac/stm32f469ii.rs create mode 100644 embassy-stm32/src/pac/stm32f469ne.rs create mode 100644 embassy-stm32/src/pac/stm32f469ng.rs create mode 100644 embassy-stm32/src/pac/stm32f469ni.rs create mode 100644 embassy-stm32/src/pac/stm32f469ve.rs create mode 100644 embassy-stm32/src/pac/stm32f469vg.rs create mode 100644 embassy-stm32/src/pac/stm32f469vi.rs create mode 100644 embassy-stm32/src/pac/stm32f469ze.rs create mode 100644 embassy-stm32/src/pac/stm32f469zg.rs create mode 100644 embassy-stm32/src/pac/stm32f469zi.rs create mode 100644 embassy-stm32/src/pac/stm32f479ag.rs create mode 100644 embassy-stm32/src/pac/stm32f479ai.rs create mode 100644 embassy-stm32/src/pac/stm32f479bg.rs create mode 100644 embassy-stm32/src/pac/stm32f479bi.rs create mode 100644 embassy-stm32/src/pac/stm32f479ig.rs create mode 100644 embassy-stm32/src/pac/stm32f479ii.rs create mode 100644 embassy-stm32/src/pac/stm32f479ng.rs create mode 100644 embassy-stm32/src/pac/stm32f479ni.rs create mode 100644 embassy-stm32/src/pac/stm32f479vg.rs create mode 100644 embassy-stm32/src/pac/stm32f479vi.rs create mode 100644 embassy-stm32/src/pac/stm32f479zg.rs create mode 100644 embassy-stm32/src/pac/stm32f479zi.rs create mode 100644 embassy-stm32/src/pac/stm32l412c8.rs create mode 100644 embassy-stm32/src/pac/stm32l412cb.rs create mode 100644 embassy-stm32/src/pac/stm32l412k8.rs create mode 100644 embassy-stm32/src/pac/stm32l412kb.rs create mode 100644 embassy-stm32/src/pac/stm32l412r8.rs create mode 100644 embassy-stm32/src/pac/stm32l412rb.rs create mode 100644 embassy-stm32/src/pac/stm32l412t8.rs create mode 100644 embassy-stm32/src/pac/stm32l412tb.rs create mode 100644 embassy-stm32/src/pac/stm32l422cb.rs create mode 100644 embassy-stm32/src/pac/stm32l422kb.rs create mode 100644 embassy-stm32/src/pac/stm32l422rb.rs create mode 100644 embassy-stm32/src/pac/stm32l422tb.rs create mode 100644 embassy-stm32/src/pac/stm32l431cb.rs create mode 100644 embassy-stm32/src/pac/stm32l431cc.rs create mode 100644 embassy-stm32/src/pac/stm32l431kb.rs create mode 100644 embassy-stm32/src/pac/stm32l431kc.rs create mode 100644 embassy-stm32/src/pac/stm32l431rb.rs create mode 100644 embassy-stm32/src/pac/stm32l431rc.rs create mode 100644 embassy-stm32/src/pac/stm32l431vc.rs create mode 100644 embassy-stm32/src/pac/stm32l432kb.rs create mode 100644 embassy-stm32/src/pac/stm32l432kc.rs create mode 100644 embassy-stm32/src/pac/stm32l433cb.rs create mode 100644 embassy-stm32/src/pac/stm32l433cc.rs create mode 100644 embassy-stm32/src/pac/stm32l433rb.rs create mode 100644 embassy-stm32/src/pac/stm32l433rc.rs create mode 100644 embassy-stm32/src/pac/stm32l433vc.rs create mode 100644 embassy-stm32/src/pac/stm32l442kc.rs create mode 100644 embassy-stm32/src/pac/stm32l443cc.rs create mode 100644 embassy-stm32/src/pac/stm32l443rc.rs create mode 100644 embassy-stm32/src/pac/stm32l443vc.rs create mode 100644 embassy-stm32/src/pac/stm32l451cc.rs create mode 100644 embassy-stm32/src/pac/stm32l451ce.rs create mode 100644 embassy-stm32/src/pac/stm32l451rc.rs create mode 100644 embassy-stm32/src/pac/stm32l451re.rs create mode 100644 embassy-stm32/src/pac/stm32l451vc.rs create mode 100644 embassy-stm32/src/pac/stm32l451ve.rs create mode 100644 embassy-stm32/src/pac/stm32l452cc.rs create mode 100644 embassy-stm32/src/pac/stm32l452ce.rs create mode 100644 embassy-stm32/src/pac/stm32l452rc.rs create mode 100644 embassy-stm32/src/pac/stm32l452re.rs create mode 100644 embassy-stm32/src/pac/stm32l452vc.rs create mode 100644 embassy-stm32/src/pac/stm32l452ve.rs create mode 100644 embassy-stm32/src/pac/stm32l462ce.rs create mode 100644 embassy-stm32/src/pac/stm32l462re.rs create mode 100644 embassy-stm32/src/pac/stm32l462ve.rs create mode 100644 embassy-stm32/src/pac/stm32l471qe.rs create mode 100644 embassy-stm32/src/pac/stm32l471qg.rs create mode 100644 embassy-stm32/src/pac/stm32l471re.rs create mode 100644 embassy-stm32/src/pac/stm32l471rg.rs create mode 100644 embassy-stm32/src/pac/stm32l471ve.rs create mode 100644 embassy-stm32/src/pac/stm32l471vg.rs create mode 100644 embassy-stm32/src/pac/stm32l471ze.rs create mode 100644 embassy-stm32/src/pac/stm32l471zg.rs create mode 100644 embassy-stm32/src/pac/stm32l475rc.rs create mode 100644 embassy-stm32/src/pac/stm32l475re.rs create mode 100644 embassy-stm32/src/pac/stm32l475rg.rs create mode 100644 embassy-stm32/src/pac/stm32l475vc.rs create mode 100644 embassy-stm32/src/pac/stm32l475ve.rs create mode 100644 embassy-stm32/src/pac/stm32l475vg.rs create mode 100644 embassy-stm32/src/pac/stm32l476je.rs create mode 100644 embassy-stm32/src/pac/stm32l476jg.rs create mode 100644 embassy-stm32/src/pac/stm32l476me.rs create mode 100644 embassy-stm32/src/pac/stm32l476mg.rs create mode 100644 embassy-stm32/src/pac/stm32l476qe.rs create mode 100644 embassy-stm32/src/pac/stm32l476qg.rs create mode 100644 embassy-stm32/src/pac/stm32l476rc.rs create mode 100644 embassy-stm32/src/pac/stm32l476re.rs create mode 100644 embassy-stm32/src/pac/stm32l476rg.rs create mode 100644 embassy-stm32/src/pac/stm32l476vc.rs create mode 100644 embassy-stm32/src/pac/stm32l476ve.rs create mode 100644 embassy-stm32/src/pac/stm32l476vg.rs create mode 100644 embassy-stm32/src/pac/stm32l476ze.rs create mode 100644 embassy-stm32/src/pac/stm32l476zg.rs create mode 100644 embassy-stm32/src/pac/stm32l485jc.rs create mode 100644 embassy-stm32/src/pac/stm32l485je.rs create mode 100644 embassy-stm32/src/pac/stm32l486jg.rs create mode 100644 embassy-stm32/src/pac/stm32l486qg.rs create mode 100644 embassy-stm32/src/pac/stm32l486rg.rs create mode 100644 embassy-stm32/src/pac/stm32l486vg.rs create mode 100644 embassy-stm32/src/pac/stm32l486zg.rs create mode 100644 embassy-stm32/src/pac/stm32l496ae.rs create mode 100644 embassy-stm32/src/pac/stm32l496ag.rs create mode 100644 embassy-stm32/src/pac/stm32l496qe.rs create mode 100644 embassy-stm32/src/pac/stm32l496qg.rs create mode 100644 embassy-stm32/src/pac/stm32l496re.rs create mode 100644 embassy-stm32/src/pac/stm32l496rg.rs create mode 100644 embassy-stm32/src/pac/stm32l496ve.rs create mode 100644 embassy-stm32/src/pac/stm32l496vg.rs create mode 100644 embassy-stm32/src/pac/stm32l496wg.rs create mode 100644 embassy-stm32/src/pac/stm32l496ze.rs create mode 100644 embassy-stm32/src/pac/stm32l496zg.rs create mode 100644 embassy-stm32/src/pac/stm32l4a6ag.rs create mode 100644 embassy-stm32/src/pac/stm32l4a6qg.rs create mode 100644 embassy-stm32/src/pac/stm32l4a6rg.rs create mode 100644 embassy-stm32/src/pac/stm32l4a6vg.rs create mode 100644 embassy-stm32/src/pac/stm32l4a6zg.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5ae.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5ag.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5ce.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5cg.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5qe.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5qg.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5re.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5rg.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5ve.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5vg.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5ze.rs create mode 100644 embassy-stm32/src/pac/stm32l4p5zg.rs create mode 100644 embassy-stm32/src/pac/stm32l4q5ag.rs create mode 100644 embassy-stm32/src/pac/stm32l4q5cg.rs create mode 100644 embassy-stm32/src/pac/stm32l4q5qg.rs create mode 100644 embassy-stm32/src/pac/stm32l4q5rg.rs create mode 100644 embassy-stm32/src/pac/stm32l4q5vg.rs create mode 100644 embassy-stm32/src/pac/stm32l4q5zg.rs create mode 100644 embassy-stm32/src/pac/stm32l4r5ag.rs create mode 100644 embassy-stm32/src/pac/stm32l4r5ai.rs create mode 100644 embassy-stm32/src/pac/stm32l4r5qg.rs create mode 100644 embassy-stm32/src/pac/stm32l4r5qi.rs create mode 100644 embassy-stm32/src/pac/stm32l4r5vg.rs create mode 100644 embassy-stm32/src/pac/stm32l4r5vi.rs create mode 100644 embassy-stm32/src/pac/stm32l4r5zg.rs create mode 100644 embassy-stm32/src/pac/stm32l4r5zi.rs create mode 100644 embassy-stm32/src/pac/stm32l4r7ai.rs create mode 100644 embassy-stm32/src/pac/stm32l4r7vi.rs create mode 100644 embassy-stm32/src/pac/stm32l4r7zi.rs create mode 100644 embassy-stm32/src/pac/stm32l4r9ag.rs create mode 100644 embassy-stm32/src/pac/stm32l4r9ai.rs create mode 100644 embassy-stm32/src/pac/stm32l4r9vg.rs create mode 100644 embassy-stm32/src/pac/stm32l4r9vi.rs create mode 100644 embassy-stm32/src/pac/stm32l4r9zg.rs create mode 100644 embassy-stm32/src/pac/stm32l4r9zi.rs create mode 100644 embassy-stm32/src/pac/stm32l4s5ai.rs create mode 100644 embassy-stm32/src/pac/stm32l4s5qi.rs create mode 100644 embassy-stm32/src/pac/stm32l4s5vi.rs create mode 100644 embassy-stm32/src/pac/stm32l4s5zi.rs create mode 100644 embassy-stm32/src/pac/stm32l4s7ai.rs create mode 100644 embassy-stm32/src/pac/stm32l4s7vi.rs create mode 100644 embassy-stm32/src/pac/stm32l4s7zi.rs create mode 100644 embassy-stm32/src/pac/stm32l4s9ai.rs create mode 100644 embassy-stm32/src/pac/stm32l4s9vi.rs create mode 100644 embassy-stm32/src/pac/stm32l4s9zi.rs diff --git a/.vscode/settings.json b/.vscode/settings.json index dc200f79e..172934130 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,16 +1,3 @@ { - "rust-analyzer.assist.importMergeBehavior": "last", "editor.formatOnSave": true, - "rust-analyzer.cargo.allFeatures": false, - "rust-analyzer.checkOnSave.allFeatures": false, - "rust-analyzer.checkOnSave.allTargets": false, - "rust-analyzer.cargo.target": "thumbv7em-none-eabihf", - "rust-analyzer.checkOnSave.target": "thumbv7em-none-eabihf", - "rust-analyzer.procMacro.enable": true, - "rust-analyzer.cargo.loadOutDirsFromCheck": true, - "files.watcherExclude": { - "**/.git/objects/**": true, - "**/.git/subtree-cache/**": true, - "**/target/**": true - } } \ No newline at end of file diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml index 245b0ffcb..a53cf9c4d 100644 --- a/embassy-stm32/Cargo.toml +++ b/embassy-stm32/Cargo.toml @@ -15,7 +15,6 @@ cortex-m-rt = { version = "0.6.13", features = ["device"] } cortex-m = "0.7.1" embedded-hal = { version = "0.2.4" } futures = { version = "0.3.5", default-features = false, features = ["async-await"] } -stm32-metapac = { path = "../../stm32-metapac"} [build-dependencies] regex = "1.4.6" @@ -32,294 +31,294 @@ _usart_v1 = [] _rng_v1 = [] # BEGIN GENERATED FEATURES -stm32f401cb = [ "_syscfg_f4", "_usart_v1",] -stm32f401cc = [ "_syscfg_f4", "_usart_v1",] -stm32f401cd = [ "_syscfg_f4", "_usart_v1",] -stm32f401ce = [ "_syscfg_f4", "_usart_v1",] -stm32f401rb = [ "_syscfg_f4", "_usart_v1",] -stm32f401rc = [ "_syscfg_f4", "_usart_v1",] -stm32f401rd = [ "_syscfg_f4", "_usart_v1",] -stm32f401re = [ "_syscfg_f4", "_usart_v1",] -stm32f401vb = [ "_syscfg_f4", "_usart_v1",] -stm32f401vc = [ "_syscfg_f4", "_usart_v1",] -stm32f401vd = [ "_syscfg_f4", "_usart_v1",] -stm32f401ve = [ "_syscfg_f4", "_usart_v1",] -stm32f405oe = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f405og = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f405rg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f405vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f405zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f407ie = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f407ig = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f407ve = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f407vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f407ze = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f407zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f410c8 = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f410cb = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f410r8 = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f410rb = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f410t8 = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f410tb = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f411cc = [ "_syscfg_f4", "_usart_v1",] -stm32f411ce = [ "_syscfg_f4", "_usart_v1",] -stm32f411rc = [ "_syscfg_f4", "_usart_v1",] -stm32f411re = [ "_syscfg_f4", "_usart_v1",] -stm32f411vc = [ "_syscfg_f4", "_usart_v1",] -stm32f411ve = [ "_syscfg_f4", "_usart_v1",] -stm32f412ce = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f412cg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f412re = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f412rg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f412ve = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f412vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f412ze = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f412zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f413cg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f413ch = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f413mg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f413mh = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f413rg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f413rh = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f413vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f413vh = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f413zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f413zh = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f415og = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f415rg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f415vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f415zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f417ie = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f417ig = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f417ve = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f417vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f417ze = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f417zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f423ch = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f423mh = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f423rh = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f423vh = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f423zh = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f427ag = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f427ai = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f427ig = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f427ii = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f427vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f427vi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f427zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f427zi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429ag = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429ai = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429be = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429bg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429bi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429ie = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429ig = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429ii = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429ne = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429ng = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429ni = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429ve = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429vi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429ze = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f429zi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f437ai = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f437ig = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f437ii = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f437vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f437vi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f437zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f437zi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439ai = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439bg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439bi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439ig = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439ii = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439ng = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439ni = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439vi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f439zi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f446mc = [ "_syscfg_f4", "_usart_v1",] -stm32f446me = [ "_syscfg_f4", "_usart_v1",] -stm32f446rc = [ "_syscfg_f4", "_usart_v1",] -stm32f446re = [ "_syscfg_f4", "_usart_v1",] -stm32f446vc = [ "_syscfg_f4", "_usart_v1",] -stm32f446ve = [ "_syscfg_f4", "_usart_v1",] -stm32f446zc = [ "_syscfg_f4", "_usart_v1",] -stm32f446ze = [ "_syscfg_f4", "_usart_v1",] -stm32f469ae = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469ag = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469ai = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469be = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469bg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469bi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469ie = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469ig = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469ii = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469ne = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469ng = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469ni = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469ve = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469vi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469ze = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f469zi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479ag = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479ai = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479bg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479bi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479ig = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479ii = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479ng = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479ni = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479vg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479vi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479zg = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32f479zi = [ "_syscfg_f4", "_rng_v1", "_usart_v1",] -stm32l412c8 = [ "_rng_v1", "_syscfg_l4",] -stm32l412cb = [ "_rng_v1", "_syscfg_l4",] -stm32l412k8 = [ "_rng_v1", "_syscfg_l4",] -stm32l412kb = [ "_rng_v1", "_syscfg_l4",] -stm32l412r8 = [ "_rng_v1", "_syscfg_l4",] -stm32l412rb = [ "_rng_v1", "_syscfg_l4",] -stm32l412t8 = [ "_rng_v1", "_syscfg_l4",] -stm32l412tb = [ "_rng_v1", "_syscfg_l4",] -stm32l422cb = [ "_rng_v1", "_syscfg_l4",] -stm32l422kb = [ "_rng_v1", "_syscfg_l4",] -stm32l422rb = [ "_rng_v1", "_syscfg_l4",] -stm32l422tb = [ "_rng_v1", "_syscfg_l4",] -stm32l431cb = [ "_rng_v1", "_syscfg_l4",] -stm32l431cc = [ "_rng_v1", "_syscfg_l4",] -stm32l431kb = [ "_rng_v1", "_syscfg_l4",] -stm32l431kc = [ "_rng_v1", "_syscfg_l4",] -stm32l431rb = [ "_rng_v1", "_syscfg_l4",] -stm32l431rc = [ "_rng_v1", "_syscfg_l4",] -stm32l431vc = [ "_rng_v1", "_syscfg_l4",] -stm32l432kb = [ "_rng_v1", "_syscfg_l4",] -stm32l432kc = [ "_rng_v1", "_syscfg_l4",] -stm32l433cb = [ "_rng_v1", "_syscfg_l4",] -stm32l433cc = [ "_rng_v1", "_syscfg_l4",] -stm32l433rb = [ "_rng_v1", "_syscfg_l4",] -stm32l433rc = [ "_rng_v1", "_syscfg_l4",] -stm32l433vc = [ "_rng_v1", "_syscfg_l4",] -stm32l442kc = [ "_rng_v1", "_syscfg_l4",] -stm32l443cc = [ "_rng_v1", "_syscfg_l4",] -stm32l443rc = [ "_rng_v1", "_syscfg_l4",] -stm32l443vc = [ "_rng_v1", "_syscfg_l4",] -stm32l451cc = [ "_rng_v1", "_syscfg_l4",] -stm32l451ce = [ "_rng_v1", "_syscfg_l4",] -stm32l451rc = [ "_rng_v1", "_syscfg_l4",] -stm32l451re = [ "_rng_v1", "_syscfg_l4",] -stm32l451vc = [ "_rng_v1", "_syscfg_l4",] -stm32l451ve = [ "_rng_v1", "_syscfg_l4",] -stm32l452cc = [ "_rng_v1", "_syscfg_l4",] -stm32l452ce = [ "_rng_v1", "_syscfg_l4",] -stm32l452rc = [ "_rng_v1", "_syscfg_l4",] -stm32l452re = [ "_rng_v1", "_syscfg_l4",] -stm32l452vc = [ "_rng_v1", "_syscfg_l4",] -stm32l452ve = [ "_rng_v1", "_syscfg_l4",] -stm32l462ce = [ "_rng_v1", "_syscfg_l4",] -stm32l462re = [ "_rng_v1", "_syscfg_l4",] -stm32l462ve = [ "_rng_v1", "_syscfg_l4",] -stm32l471qe = [ "_rng_v1", "_syscfg_l4",] -stm32l471qg = [ "_rng_v1", "_syscfg_l4",] -stm32l471re = [ "_rng_v1", "_syscfg_l4",] -stm32l471rg = [ "_rng_v1", "_syscfg_l4",] -stm32l471ve = [ "_rng_v1", "_syscfg_l4",] -stm32l471vg = [ "_rng_v1", "_syscfg_l4",] -stm32l471ze = [ "_rng_v1", "_syscfg_l4",] -stm32l471zg = [ "_rng_v1", "_syscfg_l4",] -stm32l475rc = [ "_rng_v1", "_syscfg_l4",] -stm32l475re = [ "_rng_v1", "_syscfg_l4",] -stm32l475rg = [ "_rng_v1", "_syscfg_l4",] -stm32l475vc = [ "_rng_v1", "_syscfg_l4",] -stm32l475ve = [ "_rng_v1", "_syscfg_l4",] -stm32l475vg = [ "_rng_v1", "_syscfg_l4",] -stm32l476je = [ "_rng_v1", "_syscfg_l4",] -stm32l476jg = [ "_rng_v1", "_syscfg_l4",] -stm32l476me = [ "_rng_v1", "_syscfg_l4",] -stm32l476mg = [ "_rng_v1", "_syscfg_l4",] -stm32l476qe = [ "_rng_v1", "_syscfg_l4",] -stm32l476qg = [ "_rng_v1", "_syscfg_l4",] -stm32l476rc = [ "_rng_v1", "_syscfg_l4",] -stm32l476re = [ "_rng_v1", "_syscfg_l4",] -stm32l476rg = [ "_rng_v1", "_syscfg_l4",] -stm32l476vc = [ "_rng_v1", "_syscfg_l4",] -stm32l476ve = [ "_rng_v1", "_syscfg_l4",] -stm32l476vg = [ "_rng_v1", "_syscfg_l4",] -stm32l476ze = [ "_rng_v1", "_syscfg_l4",] -stm32l476zg = [ "_rng_v1", "_syscfg_l4",] -stm32l485jc = [ "_rng_v1", "_syscfg_l4",] -stm32l485je = [ "_rng_v1", "_syscfg_l4",] -stm32l486jg = [ "_rng_v1", "_syscfg_l4",] -stm32l486qg = [ "_rng_v1", "_syscfg_l4",] -stm32l486rg = [ "_rng_v1", "_syscfg_l4",] -stm32l486vg = [ "_rng_v1", "_syscfg_l4",] -stm32l486zg = [ "_rng_v1", "_syscfg_l4",] -stm32l496ae = [ "_rng_v1", "_syscfg_l4",] -stm32l496ag = [ "_rng_v1", "_syscfg_l4",] -stm32l496qe = [ "_rng_v1", "_syscfg_l4",] -stm32l496qg = [ "_rng_v1", "_syscfg_l4",] -stm32l496re = [ "_rng_v1", "_syscfg_l4",] -stm32l496rg = [ "_rng_v1", "_syscfg_l4",] -stm32l496ve = [ "_rng_v1", "_syscfg_l4",] -stm32l496vg = [ "_rng_v1", "_syscfg_l4",] -stm32l496wg = [ "_rng_v1", "_syscfg_l4",] -stm32l496ze = [ "_rng_v1", "_syscfg_l4",] -stm32l496zg = [ "_rng_v1", "_syscfg_l4",] -stm32l4a6ag = [ "_rng_v1", "_syscfg_l4",] -stm32l4a6qg = [ "_rng_v1", "_syscfg_l4",] -stm32l4a6rg = [ "_rng_v1", "_syscfg_l4",] -stm32l4a6vg = [ "_rng_v1", "_syscfg_l4",] -stm32l4a6zg = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5ae = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5ag = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5ce = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5cg = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5qe = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5qg = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5re = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5rg = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5ve = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5vg = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5ze = [ "_rng_v1", "_syscfg_l4",] -stm32l4p5zg = [ "_rng_v1", "_syscfg_l4",] -stm32l4q5ag = [ "_rng_v1", "_syscfg_l4",] -stm32l4q5cg = [ "_rng_v1", "_syscfg_l4",] -stm32l4q5qg = [ "_rng_v1", "_syscfg_l4",] -stm32l4q5rg = [ "_rng_v1", "_syscfg_l4",] -stm32l4q5vg = [ "_rng_v1", "_syscfg_l4",] -stm32l4q5zg = [ "_rng_v1", "_syscfg_l4",] -stm32l4r5ag = [ "_rng_v1", "_syscfg_l4",] -stm32l4r5ai = [ "_rng_v1", "_syscfg_l4",] -stm32l4r5qg = [ "_rng_v1", "_syscfg_l4",] -stm32l4r5qi = [ "_rng_v1", "_syscfg_l4",] -stm32l4r5vg = [ "_rng_v1", "_syscfg_l4",] -stm32l4r5vi = [ "_rng_v1", "_syscfg_l4",] -stm32l4r5zg = [ "_rng_v1", "_syscfg_l4",] -stm32l4r5zi = [ "_rng_v1", "_syscfg_l4",] -stm32l4r7ai = [ "_rng_v1", "_syscfg_l4",] -stm32l4r7vi = [ "_rng_v1", "_syscfg_l4",] -stm32l4r7zi = [ "_rng_v1", "_syscfg_l4",] -stm32l4r9ag = [ "_rng_v1", "_syscfg_l4",] -stm32l4r9ai = [ "_rng_v1", "_syscfg_l4",] -stm32l4r9vg = [ "_rng_v1", "_syscfg_l4",] -stm32l4r9vi = [ "_rng_v1", "_syscfg_l4",] -stm32l4r9zg = [ "_rng_v1", "_syscfg_l4",] -stm32l4r9zi = [ "_rng_v1", "_syscfg_l4",] -stm32l4s5ai = [ "_rng_v1", "_syscfg_l4",] -stm32l4s5qi = [ "_rng_v1", "_syscfg_l4",] -stm32l4s5vi = [ "_rng_v1", "_syscfg_l4",] -stm32l4s5zi = [ "_rng_v1", "_syscfg_l4",] -stm32l4s7ai = [ "_rng_v1", "_syscfg_l4",] -stm32l4s7vi = [ "_rng_v1", "_syscfg_l4",] -stm32l4s7zi = [ "_rng_v1", "_syscfg_l4",] -stm32l4s9ai = [ "_rng_v1", "_syscfg_l4",] -stm32l4s9vi = [ "_rng_v1", "_syscfg_l4",] -stm32l4s9zi = [ "_rng_v1", "_syscfg_l4",] +stm32f401cb = [ "_usart_v1",] +stm32f401cc = [ "_usart_v1",] +stm32f401cd = [ "_usart_v1",] +stm32f401ce = [ "_usart_v1",] +stm32f401rb = [ "_usart_v1",] +stm32f401rc = [ "_usart_v1",] +stm32f401rd = [ "_usart_v1",] +stm32f401re = [ "_usart_v1",] +stm32f401vb = [ "_usart_v1",] +stm32f401vc = [ "_usart_v1",] +stm32f401vd = [ "_usart_v1",] +stm32f401ve = [ "_usart_v1",] +stm32f405oe = [ "_usart_v1",] +stm32f405og = [ "_usart_v1",] +stm32f405rg = [ "_usart_v1",] +stm32f405vg = [ "_usart_v1",] +stm32f405zg = [ "_usart_v1",] +stm32f407ie = [ "_usart_v1",] +stm32f407ig = [ "_usart_v1",] +stm32f407ve = [ "_usart_v1",] +stm32f407vg = [ "_usart_v1",] +stm32f407ze = [ "_usart_v1",] +stm32f407zg = [ "_usart_v1",] +stm32f410c8 = [ "_usart_v1",] +stm32f410cb = [ "_usart_v1",] +stm32f410r8 = [ "_usart_v1",] +stm32f410rb = [ "_usart_v1",] +stm32f410t8 = [ "_usart_v1",] +stm32f410tb = [ "_usart_v1",] +stm32f411cc = [ "_usart_v1",] +stm32f411ce = [ "_usart_v1",] +stm32f411rc = [ "_usart_v1",] +stm32f411re = [ "_usart_v1",] +stm32f411vc = [ "_usart_v1",] +stm32f411ve = [ "_usart_v1",] +stm32f412ce = [ "_usart_v1",] +stm32f412cg = [ "_usart_v1",] +stm32f412re = [ "_usart_v1",] +stm32f412rg = [ "_usart_v1",] +stm32f412ve = [ "_usart_v1",] +stm32f412vg = [ "_usart_v1",] +stm32f412ze = [ "_usart_v1",] +stm32f412zg = [ "_usart_v1",] +stm32f413cg = [ "_usart_v1",] +stm32f413ch = [ "_usart_v1",] +stm32f413mg = [ "_usart_v1",] +stm32f413mh = [ "_usart_v1",] +stm32f413rg = [ "_usart_v1",] +stm32f413rh = [ "_usart_v1",] +stm32f413vg = [ "_usart_v1",] +stm32f413vh = [ "_usart_v1",] +stm32f413zg = [ "_usart_v1",] +stm32f413zh = [ "_usart_v1",] +stm32f415og = [ "_usart_v1",] +stm32f415rg = [ "_usart_v1",] +stm32f415vg = [ "_usart_v1",] +stm32f415zg = [ "_usart_v1",] +stm32f417ie = [ "_usart_v1",] +stm32f417ig = [ "_usart_v1",] +stm32f417ve = [ "_usart_v1",] +stm32f417vg = [ "_usart_v1",] +stm32f417ze = [ "_usart_v1",] +stm32f417zg = [ "_usart_v1",] +stm32f423ch = [ "_usart_v1",] +stm32f423mh = [ "_usart_v1",] +stm32f423rh = [ "_usart_v1",] +stm32f423vh = [ "_usart_v1",] +stm32f423zh = [ "_usart_v1",] +stm32f427ag = [ "_usart_v1",] +stm32f427ai = [ "_usart_v1",] +stm32f427ig = [ "_usart_v1",] +stm32f427ii = [ "_usart_v1",] +stm32f427vg = [ "_usart_v1",] +stm32f427vi = [ "_usart_v1",] +stm32f427zg = [ "_usart_v1",] +stm32f427zi = [ "_usart_v1",] +stm32f429ag = [ "_usart_v1",] +stm32f429ai = [ "_usart_v1",] +stm32f429be = [ "_usart_v1",] +stm32f429bg = [ "_usart_v1",] +stm32f429bi = [ "_usart_v1",] +stm32f429ie = [ "_usart_v1",] +stm32f429ig = [ "_usart_v1",] +stm32f429ii = [ "_usart_v1",] +stm32f429ne = [ "_usart_v1",] +stm32f429ng = [ "_usart_v1",] +stm32f429ni = [ "_usart_v1",] +stm32f429ve = [ "_usart_v1",] +stm32f429vg = [ "_usart_v1",] +stm32f429vi = [ "_usart_v1",] +stm32f429ze = [ "_usart_v1",] +stm32f429zg = [ "_usart_v1",] +stm32f429zi = [ "_usart_v1",] +stm32f437ai = [ "_usart_v1",] +stm32f437ig = [ "_usart_v1",] +stm32f437ii = [ "_usart_v1",] +stm32f437vg = [ "_usart_v1",] +stm32f437vi = [ "_usart_v1",] +stm32f437zg = [ "_usart_v1",] +stm32f437zi = [ "_usart_v1",] +stm32f439ai = [ "_usart_v1",] +stm32f439bg = [ "_usart_v1",] +stm32f439bi = [ "_usart_v1",] +stm32f439ig = [ "_usart_v1",] +stm32f439ii = [ "_usart_v1",] +stm32f439ng = [ "_usart_v1",] +stm32f439ni = [ "_usart_v1",] +stm32f439vg = [ "_usart_v1",] +stm32f439vi = [ "_usart_v1",] +stm32f439zg = [ "_usart_v1",] +stm32f439zi = [ "_usart_v1",] +stm32f446mc = [ "_usart_v1",] +stm32f446me = [ "_usart_v1",] +stm32f446rc = [ "_usart_v1",] +stm32f446re = [ "_usart_v1",] +stm32f446vc = [ "_usart_v1",] +stm32f446ve = [ "_usart_v1",] +stm32f446zc = [ "_usart_v1",] +stm32f446ze = [ "_usart_v1",] +stm32f469ae = [ "_usart_v1",] +stm32f469ag = [ "_usart_v1",] +stm32f469ai = [ "_usart_v1",] +stm32f469be = [ "_usart_v1",] +stm32f469bg = [ "_usart_v1",] +stm32f469bi = [ "_usart_v1",] +stm32f469ie = [ "_usart_v1",] +stm32f469ig = [ "_usart_v1",] +stm32f469ii = [ "_usart_v1",] +stm32f469ne = [ "_usart_v1",] +stm32f469ng = [ "_usart_v1",] +stm32f469ni = [ "_usart_v1",] +stm32f469ve = [ "_usart_v1",] +stm32f469vg = [ "_usart_v1",] +stm32f469vi = [ "_usart_v1",] +stm32f469ze = [ "_usart_v1",] +stm32f469zg = [ "_usart_v1",] +stm32f469zi = [ "_usart_v1",] +stm32f479ag = [ "_usart_v1",] +stm32f479ai = [ "_usart_v1",] +stm32f479bg = [ "_usart_v1",] +stm32f479bi = [ "_usart_v1",] +stm32f479ig = [ "_usart_v1",] +stm32f479ii = [ "_usart_v1",] +stm32f479ng = [ "_usart_v1",] +stm32f479ni = [ "_usart_v1",] +stm32f479vg = [ "_usart_v1",] +stm32f479vi = [ "_usart_v1",] +stm32f479zg = [ "_usart_v1",] +stm32f479zi = [ "_usart_v1",] +stm32l412c8 = [] +stm32l412cb = [] +stm32l412k8 = [] +stm32l412kb = [] +stm32l412r8 = [] +stm32l412rb = [] +stm32l412t8 = [] +stm32l412tb = [] +stm32l422cb = [] +stm32l422kb = [] +stm32l422rb = [] +stm32l422tb = [] +stm32l431cb = [] +stm32l431cc = [] +stm32l431kb = [] +stm32l431kc = [] +stm32l431rb = [] +stm32l431rc = [] +stm32l431vc = [] +stm32l432kb = [] +stm32l432kc = [] +stm32l433cb = [] +stm32l433cc = [] +stm32l433rb = [] +stm32l433rc = [] +stm32l433vc = [] +stm32l442kc = [] +stm32l443cc = [] +stm32l443rc = [] +stm32l443vc = [] +stm32l451cc = [] +stm32l451ce = [] +stm32l451rc = [] +stm32l451re = [] +stm32l451vc = [] +stm32l451ve = [] +stm32l452cc = [] +stm32l452ce = [] +stm32l452rc = [] +stm32l452re = [] +stm32l452vc = [] +stm32l452ve = [] +stm32l462ce = [] +stm32l462re = [] +stm32l462ve = [] +stm32l471qe = [] +stm32l471qg = [] +stm32l471re = [] +stm32l471rg = [] +stm32l471ve = [] +stm32l471vg = [] +stm32l471ze = [] +stm32l471zg = [] +stm32l475rc = [] +stm32l475re = [] +stm32l475rg = [] +stm32l475vc = [] +stm32l475ve = [] +stm32l475vg = [] +stm32l476je = [] +stm32l476jg = [] +stm32l476me = [] +stm32l476mg = [] +stm32l476qe = [] +stm32l476qg = [] +stm32l476rc = [] +stm32l476re = [] +stm32l476rg = [] +stm32l476vc = [] +stm32l476ve = [] +stm32l476vg = [] +stm32l476ze = [] +stm32l476zg = [] +stm32l485jc = [] +stm32l485je = [] +stm32l486jg = [] +stm32l486qg = [] +stm32l486rg = [] +stm32l486vg = [] +stm32l486zg = [] +stm32l496ae = [] +stm32l496ag = [] +stm32l496qe = [] +stm32l496qg = [] +stm32l496re = [] +stm32l496rg = [] +stm32l496ve = [] +stm32l496vg = [] +stm32l496wg = [] +stm32l496ze = [] +stm32l496zg = [] +stm32l4a6ag = [] +stm32l4a6qg = [] +stm32l4a6rg = [] +stm32l4a6vg = [] +stm32l4a6zg = [] +stm32l4p5ae = [] +stm32l4p5ag = [] +stm32l4p5ce = [] +stm32l4p5cg = [] +stm32l4p5qe = [] +stm32l4p5qg = [] +stm32l4p5re = [] +stm32l4p5rg = [] +stm32l4p5ve = [] +stm32l4p5vg = [] +stm32l4p5ze = [] +stm32l4p5zg = [] +stm32l4q5ag = [] +stm32l4q5cg = [] +stm32l4q5qg = [] +stm32l4q5rg = [] +stm32l4q5vg = [] +stm32l4q5zg = [] +stm32l4r5ag = [] +stm32l4r5ai = [] +stm32l4r5qg = [] +stm32l4r5qi = [] +stm32l4r5vg = [] +stm32l4r5vi = [] +stm32l4r5zg = [] +stm32l4r5zi = [] +stm32l4r7ai = [] +stm32l4r7vi = [] +stm32l4r7zi = [] +stm32l4r9ag = [] +stm32l4r9ai = [] +stm32l4r9vg = [] +stm32l4r9vi = [] +stm32l4r9zg = [] +stm32l4r9zi = [] +stm32l4s5ai = [] +stm32l4s5qi = [] +stm32l4s5vi = [] +stm32l4s5zi = [] +stm32l4s7ai = [] +stm32l4s7vi = [] +stm32l4s7zi = [] +stm32l4s9ai = [] +stm32l4s9vi = [] +stm32l4s9zi = [] # END GENERATED FEATURES diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs index aacf4648b..7a46b3dc7 100644 --- a/embassy-stm32/build.rs +++ b/embassy-stm32/build.rs @@ -16,7 +16,7 @@ fn main() { let mut device_x = String::new(); - let chip_rs = fs::read_to_string(format!("src/chip/{}.rs", chip)).unwrap(); + let chip_rs = fs::read_to_string(format!("src/pac/{}.rs", chip)).unwrap(); let re = Regex::new("declare!\\(([a-zA-Z0-9_]+)\\)").unwrap(); for c in re.captures_iter(&chip_rs) { let name = c.get(1).unwrap().as_str(); @@ -29,6 +29,6 @@ fn main() { .write_all(device_x.as_bytes()) .unwrap(); println!("cargo:rustc-link-search={}", out.display()); - println!("cargo:rerun-if-changed=src/chip/{}.rs", chip); + println!("cargo:rerun-if-changed=src/pac/{}.rs", chip); println!("cargo:rerun-if-changed=build.rs"); } diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py index c275ff60f..b2bc82e46 100644 --- a/embassy-stm32/gen.py +++ b/embassy-stm32/gen.py @@ -17,7 +17,7 @@ for f in sorted(glob('stm32-data/data/chips/*.yaml')): if 'STM32F4' not in f and 'STM32L4' not in f: continue with open(f, 'r') as f: - chip = yaml.load(f, Loader=yaml.SafeLoader) + chip = yaml.load(f, Loader=yaml.CSafeLoader) chip['name'] = chip['name'].lower() chip['features'] = [] print(chip['name']) @@ -28,38 +28,54 @@ gpio_afs = {} for f in sorted(glob('stm32-data/data/gpio_af/*.yaml')): name = f.split('/')[-1].split('.')[0] with open(f, 'r') as f: - af = yaml.load(f, Loader=yaml.SafeLoader) + af = yaml.load(f, Loader=yaml.CSafeLoader) gpio_afs[name] = af -# ========= Update chip/mod.rs +# ========= Generate pac/mod.rs -with open('src/chip/mod.rs', 'w') as f: +with open('src/pac/mod.rs', 'w') as f: for chip in chips.values(): f.write( f'#[cfg_attr(feature="{chip["name"]}", path="{chip["name"]}.rs")]\n') f.write('mod chip;\n') f.write('pub use chip::*;\n') -# ========= Generate per-chip mod +# ========= Generate pac/stm32xxx.rs for chip in chips.values(): print(f'generating {chip["name"]}') - af = gpio_afs[chip['gpio_af']] - peripherals = [] - impls = [] - pins = set() - - # TODO this should probably come from the yamls? - # We don't want to hardcode the EXTI peripheral addr - peripherals.extend((f'EXTI{x}' for x in range(16))) - - exti_base = chip['peripherals']['EXTI']['address'] - syscfg_base = chip['peripherals']['SYSCFG']['address'] - gpio_base = chip['peripherals']['GPIOA']['address'] - gpio_stride = 0x400 - - for (name, peri) in chip['peripherals'].items(): - if name.startswith('GPIO'): + with open(f'src/pac/{chip["name"]}.rs', 'w') as f: + + f.write(""" + #![allow(dead_code)] + #![allow(unused_imports)] + #![allow(non_snake_case)] + """) + + af = gpio_afs[chip['gpio_af']] + peripheral_names = [] # USART1, PA5, EXTI8 + peripheral_versions = {} # usart -> v1, syscfg -> f4 + pins = set() # set of all present pins. PA4, PA5... + + # TODO this should probably come from the yamls? + # We don't want to hardcode the EXTI peripheral addr + + gpio_base = chip['peripherals']['GPIOA']['address'] + gpio_stride = 0x400 + f.write(f""" + pub fn GPIO(n: usize) -> gpio::Gpio {{ + gpio::Gpio((0x{gpio_base:x} + 0x{gpio_stride:x}*n) as _) + }} + """) + + # ========= GPIO + + peripheral_names.extend((f'EXTI{x}' for x in range(16))) + + for (name, peri) in chip['peripherals'].items(): + if not name.startswith('GPIO'): + continue + port = name[4:] port_num = ord(port) - ord('A') @@ -68,68 +84,80 @@ for chip in chips.values(): for pin_num in range(16): pin = f'P{port}{pin_num}' pins.add(pin) - peripherals.append(pin) - impls.append(f'impl_gpio_pin!({pin}, {port_num}, {pin_num}, EXTI{pin_num});') - continue - - # TODO maybe we should only autogenerate the known ones...?? - peripherals.append(name) - - if 'block' not in peri: - continue - - if peri['block'] in ('usart_v1/USART', 'usart_v1/UART'): - chip['features'].append("_usart_v1") - impls.append(f'impl_usart!({name}, 0x{peri["address"]:x});') - for pin, funcs in af.items(): - if pin in pins: - if func := funcs.get(f'{name}_RX'): - impls.append(f'impl_usart_pin!({name}, RxPin, {pin}, {func});') - if func := funcs.get(f'{name}_TX'): - impls.append(f'impl_usart_pin!({name}, TxPin, {pin}, {func});') - if func := funcs.get(f'{name}_CTS'): - impls.append(f'impl_usart_pin!({name}, CtsPin, {pin}, {func});') - if func := funcs.get(f'{name}_RTS'): - impls.append(f'impl_usart_pin!({name}, RtsPin, {pin}, {func});') - if func := funcs.get(f'{name}_CK'): - impls.append(f'impl_usart_pin!({name}, CkPin, {pin}, {func});') - - if peri['block'] == 'rng_v1/RNG': - impls.append(f'impl_rng!(0x{peri["address"]:x});') - chip['features'].append("_rng_v1") - - if peri['block'] == 'syscfg_f4/SYSCFG': - chip['features'].append("_syscfg_f4") - - if peri['block'] == 'syscfg_l4/SYSCFG': - chip['features'].append("_syscfg_l4") - - irq_variants = [] - irq_vectors = [] - irq_fns = [] - irq_declares = [] - - irqs = {num: name for name, num in chip['interrupts'].items()} - irq_count = max(irqs.keys()) + 1 - for num, name in irqs.items(): - irq_variants.append(f'{name} = {num},') - irq_fns.append(f'fn {name}();') - irq_declares.append(f'declare!({name});') - for num in range(irq_count): - if name := irqs.get(num): - irq_vectors.append(f'Vector {{ _handler: {name} }},') - else: - irq_vectors.append(f'Vector {{ _reserved: 0 }},') - - with open(f'src/chip/{chip["name"]}.rs', 'w') as f: + peripheral_names.append(pin) + f.write(f'impl_gpio_pin!({pin}, {port_num}, {pin_num}, EXTI{pin_num});') + + # ========= peripherals + + for (name, peri) in chip['peripherals'].items(): + if 'block' not in peri: + continue + + if not name.startswith('GPIO'): + peripheral_names.append(name) + + block = peri['block'] + block_mod, block_name = block.rsplit('/') + block_mod, block_version = block_mod.rsplit('_') + block_name = block_name.capitalize() + + # Check all peripherals have the same version: it's not OK for the same chip to use both usart_v1 and usart_v2 + if old_version := peripheral_versions.get(block_mod): + if old_version != block_version: + raise Exception(f'Peripheral {block_mod} has two versions: {old_version} and {block_version}') + peripheral_versions[block_mod] = block_version + + f.write(f'pub const {name}: {block_mod}::{block_name} = {block_mod}::{block_name}(0x{peri["address"]:x} as _);') + + if peri['block'] in ('usart_v1/USART', 'usart_v1/UART'): + chip['features'].append("_usart_v1") + f.write(f'impl_usart!({name});') + for pin, funcs in af.items(): + if pin in pins: + if func := funcs.get(f'{name}_RX'): + f.write(f'impl_usart_pin!({name}, RxPin, {pin}, {func});') + if func := funcs.get(f'{name}_TX'): + f.write(f'impl_usart_pin!({name}, TxPin, {pin}, {func});') + if func := funcs.get(f'{name}_CTS'): + f.write(f'impl_usart_pin!({name}, CtsPin, {pin}, {func});') + if func := funcs.get(f'{name}_RTS'): + f.write(f'impl_usart_pin!({name}, RtsPin, {pin}, {func});') + if func := funcs.get(f'{name}_CK'): + f.write(f'impl_usart_pin!({name}, CkPin, {pin}, {func});') + + if peri['block'] == 'rng_v1/RNG': + f.write(f'impl_rng!({name});') + + for mod, version in peripheral_versions.items(): + f.write(f'pub use regs::{mod}_{version} as {mod};') + f.write(f""" + mod regs; + pub use regs::generic; use embassy_extras::peripherals; - peripherals!({','.join(peripherals)}); - pub const SYSCFG_BASE: usize = 0x{syscfg_base:x}; - pub const EXTI_BASE: usize = 0x{exti_base:x}; - pub const GPIO_BASE: usize = 0x{gpio_base:x}; - pub const GPIO_STRIDE: usize = 0x{gpio_stride:x}; + peripherals!({','.join(peripheral_names)}); + """) + # ========= interrupts + + irq_variants = [] + irq_vectors = [] + irq_fns = [] + irq_declares = [] + + irqs = {num: name for name, num in chip['interrupts'].items()} + irq_count = max(irqs.keys()) + 1 + for num, name in irqs.items(): + irq_variants.append(f'{name} = {num},') + irq_fns.append(f'fn {name}();') + irq_declares.append(f'declare!({name});') + for num in range(irq_count): + if name := irqs.get(num): + irq_vectors.append(f'Vector {{ _handler: {name} }},') + else: + irq_vectors.append(f'Vector {{ _reserved: 0 }},') + + f.write(f""" pub mod interrupt {{ pub use cortex_m::interrupt::{{CriticalSection, Mutex}}; pub use embassy::interrupt::{{declare, take, Interrupt}}; @@ -164,9 +192,6 @@ for chip in chips.values(): ]; }} """) - for i in impls: - f.write(i) - # ========= Update Cargo features @@ -184,6 +209,9 @@ cargo = before + SEPARATOR_START + toml.dumps(features) + SEPARATOR_END + after with open('Cargo.toml', 'w') as f: f.write(cargo) +# ========= Generate pac/regs.rs +os.system('cargo run --manifest-path ../../svd2rust/Cargo.toml -- generate --dir stm32-data/data/registers') +os.system('mv lib.rs src/pac/regs.rs') -# format -os.system('rustfmt src/chip/*') +# ========= Update Cargo features +os.system('rustfmt src/pac/*') diff --git a/embassy-stm32/src/chip/mod.rs b/embassy-stm32/src/chip/mod.rs deleted file mode 100644 index 35fff08c0..000000000 --- a/embassy-stm32/src/chip/mod.rs +++ /dev/null @@ -1,292 +0,0 @@ -#[cfg_attr(feature = "stm32f401cb", path = "stm32f401cb.rs")] -#[cfg_attr(feature = "stm32f401cc", path = "stm32f401cc.rs")] -#[cfg_attr(feature = "stm32f401cd", path = "stm32f401cd.rs")] -#[cfg_attr(feature = "stm32f401ce", path = "stm32f401ce.rs")] -#[cfg_attr(feature = "stm32f401rb", path = "stm32f401rb.rs")] -#[cfg_attr(feature = "stm32f401rc", path = "stm32f401rc.rs")] -#[cfg_attr(feature = "stm32f401rd", path = "stm32f401rd.rs")] -#[cfg_attr(feature = "stm32f401re", path = "stm32f401re.rs")] -#[cfg_attr(feature = "stm32f401vb", path = "stm32f401vb.rs")] -#[cfg_attr(feature = "stm32f401vc", path = "stm32f401vc.rs")] -#[cfg_attr(feature = "stm32f401vd", path = "stm32f401vd.rs")] -#[cfg_attr(feature = "stm32f401ve", path = "stm32f401ve.rs")] -#[cfg_attr(feature = "stm32f405oe", path = "stm32f405oe.rs")] -#[cfg_attr(feature = "stm32f405og", path = "stm32f405og.rs")] -#[cfg_attr(feature = "stm32f405rg", path = "stm32f405rg.rs")] -#[cfg_attr(feature = "stm32f405vg", path = "stm32f405vg.rs")] -#[cfg_attr(feature = "stm32f405zg", path = "stm32f405zg.rs")] -#[cfg_attr(feature = "stm32f407ie", path = "stm32f407ie.rs")] -#[cfg_attr(feature = "stm32f407ig", path = "stm32f407ig.rs")] -#[cfg_attr(feature = "stm32f407ve", path = "stm32f407ve.rs")] -#[cfg_attr(feature = "stm32f407vg", path = "stm32f407vg.rs")] -#[cfg_attr(feature = "stm32f407ze", path = "stm32f407ze.rs")] -#[cfg_attr(feature = "stm32f407zg", path = "stm32f407zg.rs")] -#[cfg_attr(feature = "stm32f410c8", path = "stm32f410c8.rs")] -#[cfg_attr(feature = "stm32f410cb", path = "stm32f410cb.rs")] -#[cfg_attr(feature = "stm32f410r8", path = "stm32f410r8.rs")] -#[cfg_attr(feature = "stm32f410rb", path = "stm32f410rb.rs")] -#[cfg_attr(feature = "stm32f410t8", path = "stm32f410t8.rs")] -#[cfg_attr(feature = "stm32f410tb", path = "stm32f410tb.rs")] -#[cfg_attr(feature = "stm32f411cc", path = "stm32f411cc.rs")] -#[cfg_attr(feature = "stm32f411ce", path = "stm32f411ce.rs")] -#[cfg_attr(feature = "stm32f411rc", path = "stm32f411rc.rs")] -#[cfg_attr(feature = "stm32f411re", path = "stm32f411re.rs")] -#[cfg_attr(feature = "stm32f411vc", path = "stm32f411vc.rs")] -#[cfg_attr(feature = "stm32f411ve", path = "stm32f411ve.rs")] -#[cfg_attr(feature = "stm32f412ce", path = "stm32f412ce.rs")] -#[cfg_attr(feature = "stm32f412cg", path = "stm32f412cg.rs")] -#[cfg_attr(feature = "stm32f412re", path = "stm32f412re.rs")] -#[cfg_attr(feature = "stm32f412rg", path = "stm32f412rg.rs")] -#[cfg_attr(feature = "stm32f412ve", path = "stm32f412ve.rs")] -#[cfg_attr(feature = "stm32f412vg", path = "stm32f412vg.rs")] -#[cfg_attr(feature = "stm32f412ze", path = "stm32f412ze.rs")] -#[cfg_attr(feature = "stm32f412zg", path = "stm32f412zg.rs")] -#[cfg_attr(feature = "stm32f413cg", path = "stm32f413cg.rs")] -#[cfg_attr(feature = "stm32f413ch", path = "stm32f413ch.rs")] -#[cfg_attr(feature = "stm32f413mg", path = "stm32f413mg.rs")] -#[cfg_attr(feature = "stm32f413mh", path = "stm32f413mh.rs")] -#[cfg_attr(feature = "stm32f413rg", path = "stm32f413rg.rs")] -#[cfg_attr(feature = "stm32f413rh", path = "stm32f413rh.rs")] -#[cfg_attr(feature = "stm32f413vg", path = "stm32f413vg.rs")] -#[cfg_attr(feature = "stm32f413vh", path = "stm32f413vh.rs")] -#[cfg_attr(feature = "stm32f413zg", path = "stm32f413zg.rs")] -#[cfg_attr(feature = "stm32f413zh", path = "stm32f413zh.rs")] -#[cfg_attr(feature = "stm32f415og", path = "stm32f415og.rs")] -#[cfg_attr(feature = "stm32f415rg", path = "stm32f415rg.rs")] -#[cfg_attr(feature = "stm32f415vg", path = "stm32f415vg.rs")] -#[cfg_attr(feature = "stm32f415zg", path = "stm32f415zg.rs")] -#[cfg_attr(feature = "stm32f417ie", path = "stm32f417ie.rs")] -#[cfg_attr(feature = "stm32f417ig", path = "stm32f417ig.rs")] -#[cfg_attr(feature = "stm32f417ve", path = "stm32f417ve.rs")] -#[cfg_attr(feature = "stm32f417vg", path = "stm32f417vg.rs")] -#[cfg_attr(feature = "stm32f417ze", path = "stm32f417ze.rs")] -#[cfg_attr(feature = "stm32f417zg", path = "stm32f417zg.rs")] -#[cfg_attr(feature = "stm32f423ch", path = "stm32f423ch.rs")] -#[cfg_attr(feature = "stm32f423mh", path = "stm32f423mh.rs")] -#[cfg_attr(feature = "stm32f423rh", path = "stm32f423rh.rs")] -#[cfg_attr(feature = "stm32f423vh", path = "stm32f423vh.rs")] -#[cfg_attr(feature = "stm32f423zh", path = "stm32f423zh.rs")] -#[cfg_attr(feature = "stm32f427ag", path = "stm32f427ag.rs")] -#[cfg_attr(feature = "stm32f427ai", path = "stm32f427ai.rs")] -#[cfg_attr(feature = "stm32f427ig", path = "stm32f427ig.rs")] -#[cfg_attr(feature = "stm32f427ii", path = "stm32f427ii.rs")] -#[cfg_attr(feature = "stm32f427vg", path = "stm32f427vg.rs")] -#[cfg_attr(feature = "stm32f427vi", path = "stm32f427vi.rs")] -#[cfg_attr(feature = "stm32f427zg", path = "stm32f427zg.rs")] -#[cfg_attr(feature = "stm32f427zi", path = "stm32f427zi.rs")] -#[cfg_attr(feature = "stm32f429ag", path = "stm32f429ag.rs")] -#[cfg_attr(feature = "stm32f429ai", path = "stm32f429ai.rs")] -#[cfg_attr(feature = "stm32f429be", path = "stm32f429be.rs")] -#[cfg_attr(feature = "stm32f429bg", path = "stm32f429bg.rs")] -#[cfg_attr(feature = "stm32f429bi", path = "stm32f429bi.rs")] -#[cfg_attr(feature = "stm32f429ie", path = "stm32f429ie.rs")] -#[cfg_attr(feature = "stm32f429ig", path = "stm32f429ig.rs")] -#[cfg_attr(feature = "stm32f429ii", path = "stm32f429ii.rs")] -#[cfg_attr(feature = "stm32f429ne", path = "stm32f429ne.rs")] -#[cfg_attr(feature = "stm32f429ng", path = "stm32f429ng.rs")] -#[cfg_attr(feature = "stm32f429ni", path = "stm32f429ni.rs")] -#[cfg_attr(feature = "stm32f429ve", path = "stm32f429ve.rs")] -#[cfg_attr(feature = "stm32f429vg", path = "stm32f429vg.rs")] -#[cfg_attr(feature = "stm32f429vi", path = "stm32f429vi.rs")] -#[cfg_attr(feature = "stm32f429ze", path = "stm32f429ze.rs")] -#[cfg_attr(feature = "stm32f429zg", path = "stm32f429zg.rs")] -#[cfg_attr(feature = "stm32f429zi", path = "stm32f429zi.rs")] -#[cfg_attr(feature = "stm32f437ai", path = "stm32f437ai.rs")] -#[cfg_attr(feature = "stm32f437ig", path = "stm32f437ig.rs")] -#[cfg_attr(feature = "stm32f437ii", path = "stm32f437ii.rs")] -#[cfg_attr(feature = "stm32f437vg", path = "stm32f437vg.rs")] -#[cfg_attr(feature = "stm32f437vi", path = "stm32f437vi.rs")] -#[cfg_attr(feature = "stm32f437zg", path = "stm32f437zg.rs")] -#[cfg_attr(feature = "stm32f437zi", path = "stm32f437zi.rs")] -#[cfg_attr(feature = "stm32f439ai", path = "stm32f439ai.rs")] -#[cfg_attr(feature = "stm32f439bg", path = "stm32f439bg.rs")] -#[cfg_attr(feature = "stm32f439bi", path = "stm32f439bi.rs")] -#[cfg_attr(feature = "stm32f439ig", path = "stm32f439ig.rs")] -#[cfg_attr(feature = "stm32f439ii", path = "stm32f439ii.rs")] -#[cfg_attr(feature = "stm32f439ng", path = "stm32f439ng.rs")] -#[cfg_attr(feature = "stm32f439ni", path = "stm32f439ni.rs")] -#[cfg_attr(feature = "stm32f439vg", path = "stm32f439vg.rs")] -#[cfg_attr(feature = "stm32f439vi", path = "stm32f439vi.rs")] -#[cfg_attr(feature = "stm32f439zg", path = "stm32f439zg.rs")] -#[cfg_attr(feature = "stm32f439zi", path = "stm32f439zi.rs")] -#[cfg_attr(feature = "stm32f446mc", path = "stm32f446mc.rs")] -#[cfg_attr(feature = "stm32f446me", path = "stm32f446me.rs")] -#[cfg_attr(feature = "stm32f446rc", path = "stm32f446rc.rs")] -#[cfg_attr(feature = "stm32f446re", path = "stm32f446re.rs")] -#[cfg_attr(feature = "stm32f446vc", path = "stm32f446vc.rs")] -#[cfg_attr(feature = "stm32f446ve", path = "stm32f446ve.rs")] -#[cfg_attr(feature = "stm32f446zc", path = "stm32f446zc.rs")] -#[cfg_attr(feature = "stm32f446ze", path = "stm32f446ze.rs")] -#[cfg_attr(feature = "stm32f469ae", path = "stm32f469ae.rs")] -#[cfg_attr(feature = "stm32f469ag", path = "stm32f469ag.rs")] -#[cfg_attr(feature = "stm32f469ai", path = "stm32f469ai.rs")] -#[cfg_attr(feature = "stm32f469be", path = "stm32f469be.rs")] -#[cfg_attr(feature = "stm32f469bg", path = "stm32f469bg.rs")] -#[cfg_attr(feature = "stm32f469bi", path = "stm32f469bi.rs")] -#[cfg_attr(feature = "stm32f469ie", path = "stm32f469ie.rs")] -#[cfg_attr(feature = "stm32f469ig", path = "stm32f469ig.rs")] -#[cfg_attr(feature = "stm32f469ii", path = "stm32f469ii.rs")] -#[cfg_attr(feature = "stm32f469ne", path = "stm32f469ne.rs")] -#[cfg_attr(feature = "stm32f469ng", path = "stm32f469ng.rs")] -#[cfg_attr(feature = "stm32f469ni", path = "stm32f469ni.rs")] -#[cfg_attr(feature = "stm32f469ve", path = "stm32f469ve.rs")] -#[cfg_attr(feature = "stm32f469vg", path = "stm32f469vg.rs")] -#[cfg_attr(feature = "stm32f469vi", path = "stm32f469vi.rs")] -#[cfg_attr(feature = "stm32f469ze", path = "stm32f469ze.rs")] -#[cfg_attr(feature = "stm32f469zg", path = "stm32f469zg.rs")] -#[cfg_attr(feature = "stm32f469zi", path = "stm32f469zi.rs")] -#[cfg_attr(feature = "stm32f479ag", path = "stm32f479ag.rs")] -#[cfg_attr(feature = "stm32f479ai", path = "stm32f479ai.rs")] -#[cfg_attr(feature = "stm32f479bg", path = "stm32f479bg.rs")] -#[cfg_attr(feature = "stm32f479bi", path = "stm32f479bi.rs")] -#[cfg_attr(feature = "stm32f479ig", path = "stm32f479ig.rs")] -#[cfg_attr(feature = "stm32f479ii", path = "stm32f479ii.rs")] -#[cfg_attr(feature = "stm32f479ng", path = "stm32f479ng.rs")] -#[cfg_attr(feature = "stm32f479ni", path = "stm32f479ni.rs")] -#[cfg_attr(feature = "stm32f479vg", path = "stm32f479vg.rs")] -#[cfg_attr(feature = "stm32f479vi", path = "stm32f479vi.rs")] -#[cfg_attr(feature = "stm32f479zg", path = "stm32f479zg.rs")] -#[cfg_attr(feature = "stm32f479zi", path = "stm32f479zi.rs")] -#[cfg_attr(feature = "stm32l412c8", path = "stm32l412c8.rs")] -#[cfg_attr(feature = "stm32l412cb", path = "stm32l412cb.rs")] -#[cfg_attr(feature = "stm32l412k8", path = "stm32l412k8.rs")] -#[cfg_attr(feature = "stm32l412kb", path = "stm32l412kb.rs")] -#[cfg_attr(feature = "stm32l412r8", path = "stm32l412r8.rs")] -#[cfg_attr(feature = "stm32l412rb", path = "stm32l412rb.rs")] -#[cfg_attr(feature = "stm32l412t8", path = "stm32l412t8.rs")] -#[cfg_attr(feature = "stm32l412tb", path = "stm32l412tb.rs")] -#[cfg_attr(feature = "stm32l422cb", path = "stm32l422cb.rs")] -#[cfg_attr(feature = "stm32l422kb", path = "stm32l422kb.rs")] -#[cfg_attr(feature = "stm32l422rb", path = "stm32l422rb.rs")] -#[cfg_attr(feature = "stm32l422tb", path = "stm32l422tb.rs")] -#[cfg_attr(feature = "stm32l431cb", path = "stm32l431cb.rs")] -#[cfg_attr(feature = "stm32l431cc", path = "stm32l431cc.rs")] -#[cfg_attr(feature = "stm32l431kb", path = "stm32l431kb.rs")] -#[cfg_attr(feature = "stm32l431kc", path = "stm32l431kc.rs")] -#[cfg_attr(feature = "stm32l431rb", path = "stm32l431rb.rs")] -#[cfg_attr(feature = "stm32l431rc", path = "stm32l431rc.rs")] -#[cfg_attr(feature = "stm32l431vc", path = "stm32l431vc.rs")] -#[cfg_attr(feature = "stm32l432kb", path = "stm32l432kb.rs")] -#[cfg_attr(feature = "stm32l432kc", path = "stm32l432kc.rs")] -#[cfg_attr(feature = "stm32l433cb", path = "stm32l433cb.rs")] -#[cfg_attr(feature = "stm32l433cc", path = "stm32l433cc.rs")] -#[cfg_attr(feature = "stm32l433rb", path = "stm32l433rb.rs")] -#[cfg_attr(feature = "stm32l433rc", path = "stm32l433rc.rs")] -#[cfg_attr(feature = "stm32l433vc", path = "stm32l433vc.rs")] -#[cfg_attr(feature = "stm32l442kc", path = "stm32l442kc.rs")] -#[cfg_attr(feature = "stm32l443cc", path = "stm32l443cc.rs")] -#[cfg_attr(feature = "stm32l443rc", path = "stm32l443rc.rs")] -#[cfg_attr(feature = "stm32l443vc", path = "stm32l443vc.rs")] -#[cfg_attr(feature = "stm32l451cc", path = "stm32l451cc.rs")] -#[cfg_attr(feature = "stm32l451ce", path = "stm32l451ce.rs")] -#[cfg_attr(feature = "stm32l451rc", path = "stm32l451rc.rs")] -#[cfg_attr(feature = "stm32l451re", path = "stm32l451re.rs")] -#[cfg_attr(feature = "stm32l451vc", path = "stm32l451vc.rs")] -#[cfg_attr(feature = "stm32l451ve", path = "stm32l451ve.rs")] -#[cfg_attr(feature = "stm32l452cc", path = "stm32l452cc.rs")] -#[cfg_attr(feature = "stm32l452ce", path = "stm32l452ce.rs")] -#[cfg_attr(feature = "stm32l452rc", path = "stm32l452rc.rs")] -#[cfg_attr(feature = "stm32l452re", path = "stm32l452re.rs")] -#[cfg_attr(feature = "stm32l452vc", path = "stm32l452vc.rs")] -#[cfg_attr(feature = "stm32l452ve", path = "stm32l452ve.rs")] -#[cfg_attr(feature = "stm32l462ce", path = "stm32l462ce.rs")] -#[cfg_attr(feature = "stm32l462re", path = "stm32l462re.rs")] -#[cfg_attr(feature = "stm32l462ve", path = "stm32l462ve.rs")] -#[cfg_attr(feature = "stm32l471qe", path = "stm32l471qe.rs")] -#[cfg_attr(feature = "stm32l471qg", path = "stm32l471qg.rs")] -#[cfg_attr(feature = "stm32l471re", path = "stm32l471re.rs")] -#[cfg_attr(feature = "stm32l471rg", path = "stm32l471rg.rs")] -#[cfg_attr(feature = "stm32l471ve", path = "stm32l471ve.rs")] -#[cfg_attr(feature = "stm32l471vg", path = "stm32l471vg.rs")] -#[cfg_attr(feature = "stm32l471ze", path = "stm32l471ze.rs")] -#[cfg_attr(feature = "stm32l471zg", path = "stm32l471zg.rs")] -#[cfg_attr(feature = "stm32l475rc", path = "stm32l475rc.rs")] -#[cfg_attr(feature = "stm32l475re", path = "stm32l475re.rs")] -#[cfg_attr(feature = "stm32l475rg", path = "stm32l475rg.rs")] -#[cfg_attr(feature = "stm32l475vc", path = "stm32l475vc.rs")] -#[cfg_attr(feature = "stm32l475ve", path = "stm32l475ve.rs")] -#[cfg_attr(feature = "stm32l475vg", path = "stm32l475vg.rs")] -#[cfg_attr(feature = "stm32l476je", path = "stm32l476je.rs")] -#[cfg_attr(feature = "stm32l476jg", path = "stm32l476jg.rs")] -#[cfg_attr(feature = "stm32l476me", path = "stm32l476me.rs")] -#[cfg_attr(feature = "stm32l476mg", path = "stm32l476mg.rs")] -#[cfg_attr(feature = "stm32l476qe", path = "stm32l476qe.rs")] -#[cfg_attr(feature = "stm32l476qg", path = "stm32l476qg.rs")] -#[cfg_attr(feature = "stm32l476rc", path = "stm32l476rc.rs")] -#[cfg_attr(feature = "stm32l476re", path = "stm32l476re.rs")] -#[cfg_attr(feature = "stm32l476rg", path = "stm32l476rg.rs")] -#[cfg_attr(feature = "stm32l476vc", path = "stm32l476vc.rs")] -#[cfg_attr(feature = "stm32l476ve", path = "stm32l476ve.rs")] -#[cfg_attr(feature = "stm32l476vg", path = "stm32l476vg.rs")] -#[cfg_attr(feature = "stm32l476ze", path = "stm32l476ze.rs")] -#[cfg_attr(feature = "stm32l476zg", path = "stm32l476zg.rs")] -#[cfg_attr(feature = "stm32l485jc", path = "stm32l485jc.rs")] -#[cfg_attr(feature = "stm32l485je", path = "stm32l485je.rs")] -#[cfg_attr(feature = "stm32l486jg", path = "stm32l486jg.rs")] -#[cfg_attr(feature = "stm32l486qg", path = "stm32l486qg.rs")] -#[cfg_attr(feature = "stm32l486rg", path = "stm32l486rg.rs")] -#[cfg_attr(feature = "stm32l486vg", path = "stm32l486vg.rs")] -#[cfg_attr(feature = "stm32l486zg", path = "stm32l486zg.rs")] -#[cfg_attr(feature = "stm32l496ae", path = "stm32l496ae.rs")] -#[cfg_attr(feature = "stm32l496ag", path = "stm32l496ag.rs")] -#[cfg_attr(feature = "stm32l496qe", path = "stm32l496qe.rs")] -#[cfg_attr(feature = "stm32l496qg", path = "stm32l496qg.rs")] -#[cfg_attr(feature = "stm32l496re", path = "stm32l496re.rs")] -#[cfg_attr(feature = "stm32l496rg", path = "stm32l496rg.rs")] -#[cfg_attr(feature = "stm32l496ve", path = "stm32l496ve.rs")] -#[cfg_attr(feature = "stm32l496vg", path = "stm32l496vg.rs")] -#[cfg_attr(feature = "stm32l496wg", path = "stm32l496wg.rs")] -#[cfg_attr(feature = "stm32l496ze", path = "stm32l496ze.rs")] -#[cfg_attr(feature = "stm32l496zg", path = "stm32l496zg.rs")] -#[cfg_attr(feature = "stm32l4a6ag", path = "stm32l4a6ag.rs")] -#[cfg_attr(feature = "stm32l4a6qg", path = "stm32l4a6qg.rs")] -#[cfg_attr(feature = "stm32l4a6rg", path = "stm32l4a6rg.rs")] -#[cfg_attr(feature = "stm32l4a6vg", path = "stm32l4a6vg.rs")] -#[cfg_attr(feature = "stm32l4a6zg", path = "stm32l4a6zg.rs")] -#[cfg_attr(feature = "stm32l4p5ae", path = "stm32l4p5ae.rs")] -#[cfg_attr(feature = "stm32l4p5ag", path = "stm32l4p5ag.rs")] -#[cfg_attr(feature = "stm32l4p5ce", path = "stm32l4p5ce.rs")] -#[cfg_attr(feature = "stm32l4p5cg", path = "stm32l4p5cg.rs")] -#[cfg_attr(feature = "stm32l4p5qe", path = "stm32l4p5qe.rs")] -#[cfg_attr(feature = "stm32l4p5qg", path = "stm32l4p5qg.rs")] -#[cfg_attr(feature = "stm32l4p5re", path = "stm32l4p5re.rs")] -#[cfg_attr(feature = "stm32l4p5rg", path = "stm32l4p5rg.rs")] -#[cfg_attr(feature = "stm32l4p5ve", path = "stm32l4p5ve.rs")] -#[cfg_attr(feature = "stm32l4p5vg", path = "stm32l4p5vg.rs")] -#[cfg_attr(feature = "stm32l4p5ze", path = "stm32l4p5ze.rs")] -#[cfg_attr(feature = "stm32l4p5zg", path = "stm32l4p5zg.rs")] -#[cfg_attr(feature = "stm32l4q5ag", path = "stm32l4q5ag.rs")] -#[cfg_attr(feature = "stm32l4q5cg", path = "stm32l4q5cg.rs")] -#[cfg_attr(feature = "stm32l4q5qg", path = "stm32l4q5qg.rs")] -#[cfg_attr(feature = "stm32l4q5rg", path = "stm32l4q5rg.rs")] -#[cfg_attr(feature = "stm32l4q5vg", path = "stm32l4q5vg.rs")] -#[cfg_attr(feature = "stm32l4q5zg", path = "stm32l4q5zg.rs")] -#[cfg_attr(feature = "stm32l4r5ag", path = "stm32l4r5ag.rs")] -#[cfg_attr(feature = "stm32l4r5ai", path = "stm32l4r5ai.rs")] -#[cfg_attr(feature = "stm32l4r5qg", path = "stm32l4r5qg.rs")] -#[cfg_attr(feature = "stm32l4r5qi", path = "stm32l4r5qi.rs")] -#[cfg_attr(feature = "stm32l4r5vg", path = "stm32l4r5vg.rs")] -#[cfg_attr(feature = "stm32l4r5vi", path = "stm32l4r5vi.rs")] -#[cfg_attr(feature = "stm32l4r5zg", path = "stm32l4r5zg.rs")] -#[cfg_attr(feature = "stm32l4r5zi", path = "stm32l4r5zi.rs")] -#[cfg_attr(feature = "stm32l4r7ai", path = "stm32l4r7ai.rs")] -#[cfg_attr(feature = "stm32l4r7vi", path = "stm32l4r7vi.rs")] -#[cfg_attr(feature = "stm32l4r7zi", path = "stm32l4r7zi.rs")] -#[cfg_attr(feature = "stm32l4r9ag", path = "stm32l4r9ag.rs")] -#[cfg_attr(feature = "stm32l4r9ai", path = "stm32l4r9ai.rs")] -#[cfg_attr(feature = "stm32l4r9vg", path = "stm32l4r9vg.rs")] -#[cfg_attr(feature = "stm32l4r9vi", path = "stm32l4r9vi.rs")] -#[cfg_attr(feature = "stm32l4r9zg", path = "stm32l4r9zg.rs")] -#[cfg_attr(feature = "stm32l4r9zi", path = "stm32l4r9zi.rs")] -#[cfg_attr(feature = "stm32l4s5ai", path = "stm32l4s5ai.rs")] -#[cfg_attr(feature = "stm32l4s5qi", path = "stm32l4s5qi.rs")] -#[cfg_attr(feature = "stm32l4s5vi", path = "stm32l4s5vi.rs")] -#[cfg_attr(feature = "stm32l4s5zi", path = "stm32l4s5zi.rs")] -#[cfg_attr(feature = "stm32l4s7ai", path = "stm32l4s7ai.rs")] -#[cfg_attr(feature = "stm32l4s7vi", path = "stm32l4s7vi.rs")] -#[cfg_attr(feature = "stm32l4s7zi", path = "stm32l4s7zi.rs")] -#[cfg_attr(feature = "stm32l4s9ai", path = "stm32l4s9ai.rs")] -#[cfg_attr(feature = "stm32l4s9vi", path = "stm32l4s9vi.rs")] -#[cfg_attr(feature = "stm32l4s9zi", path = "stm32l4s9zi.rs")] -mod chip; -pub use chip::*; diff --git a/embassy-stm32/src/chip/stm32f401cb.rs b/embassy-stm32/src/chip/stm32f401cb.rs deleted file mode 100644 index 027fef5a2..000000000 --- a/embassy-stm32/src/chip/stm32f401cb.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3, - TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401cc.rs b/embassy-stm32/src/chip/stm32f401cc.rs deleted file mode 100644 index 027fef5a2..000000000 --- a/embassy-stm32/src/chip/stm32f401cc.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3, - TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401cd.rs b/embassy-stm32/src/chip/stm32f401cd.rs deleted file mode 100644 index 027fef5a2..000000000 --- a/embassy-stm32/src/chip/stm32f401cd.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3, - TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401ce.rs b/embassy-stm32/src/chip/stm32f401ce.rs deleted file mode 100644 index 027fef5a2..000000000 --- a/embassy-stm32/src/chip/stm32f401ce.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, TIM3, - TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401rb.rs b/embassy-stm32/src/chip/stm32f401rb.rs deleted file mode 100644 index 163900e93..000000000 --- a/embassy-stm32/src/chip/stm32f401rb.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, - TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401rc.rs b/embassy-stm32/src/chip/stm32f401rc.rs deleted file mode 100644 index 163900e93..000000000 --- a/embassy-stm32/src/chip/stm32f401rc.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, - TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401rd.rs b/embassy-stm32/src/chip/stm32f401rd.rs deleted file mode 100644 index 163900e93..000000000 --- a/embassy-stm32/src/chip/stm32f401rd.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, - TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401re.rs b/embassy-stm32/src/chip/stm32f401re.rs deleted file mode 100644 index 163900e93..000000000 --- a/embassy-stm32/src/chip/stm32f401re.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM2, - TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401vb.rs b/embassy-stm32/src/chip/stm32f401vb.rs deleted file mode 100644 index 8976fb754..000000000 --- a/embassy-stm32/src/chip/stm32f401vb.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, - TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401vc.rs b/embassy-stm32/src/chip/stm32f401vc.rs deleted file mode 100644 index 8976fb754..000000000 --- a/embassy-stm32/src/chip/stm32f401vc.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, - TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401vd.rs b/embassy-stm32/src/chip/stm32f401vd.rs deleted file mode 100644 index 8976fb754..000000000 --- a/embassy-stm32/src/chip/stm32f401vd.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, - TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f401ve.rs b/embassy-stm32/src/chip/stm32f401ve.rs deleted file mode 100644 index 8976fb754..000000000 --- a/embassy-stm32/src/chip/stm32f401ve.rs +++ /dev/null @@ -1,466 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, - TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f405oe.rs b/embassy-stm32/src/chip/stm32f405oe.rs deleted file mode 100644 index 8cffccd9b..000000000 --- a/embassy-stm32/src/chip/stm32f405oe.rs +++ /dev/null @@ -1,613 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, - PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, - PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, - PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, - TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, - USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f405og.rs b/embassy-stm32/src/chip/stm32f405og.rs deleted file mode 100644 index 8cffccd9b..000000000 --- a/embassy-stm32/src/chip/stm32f405og.rs +++ /dev/null @@ -1,613 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, - PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, - PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, - PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, - TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, - USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f405rg.rs b/embassy-stm32/src/chip/stm32f405rg.rs deleted file mode 100644 index 8cffccd9b..000000000 --- a/embassy-stm32/src/chip/stm32f405rg.rs +++ /dev/null @@ -1,613 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, - PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, - PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, - PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, - TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, - USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f405vg.rs b/embassy-stm32/src/chip/stm32f405vg.rs deleted file mode 100644 index 8cffccd9b..000000000 --- a/embassy-stm32/src/chip/stm32f405vg.rs +++ /dev/null @@ -1,613 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, - PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, - PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, - PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, - TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, - USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f405zg.rs b/embassy-stm32/src/chip/stm32f405zg.rs deleted file mode 100644 index 8cffccd9b..000000000 --- a/embassy-stm32/src/chip/stm32f405zg.rs +++ /dev/null @@ -1,613 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, - PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, - PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, - PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, TIM11, - TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, - USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f407ie.rs b/embassy-stm32/src/chip/stm32f407ie.rs deleted file mode 100644 index f86038e1e..000000000 --- a/embassy-stm32/src/chip/stm32f407ie.rs +++ /dev/null @@ -1,622 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f407ig.rs b/embassy-stm32/src/chip/stm32f407ig.rs deleted file mode 100644 index f86038e1e..000000000 --- a/embassy-stm32/src/chip/stm32f407ig.rs +++ /dev/null @@ -1,622 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f407ve.rs b/embassy-stm32/src/chip/stm32f407ve.rs deleted file mode 100644 index f86038e1e..000000000 --- a/embassy-stm32/src/chip/stm32f407ve.rs +++ /dev/null @@ -1,622 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f407vg.rs b/embassy-stm32/src/chip/stm32f407vg.rs deleted file mode 100644 index f86038e1e..000000000 --- a/embassy-stm32/src/chip/stm32f407vg.rs +++ /dev/null @@ -1,622 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f407ze.rs b/embassy-stm32/src/chip/stm32f407ze.rs deleted file mode 100644 index f86038e1e..000000000 --- a/embassy-stm32/src/chip/stm32f407ze.rs +++ /dev/null @@ -1,622 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f407zg.rs b/embassy-stm32/src/chip/stm32f407zg.rs deleted file mode 100644 index f86038e1e..000000000 --- a/embassy-stm32/src/chip/stm32f407zg.rs +++ /dev/null @@ -1,622 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, ETH, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f410c8.rs b/embassy-stm32/src/chip/stm32f410c8.rs deleted file mode 100644 index 3b7a40d35..000000000 --- a/embassy-stm32/src/chip/stm32f410c8.rs +++ /dev/null @@ -1,431 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG, - TIM1, TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - LPTIM1 = 97, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP = 25, - TIM5 = 50, - TIM6_DAC = 54, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(LPTIM1); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn LPTIM1(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP(); - fn TIM5(); - fn TIM6_DAC(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 98] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { _handler: TIM1_UP }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x40080000); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f410cb.rs b/embassy-stm32/src/chip/stm32f410cb.rs deleted file mode 100644 index 3b7a40d35..000000000 --- a/embassy-stm32/src/chip/stm32f410cb.rs +++ /dev/null @@ -1,431 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG, - TIM1, TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - LPTIM1 = 97, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP = 25, - TIM5 = 50, - TIM6_DAC = 54, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(LPTIM1); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn LPTIM1(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP(); - fn TIM5(); - fn TIM6_DAC(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 98] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { _handler: TIM1_UP }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x40080000); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f410r8.rs b/embassy-stm32/src/chip/stm32f410r8.rs deleted file mode 100644 index 3b7a40d35..000000000 --- a/embassy-stm32/src/chip/stm32f410r8.rs +++ /dev/null @@ -1,431 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG, - TIM1, TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - LPTIM1 = 97, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP = 25, - TIM5 = 50, - TIM6_DAC = 54, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(LPTIM1); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn LPTIM1(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP(); - fn TIM5(); - fn TIM6_DAC(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 98] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { _handler: TIM1_UP }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x40080000); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f410rb.rs b/embassy-stm32/src/chip/stm32f410rb.rs deleted file mode 100644 index 3b7a40d35..000000000 --- a/embassy-stm32/src/chip/stm32f410rb.rs +++ /dev/null @@ -1,431 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SPI2, SPI5, SYSCFG, - TIM1, TIM11, TIM5, TIM6, TIM9, USART1, USART2, USART6, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - LPTIM1 = 97, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP = 25, - TIM5 = 50, - TIM6_DAC = 54, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(LPTIM1); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn LPTIM1(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP(); - fn TIM5(); - fn TIM6_DAC(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 98] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { _handler: TIM1_UP }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x40080000); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f410t8.rs b/embassy-stm32/src/chip/stm32f410t8.rs deleted file mode 100644 index e9035f1a3..000000000 --- a/embassy-stm32/src/chip/stm32f410t8.rs +++ /dev/null @@ -1,416 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SYSCFG, TIM1, TIM11, - TIM5, TIM6, TIM9, USART1, USART2, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - LPTIM1 = 97, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP = 25, - TIM5 = 50, - TIM6_DAC = 54, - USART1 = 37, - USART2 = 38, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(LPTIM1); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(USART1); - declare!(USART2); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn LPTIM1(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP(); - fn TIM5(); - fn TIM6_DAC(); - fn USART1(); - fn USART2(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 98] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { _handler: TIM1_UP }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _reserved: 0 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x40080000); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); diff --git a/embassy-stm32/src/chip/stm32f410tb.rs b/embassy-stm32/src/chip/stm32f410tb.rs deleted file mode 100644 index e9035f1a3..000000000 --- a/embassy-stm32/src/chip/stm32f410tb.rs +++ /dev/null @@ -1,416 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, IWDG, LPTIM1, RCC, RNG, RTC, SPI1, SYSCFG, TIM1, TIM11, - TIM5, TIM6, TIM9, USART1, USART2, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - LPTIM1 = 97, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP = 25, - TIM5 = 50, - TIM6_DAC = 54, - USART1 = 37, - USART2 = 38, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(LPTIM1); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(USART1); - declare!(USART2); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn LPTIM1(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP(); - fn TIM5(); - fn TIM6_DAC(); - fn USART1(); - fn USART2(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 98] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { _handler: TIM1_UP }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _reserved: 0 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x40080000); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); diff --git a/embassy-stm32/src/chip/stm32f411cc.rs b/embassy-stm32/src/chip/stm32f411cc.rs deleted file mode 100644 index 1cad69bae..000000000 --- a/embassy-stm32/src/chip/stm32f411cc.rs +++ /dev/null @@ -1,472 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, - TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 86] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f411ce.rs b/embassy-stm32/src/chip/stm32f411ce.rs deleted file mode 100644 index 1cad69bae..000000000 --- a/embassy-stm32/src/chip/stm32f411ce.rs +++ /dev/null @@ -1,472 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, - TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 86] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f411rc.rs b/embassy-stm32/src/chip/stm32f411rc.rs deleted file mode 100644 index 1cad69bae..000000000 --- a/embassy-stm32/src/chip/stm32f411rc.rs +++ /dev/null @@ -1,472 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, - TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 86] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f411re.rs b/embassy-stm32/src/chip/stm32f411re.rs deleted file mode 100644 index 1cad69bae..000000000 --- a/embassy-stm32/src/chip/stm32f411re.rs +++ /dev/null @@ -1,472 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, - TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 86] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f411vc.rs b/embassy-stm32/src/chip/stm32f411vc.rs deleted file mode 100644 index 1cad69bae..000000000 --- a/embassy-stm32/src/chip/stm32f411vc.rs +++ /dev/null @@ -1,472 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, - TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 86] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f411ve.rs b/embassy-stm32/src/chip/stm32f411ve.rs deleted file mode 100644 index 1cad69bae..000000000 --- a/embassy-stm32/src/chip/stm32f411ve.rs +++ /dev/null @@ -1,472 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, - PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, - PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, - PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, - PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, - PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, - I2C1, I2C2, I2C3, IWDG, RCC, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, - TIM11, TIM2, TIM3, TIM4, TIM5, TIM9, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - USART1 = 37, - USART2 = 38, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(USART1); - declare!(USART2); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn USART1(); - fn USART2(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 86] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f412ce.rs b/embassy-stm32/src/chip/stm32f412ce.rs deleted file mode 100644 index 5943ee391..000000000 --- a/embassy-stm32/src/chip/stm32f412ce.rs +++ /dev/null @@ -1,530 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, - PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, - PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, - PH11, PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, - SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6 = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f412cg.rs b/embassy-stm32/src/chip/stm32f412cg.rs deleted file mode 100644 index 5943ee391..000000000 --- a/embassy-stm32/src/chip/stm32f412cg.rs +++ /dev/null @@ -1,530 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, - PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, - PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, - PH11, PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, - SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6 = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f412re.rs b/embassy-stm32/src/chip/stm32f412re.rs deleted file mode 100644 index b668b84e8..000000000 --- a/embassy-stm32/src/chip/stm32f412re.rs +++ /dev/null @@ -1,560 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, - PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, - PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, - SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6 = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f412rg.rs b/embassy-stm32/src/chip/stm32f412rg.rs deleted file mode 100644 index b668b84e8..000000000 --- a/embassy-stm32/src/chip/stm32f412rg.rs +++ /dev/null @@ -1,560 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, - PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, - PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, - SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6 = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); diff --git a/embassy-stm32/src/chip/stm32f412ve.rs b/embassy-stm32/src/chip/stm32f412ve.rs deleted file mode 100644 index 2c3dda1c8..000000000 --- a/embassy-stm32/src/chip/stm32f412ve.rs +++ /dev/null @@ -1,618 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, - PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, - PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, - PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, - PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, - PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6 = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f412vg.rs b/embassy-stm32/src/chip/stm32f412vg.rs deleted file mode 100644 index 2c3dda1c8..000000000 --- a/embassy-stm32/src/chip/stm32f412vg.rs +++ /dev/null @@ -1,618 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, - PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, - PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, - PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, - PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, - PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6 = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f412ze.rs b/embassy-stm32/src/chip/stm32f412ze.rs deleted file mode 100644 index 2c3dda1c8..000000000 --- a/embassy-stm32/src/chip/stm32f412ze.rs +++ /dev/null @@ -1,618 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, - PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, - PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, - PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, - PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, - PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6 = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f412zg.rs b/embassy-stm32/src/chip/stm32f412zg.rs deleted file mode 100644 index 2c3dda1c8..000000000 --- a/embassy-stm32/src/chip/stm32f412zg.rs +++ /dev/null @@ -1,618 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, - PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, - PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, - PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, - PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, - PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6 = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f413cg.rs b/embassy-stm32/src/chip/stm32f413cg.rs deleted file mode 100644 index f15f2ed3c..000000000 --- a/embassy-stm32/src/chip/stm32f413cg.rs +++ /dev/null @@ -1,664 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f413ch.rs b/embassy-stm32/src/chip/stm32f413ch.rs deleted file mode 100644 index f15f2ed3c..000000000 --- a/embassy-stm32/src/chip/stm32f413ch.rs +++ /dev/null @@ -1,664 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f413mg.rs b/embassy-stm32/src/chip/stm32f413mg.rs deleted file mode 100644 index 7ea6dd58f..000000000 --- a/embassy-stm32/src/chip/stm32f413mg.rs +++ /dev/null @@ -1,679 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f413mh.rs b/embassy-stm32/src/chip/stm32f413mh.rs deleted file mode 100644 index 7ea6dd58f..000000000 --- a/embassy-stm32/src/chip/stm32f413mh.rs +++ /dev/null @@ -1,679 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f413rg.rs b/embassy-stm32/src/chip/stm32f413rg.rs deleted file mode 100644 index 7ea6dd58f..000000000 --- a/embassy-stm32/src/chip/stm32f413rg.rs +++ /dev/null @@ -1,679 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f413rh.rs b/embassy-stm32/src/chip/stm32f413rh.rs deleted file mode 100644 index 7ea6dd58f..000000000 --- a/embassy-stm32/src/chip/stm32f413rh.rs +++ /dev/null @@ -1,679 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f413vg.rs b/embassy-stm32/src/chip/stm32f413vg.rs deleted file mode 100644 index 1894feacb..000000000 --- a/embassy-stm32/src/chip/stm32f413vg.rs +++ /dev/null @@ -1,680 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3, - USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f413vh.rs b/embassy-stm32/src/chip/stm32f413vh.rs deleted file mode 100644 index 1894feacb..000000000 --- a/embassy-stm32/src/chip/stm32f413vh.rs +++ /dev/null @@ -1,680 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3, - USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f413zg.rs b/embassy-stm32/src/chip/stm32f413zg.rs deleted file mode 100644 index 1894feacb..000000000 --- a/embassy-stm32/src/chip/stm32f413zg.rs +++ /dev/null @@ -1,680 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3, - USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f413zh.rs b/embassy-stm32/src/chip/stm32f413zh.rs deleted file mode 100644 index 1894feacb..000000000 --- a/embassy-stm32/src/chip/stm32f413zh.rs +++ /dev/null @@ -1,680 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3, - USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f415og.rs b/embassy-stm32/src/chip/stm32f415og.rs deleted file mode 100644 index 1c3243ed1..000000000 --- a/embassy-stm32/src/chip/stm32f415og.rs +++ /dev/null @@ -1,616 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _reserved: 0 }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f415rg.rs b/embassy-stm32/src/chip/stm32f415rg.rs deleted file mode 100644 index 1c3243ed1..000000000 --- a/embassy-stm32/src/chip/stm32f415rg.rs +++ /dev/null @@ -1,616 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _reserved: 0 }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f415vg.rs b/embassy-stm32/src/chip/stm32f415vg.rs deleted file mode 100644 index 1c3243ed1..000000000 --- a/embassy-stm32/src/chip/stm32f415vg.rs +++ /dev/null @@ -1,616 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _reserved: 0 }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f415zg.rs b/embassy-stm32/src/chip/stm32f415zg.rs deleted file mode 100644 index 1c3243ed1..000000000 --- a/embassy-stm32/src/chip/stm32f415zg.rs +++ /dev/null @@ -1,616 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _reserved: 0 }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f417ie.rs b/embassy-stm32/src/chip/stm32f417ie.rs deleted file mode 100644 index f99ca7b1b..000000000 --- a/embassy-stm32/src/chip/stm32f417ie.rs +++ /dev/null @@ -1,625 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f417ig.rs b/embassy-stm32/src/chip/stm32f417ig.rs deleted file mode 100644 index f99ca7b1b..000000000 --- a/embassy-stm32/src/chip/stm32f417ig.rs +++ /dev/null @@ -1,625 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f417ve.rs b/embassy-stm32/src/chip/stm32f417ve.rs deleted file mode 100644 index f99ca7b1b..000000000 --- a/embassy-stm32/src/chip/stm32f417ve.rs +++ /dev/null @@ -1,625 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f417vg.rs b/embassy-stm32/src/chip/stm32f417vg.rs deleted file mode 100644 index f99ca7b1b..000000000 --- a/embassy-stm32/src/chip/stm32f417vg.rs +++ /dev/null @@ -1,625 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f417ze.rs b/embassy-stm32/src/chip/stm32f417ze.rs deleted file mode 100644 index f99ca7b1b..000000000 --- a/embassy-stm32/src/chip/stm32f417ze.rs +++ /dev/null @@ -1,625 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f417zg.rs b/embassy-stm32/src/chip/stm32f417zg.rs deleted file mode 100644 index f99ca7b1b..000000000 --- a/embassy-stm32/src/chip/stm32f417zg.rs +++ /dev/null @@ -1,625 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SDIO, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - FSMC = 48, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(FSMC); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn FSMC(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FSMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f423ch.rs b/embassy-stm32/src/chip/stm32f423ch.rs deleted file mode 100644 index 54d5dbae6..000000000 --- a/embassy-stm32/src/chip/stm32f423ch.rs +++ /dev/null @@ -1,667 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f423mh.rs b/embassy-stm32/src/chip/stm32f423mh.rs deleted file mode 100644 index a033c03ba..000000000 --- a/embassy-stm32/src/chip/stm32f423mh.rs +++ /dev/null @@ -1,682 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f423rh.rs b/embassy-stm32/src/chip/stm32f423rh.rs deleted file mode 100644 index a033c03ba..000000000 --- a/embassy-stm32/src/chip/stm32f423rh.rs +++ /dev/null @@ -1,682 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f423vh.rs b/embassy-stm32/src/chip/stm32f423vh.rs deleted file mode 100644 index 6f0c5bd6e..000000000 --- a/embassy-stm32/src/chip/stm32f423vh.rs +++ /dev/null @@ -1,683 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3, - USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f423zh.rs b/embassy-stm32/src/chip/stm32f423zh.rs deleted file mode 100644 index 6f0c5bd6e..000000000 --- a/embassy-stm32/src/chip/stm32f423zh.rs +++ /dev/null @@ -1,683 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, CAN2, CAN3, DAC, EXTI, FMPI2C1, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, - SPI3, SPI4, SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART10, UART4, UART5, UART7, UART8, UART9, USART1, USART2, USART3, - USART6, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CAN3_RX0 = 75, - CAN3_RX1 = 76, - CAN3_SCE = 77, - CAN3_TX = 74, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM2_FLT0 = 98, - DFSDM2_FLT1 = 99, - DFSDM2_FLT2 = 100, - DFSDM2_FLT3 = 101, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 97, - OTG_FS = 67, - OTG_FS_WKUP = 42, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART10 = 89, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - UART9 = 88, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CAN3_TX); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM2_FLT0); - declare!(DFSDM2_FLT1); - declare!(DFSDM2_FLT2); - declare!(DFSDM2_FLT3); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART10); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(UART9); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CAN3_RX0(); - fn CAN3_RX1(); - fn CAN3_SCE(); - fn CAN3_TX(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM2_FLT0(); - fn DFSDM2_FLT1(); - fn DFSDM2_FLT2(); - fn DFSDM2_FLT3(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART10(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn UART9(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 102] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _reserved: 0 }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: CAN3_TX }, - Vector { _handler: CAN3_RX0 }, - Vector { _handler: CAN3_RX1 }, - Vector { _handler: CAN3_SCE }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _handler: UART9 }, - Vector { _handler: UART10 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: QUADSPI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - Vector { _handler: LPTIM1 }, - Vector { - _handler: DFSDM2_FLT0, - }, - Vector { - _handler: DFSDM2_FLT1, - }, - Vector { - _handler: DFSDM2_FLT2, - }, - Vector { - _handler: DFSDM2_FLT3, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, TxPin, PA15, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, RxPin, PB3, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 8); -impl_usart_pin!(USART3, CtsPin, PB13, 8); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PA11, 8); -impl_usart_pin!(USART6, RxPin, PA12, 8); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f427ag.rs b/embassy-stm32/src/chip/stm32f427ag.rs deleted file mode 100644 index 9d2e19b80..000000000 --- a/embassy-stm32/src/chip/stm32f427ag.rs +++ /dev/null @@ -1,686 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f427ai.rs b/embassy-stm32/src/chip/stm32f427ai.rs deleted file mode 100644 index 9d2e19b80..000000000 --- a/embassy-stm32/src/chip/stm32f427ai.rs +++ /dev/null @@ -1,686 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f427ig.rs b/embassy-stm32/src/chip/stm32f427ig.rs deleted file mode 100644 index 2e18827e7..000000000 --- a/embassy-stm32/src/chip/stm32f427ig.rs +++ /dev/null @@ -1,686 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, - TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f427ii.rs b/embassy-stm32/src/chip/stm32f427ii.rs deleted file mode 100644 index 2e18827e7..000000000 --- a/embassy-stm32/src/chip/stm32f427ii.rs +++ /dev/null @@ -1,686 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, - TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f427vg.rs b/embassy-stm32/src/chip/stm32f427vg.rs deleted file mode 100644 index 67ee554a0..000000000 --- a/embassy-stm32/src/chip/stm32f427vg.rs +++ /dev/null @@ -1,686 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f427vi.rs b/embassy-stm32/src/chip/stm32f427vi.rs deleted file mode 100644 index 67ee554a0..000000000 --- a/embassy-stm32/src/chip/stm32f427vi.rs +++ /dev/null @@ -1,686 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, - TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, UART5, - UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f427zg.rs b/embassy-stm32/src/chip/stm32f427zg.rs deleted file mode 100644 index 2e18827e7..000000000 --- a/embassy-stm32/src/chip/stm32f427zg.rs +++ /dev/null @@ -1,686 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, - TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f427zi.rs b/embassy-stm32/src/chip/stm32f427zi.rs deleted file mode 100644 index 2e18827e7..000000000 --- a/embassy-stm32/src/chip/stm32f427zi.rs +++ /dev/null @@ -1,686 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, - TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429ag.rs b/embassy-stm32/src/chip/stm32f429ag.rs deleted file mode 100644 index 8ae247ad1..000000000 --- a/embassy-stm32/src/chip/stm32f429ag.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, - TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429ai.rs b/embassy-stm32/src/chip/stm32f429ai.rs deleted file mode 100644 index 8ae247ad1..000000000 --- a/embassy-stm32/src/chip/stm32f429ai.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, - TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429be.rs b/embassy-stm32/src/chip/stm32f429be.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429be.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429bg.rs b/embassy-stm32/src/chip/stm32f429bg.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429bg.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429bi.rs b/embassy-stm32/src/chip/stm32f429bi.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429bi.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429ie.rs b/embassy-stm32/src/chip/stm32f429ie.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429ie.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429ig.rs b/embassy-stm32/src/chip/stm32f429ig.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429ig.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429ii.rs b/embassy-stm32/src/chip/stm32f429ii.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429ii.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429ne.rs b/embassy-stm32/src/chip/stm32f429ne.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429ne.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429ng.rs b/embassy-stm32/src/chip/stm32f429ng.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429ng.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429ni.rs b/embassy-stm32/src/chip/stm32f429ni.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429ni.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429ve.rs b/embassy-stm32/src/chip/stm32f429ve.rs deleted file mode 100644 index 4b609740f..000000000 --- a/embassy-stm32/src/chip/stm32f429ve.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429vg.rs b/embassy-stm32/src/chip/stm32f429vg.rs deleted file mode 100644 index 4b609740f..000000000 --- a/embassy-stm32/src/chip/stm32f429vg.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429vi.rs b/embassy-stm32/src/chip/stm32f429vi.rs deleted file mode 100644 index 4b609740f..000000000 --- a/embassy-stm32/src/chip/stm32f429vi.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, TIM1, - TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429ze.rs b/embassy-stm32/src/chip/stm32f429ze.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429ze.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429zg.rs b/embassy-stm32/src/chip/stm32f429zg.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429zg.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f429zi.rs b/embassy-stm32/src/chip/stm32f429zi.rs deleted file mode 100644 index a1c7ae71b..000000000 --- a/embassy-stm32/src/chip/stm32f429zi.rs +++ /dev/null @@ -1,692 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f437ai.rs b/embassy-stm32/src/chip/stm32f437ai.rs deleted file mode 100644 index 8b1eb9e33..000000000 --- a/embassy-stm32/src/chip/stm32f437ai.rs +++ /dev/null @@ -1,689 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f437ig.rs b/embassy-stm32/src/chip/stm32f437ig.rs deleted file mode 100644 index 198585d78..000000000 --- a/embassy-stm32/src/chip/stm32f437ig.rs +++ /dev/null @@ -1,690 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f437ii.rs b/embassy-stm32/src/chip/stm32f437ii.rs deleted file mode 100644 index 198585d78..000000000 --- a/embassy-stm32/src/chip/stm32f437ii.rs +++ /dev/null @@ -1,690 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f437vg.rs b/embassy-stm32/src/chip/stm32f437vg.rs deleted file mode 100644 index b1d2e290f..000000000 --- a/embassy-stm32/src/chip/stm32f437vg.rs +++ /dev/null @@ -1,689 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, - TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f437vi.rs b/embassy-stm32/src/chip/stm32f437vi.rs deleted file mode 100644 index b1d2e290f..000000000 --- a/embassy-stm32/src/chip/stm32f437vi.rs +++ /dev/null @@ -1,689 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SYSCFG, - TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM9, UART4, - UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f437zg.rs b/embassy-stm32/src/chip/stm32f437zg.rs deleted file mode 100644 index 198585d78..000000000 --- a/embassy-stm32/src/chip/stm32f437zg.rs +++ /dev/null @@ -1,690 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f437zi.rs b/embassy-stm32/src/chip/stm32f437zi.rs deleted file mode 100644 index 198585d78..000000000 --- a/embassy-stm32/src/chip/stm32f437zi.rs +++ /dev/null @@ -1,690 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439ai.rs b/embassy-stm32/src/chip/stm32f439ai.rs deleted file mode 100644 index b0ff8fa35..000000000 --- a/embassy-stm32/src/chip/stm32f439ai.rs +++ /dev/null @@ -1,696 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439bg.rs b/embassy-stm32/src/chip/stm32f439bg.rs deleted file mode 100644 index eec3a3f65..000000000 --- a/embassy-stm32/src/chip/stm32f439bg.rs +++ /dev/null @@ -1,696 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439bi.rs b/embassy-stm32/src/chip/stm32f439bi.rs deleted file mode 100644 index eec3a3f65..000000000 --- a/embassy-stm32/src/chip/stm32f439bi.rs +++ /dev/null @@ -1,696 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439ig.rs b/embassy-stm32/src/chip/stm32f439ig.rs deleted file mode 100644 index eec3a3f65..000000000 --- a/embassy-stm32/src/chip/stm32f439ig.rs +++ /dev/null @@ -1,696 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439ii.rs b/embassy-stm32/src/chip/stm32f439ii.rs deleted file mode 100644 index eec3a3f65..000000000 --- a/embassy-stm32/src/chip/stm32f439ii.rs +++ /dev/null @@ -1,696 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439ng.rs b/embassy-stm32/src/chip/stm32f439ng.rs deleted file mode 100644 index eec3a3f65..000000000 --- a/embassy-stm32/src/chip/stm32f439ng.rs +++ /dev/null @@ -1,696 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439ni.rs b/embassy-stm32/src/chip/stm32f439ni.rs deleted file mode 100644 index eec3a3f65..000000000 --- a/embassy-stm32/src/chip/stm32f439ni.rs +++ /dev/null @@ -1,696 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439vg.rs b/embassy-stm32/src/chip/stm32f439vg.rs deleted file mode 100644 index 8dfb7bdbc..000000000 --- a/embassy-stm32/src/chip/stm32f439vg.rs +++ /dev/null @@ -1,695 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439vi.rs b/embassy-stm32/src/chip/stm32f439vi.rs deleted file mode 100644 index 8dfb7bdbc..000000000 --- a/embassy-stm32/src/chip/stm32f439vi.rs +++ /dev/null @@ -1,695 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439zg.rs b/embassy-stm32/src/chip/stm32f439zg.rs deleted file mode 100644 index eec3a3f65..000000000 --- a/embassy-stm32/src/chip/stm32f439zg.rs +++ /dev/null @@ -1,696 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f439zi.rs b/embassy-stm32/src/chip/stm32f439zi.rs deleted file mode 100644 index eec3a3f65..000000000 --- a/embassy-stm32/src/chip/stm32f439zi.rs +++ /dev/null @@ -1,696 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, - TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f446mc.rs b/embassy-stm32/src/chip/stm32f446mc.rs deleted file mode 100644 index b4f048cab..000000000 --- a/embassy-stm32/src/chip/stm32f446mc.rs +++ /dev/null @@ -1,640 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, - SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CEC = 93, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SAI2 = 91, - SDIO = 49, - SPDIF_RX = 94, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CEC); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDIO); - declare!(SPDIF_RX); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CEC(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDIO(); - fn SPDIF_RX(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI2 }, - Vector { _handler: QUADSPI }, - Vector { _handler: CEC }, - Vector { _handler: SPDIF_RX }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f446me.rs b/embassy-stm32/src/chip/stm32f446me.rs deleted file mode 100644 index b4f048cab..000000000 --- a/embassy-stm32/src/chip/stm32f446me.rs +++ /dev/null @@ -1,640 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, - SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CEC = 93, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SAI2 = 91, - SDIO = 49, - SPDIF_RX = 94, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CEC); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDIO); - declare!(SPDIF_RX); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CEC(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDIO(); - fn SPDIF_RX(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI2 }, - Vector { _handler: QUADSPI }, - Vector { _handler: CEC }, - Vector { _handler: SPDIF_RX }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f446rc.rs b/embassy-stm32/src/chip/stm32f446rc.rs deleted file mode 100644 index 222dcfb80..000000000 --- a/embassy-stm32/src/chip/stm32f446rc.rs +++ /dev/null @@ -1,639 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SDIO, SPDIFRX, SPI1, SPI2, - SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CEC = 93, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SAI2 = 91, - SDIO = 49, - SPDIF_RX = 94, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CEC); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDIO); - declare!(SPDIF_RX); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CEC(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDIO(); - fn SPDIF_RX(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI2 }, - Vector { _handler: QUADSPI }, - Vector { _handler: CEC }, - Vector { _handler: SPDIF_RX }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f446re.rs b/embassy-stm32/src/chip/stm32f446re.rs deleted file mode 100644 index 222dcfb80..000000000 --- a/embassy-stm32/src/chip/stm32f446re.rs +++ /dev/null @@ -1,639 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SDIO, SPDIFRX, SPI1, SPI2, - SPI3, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CEC = 93, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SAI2 = 91, - SDIO = 49, - SPDIF_RX = 94, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CEC); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDIO); - declare!(SPDIF_RX); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CEC(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDIO(); - fn SPDIF_RX(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI2 }, - Vector { _handler: QUADSPI }, - Vector { _handler: CEC }, - Vector { _handler: SPDIF_RX }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f446vc.rs b/embassy-stm32/src/chip/stm32f446vc.rs deleted file mode 100644 index b4f048cab..000000000 --- a/embassy-stm32/src/chip/stm32f446vc.rs +++ /dev/null @@ -1,640 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, - SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CEC = 93, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SAI2 = 91, - SDIO = 49, - SPDIF_RX = 94, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CEC); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDIO); - declare!(SPDIF_RX); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CEC(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDIO(); - fn SPDIF_RX(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI2 }, - Vector { _handler: QUADSPI }, - Vector { _handler: CEC }, - Vector { _handler: SPDIF_RX }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f446ve.rs b/embassy-stm32/src/chip/stm32f446ve.rs deleted file mode 100644 index b4f048cab..000000000 --- a/embassy-stm32/src/chip/stm32f446ve.rs +++ /dev/null @@ -1,640 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, - SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CEC = 93, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SAI2 = 91, - SDIO = 49, - SPDIF_RX = 94, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CEC); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDIO); - declare!(SPDIF_RX); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CEC(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDIO(); - fn SPDIF_RX(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI2 }, - Vector { _handler: QUADSPI }, - Vector { _handler: CEC }, - Vector { _handler: SPDIF_RX }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f446zc.rs b/embassy-stm32/src/chip/stm32f446zc.rs deleted file mode 100644 index b4f048cab..000000000 --- a/embassy-stm32/src/chip/stm32f446zc.rs +++ /dev/null @@ -1,640 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, - SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CEC = 93, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SAI2 = 91, - SDIO = 49, - SPDIF_RX = 94, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CEC); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDIO); - declare!(SPDIF_RX); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CEC(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDIO(); - fn SPDIF_RX(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI2 }, - Vector { _handler: QUADSPI }, - Vector { _handler: CEC }, - Vector { _handler: SPDIF_RX }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f446ze.rs b/embassy-stm32/src/chip/stm32f446ze.rs deleted file mode 100644 index b4f048cab..000000000 --- a/embassy-stm32/src/chip/stm32f446ze.rs +++ /dev/null @@ -1,640 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, EXTI, FMPI2C1, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, QUADSPI, RCC, RTC, SAI1, SAI2, SDIO, SPDIFRX, SPI1, - SPI2, SPI3, SPI4, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CEC = 93, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FMPI2C1_ER = 96, - FMPI2C1_EV = 95, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 92, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SAI2 = 91, - SDIO = 49, - SPDIF_RX = 94, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CEC); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FMPI2C1_ER); - declare!(FMPI2C1_EV); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDIO); - declare!(SPDIF_RX); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CEC(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FMPI2C1_ER(); - fn FMPI2C1_EV(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDIO(); - fn SPDIF_RX(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 97] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: FPU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI4 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SAI2 }, - Vector { _handler: QUADSPI }, - Vector { _handler: CEC }, - Vector { _handler: SPDIF_RX }, - Vector { - _handler: FMPI2C1_EV, - }, - Vector { - _handler: FMPI2C1_ER, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, RxPin, PC5, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ae.rs b/embassy-stm32/src/chip/stm32f469ae.rs deleted file mode 100644 index 94e2689fc..000000000 --- a/embassy-stm32/src/chip/stm32f469ae.rs +++ /dev/null @@ -1,700 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ag.rs b/embassy-stm32/src/chip/stm32f469ag.rs deleted file mode 100644 index 94e2689fc..000000000 --- a/embassy-stm32/src/chip/stm32f469ag.rs +++ /dev/null @@ -1,700 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ai.rs b/embassy-stm32/src/chip/stm32f469ai.rs deleted file mode 100644 index 94e2689fc..000000000 --- a/embassy-stm32/src/chip/stm32f469ai.rs +++ /dev/null @@ -1,700 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI6, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469be.rs b/embassy-stm32/src/chip/stm32f469be.rs deleted file mode 100644 index ccfe25ded..000000000 --- a/embassy-stm32/src/chip/stm32f469be.rs +++ /dev/null @@ -1,701 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469bg.rs b/embassy-stm32/src/chip/stm32f469bg.rs deleted file mode 100644 index ccfe25ded..000000000 --- a/embassy-stm32/src/chip/stm32f469bg.rs +++ /dev/null @@ -1,701 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469bi.rs b/embassy-stm32/src/chip/stm32f469bi.rs deleted file mode 100644 index ccfe25ded..000000000 --- a/embassy-stm32/src/chip/stm32f469bi.rs +++ /dev/null @@ -1,701 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ie.rs b/embassy-stm32/src/chip/stm32f469ie.rs deleted file mode 100644 index ccfe25ded..000000000 --- a/embassy-stm32/src/chip/stm32f469ie.rs +++ /dev/null @@ -1,701 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ig.rs b/embassy-stm32/src/chip/stm32f469ig.rs deleted file mode 100644 index ccfe25ded..000000000 --- a/embassy-stm32/src/chip/stm32f469ig.rs +++ /dev/null @@ -1,701 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ii.rs b/embassy-stm32/src/chip/stm32f469ii.rs deleted file mode 100644 index ccfe25ded..000000000 --- a/embassy-stm32/src/chip/stm32f469ii.rs +++ /dev/null @@ -1,701 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ne.rs b/embassy-stm32/src/chip/stm32f469ne.rs deleted file mode 100644 index ccfe25ded..000000000 --- a/embassy-stm32/src/chip/stm32f469ne.rs +++ /dev/null @@ -1,701 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ng.rs b/embassy-stm32/src/chip/stm32f469ng.rs deleted file mode 100644 index ccfe25ded..000000000 --- a/embassy-stm32/src/chip/stm32f469ng.rs +++ /dev/null @@ -1,701 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ni.rs b/embassy-stm32/src/chip/stm32f469ni.rs deleted file mode 100644 index ccfe25ded..000000000 --- a/embassy-stm32/src/chip/stm32f469ni.rs +++ /dev/null @@ -1,701 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, ETH, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, SPI5, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ve.rs b/embassy-stm32/src/chip/stm32f469ve.rs deleted file mode 100644 index ef61f2bde..000000000 --- a/embassy-stm32/src/chip/stm32f469ve.rs +++ /dev/null @@ -1,700 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469vg.rs b/embassy-stm32/src/chip/stm32f469vg.rs deleted file mode 100644 index ef61f2bde..000000000 --- a/embassy-stm32/src/chip/stm32f469vg.rs +++ /dev/null @@ -1,700 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469vi.rs b/embassy-stm32/src/chip/stm32f469vi.rs deleted file mode 100644 index ef61f2bde..000000000 --- a/embassy-stm32/src/chip/stm32f469vi.rs +++ /dev/null @@ -1,700 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469ze.rs b/embassy-stm32/src/chip/stm32f469ze.rs deleted file mode 100644 index 569912a38..000000000 --- a/embassy-stm32/src/chip/stm32f469ze.rs +++ /dev/null @@ -1,700 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469zg.rs b/embassy-stm32/src/chip/stm32f469zg.rs deleted file mode 100644 index 569912a38..000000000 --- a/embassy-stm32/src/chip/stm32f469zg.rs +++ /dev/null @@ -1,700 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f469zi.rs b/embassy-stm32/src/chip/stm32f469zi.rs deleted file mode 100644 index 569912a38..000000000 --- a/embassy-stm32/src/chip/stm32f469zi.rs +++ /dev/null @@ -1,700 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, DAC, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479ag.rs b/embassy-stm32/src/chip/stm32f479ag.rs deleted file mode 100644 index 6cea1e1df..000000000 --- a/embassy-stm32/src/chip/stm32f479ag.rs +++ /dev/null @@ -1,704 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479ai.rs b/embassy-stm32/src/chip/stm32f479ai.rs deleted file mode 100644 index 6cea1e1df..000000000 --- a/embassy-stm32/src/chip/stm32f479ai.rs +++ /dev/null @@ -1,704 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, - TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479bg.rs b/embassy-stm32/src/chip/stm32f479bg.rs deleted file mode 100644 index 40a58618b..000000000 --- a/embassy-stm32/src/chip/stm32f479bg.rs +++ /dev/null @@ -1,704 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, - SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479bi.rs b/embassy-stm32/src/chip/stm32f479bi.rs deleted file mode 100644 index 40a58618b..000000000 --- a/embassy-stm32/src/chip/stm32f479bi.rs +++ /dev/null @@ -1,704 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, - SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479ig.rs b/embassy-stm32/src/chip/stm32f479ig.rs deleted file mode 100644 index 40a58618b..000000000 --- a/embassy-stm32/src/chip/stm32f479ig.rs +++ /dev/null @@ -1,704 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, - SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479ii.rs b/embassy-stm32/src/chip/stm32f479ii.rs deleted file mode 100644 index 40a58618b..000000000 --- a/embassy-stm32/src/chip/stm32f479ii.rs +++ /dev/null @@ -1,704 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, - SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479ng.rs b/embassy-stm32/src/chip/stm32f479ng.rs deleted file mode 100644 index 40a58618b..000000000 --- a/embassy-stm32/src/chip/stm32f479ng.rs +++ /dev/null @@ -1,704 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, - SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479ni.rs b/embassy-stm32/src/chip/stm32f479ni.rs deleted file mode 100644 index 40a58618b..000000000 --- a/embassy-stm32/src/chip/stm32f479ni.rs +++ /dev/null @@ -1,704 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, ETH, EXTI, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, - PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, - PK15, HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, - SPI4, SPI5, SPI6, SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, - TIM6, TIM7, TIM8, TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, - USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479vg.rs b/embassy-stm32/src/chip/stm32f479vg.rs deleted file mode 100644 index 25c960a4a..000000000 --- a/embassy-stm32/src/chip/stm32f479vg.rs +++ /dev/null @@ -1,703 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479vi.rs b/embassy-stm32/src/chip/stm32f479vi.rs deleted file mode 100644 index 25c960a4a..000000000 --- a/embassy-stm32/src/chip/stm32f479vi.rs +++ /dev/null @@ -1,703 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479zg.rs b/embassy-stm32/src/chip/stm32f479zg.rs deleted file mode 100644 index 7e5ee3245..000000000 --- a/embassy-stm32/src/chip/stm32f479zg.rs +++ /dev/null @@ -1,703 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32f479zi.rs b/embassy-stm32/src/chip/stm32f479zi.rs deleted file mode 100644 index 7e5ee3245..000000000 --- a/embassy-stm32/src/chip/stm32f479zi.rs +++ /dev/null @@ -1,703 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, CRYP, DAC, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, - PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, - HASH, I2C1, I2C2, I2C3, IWDG, LTDC, QUADSPI, RCC, RNG, RTC, SAI1, SDIO, SPI1, SPI2, SPI3, SPI4, - SYSCFG, TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, - TIM9, UART4, UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40013800; -pub const EXTI_BASE: usize = 0x40013c00; -pub const GPIO_BASE: usize = 0x40020000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 64, - CAN2_RX1 = 65, - CAN2_SCE = 66, - CAN2_TX = 63, - CRYP = 79, - DCMI = 78, - DMA1_Stream0 = 11, - DMA1_Stream1 = 12, - DMA1_Stream2 = 13, - DMA1_Stream3 = 14, - DMA1_Stream4 = 15, - DMA1_Stream5 = 16, - DMA1_Stream6 = 17, - DMA1_Stream7 = 47, - DMA2D = 90, - DMA2_Stream0 = 56, - DMA2_Stream1 = 57, - DMA2_Stream2 = 58, - DMA2_Stream3 = 59, - DMA2_Stream4 = 60, - DMA2_Stream5 = 68, - DMA2_Stream6 = 69, - DMA2_Stream7 = 70, - DSI = 92, - ETH = 61, - ETH_WKUP = 62, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LTDC = 88, - LTDC_ER = 89, - OTG_FS = 67, - OTG_FS_WKUP = 42, - OTG_HS = 77, - OTG_HS_EP1_IN = 75, - OTG_HS_EP1_OUT = 74, - OTG_HS_WKUP = 76, - PVD = 1, - QUADSPI = 91, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 87, - SDIO = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SPI4 = 84, - SPI5 = 85, - SPI6 = 86, - TAMP_STAMP = 2, - TIM1_BRK_TIM9 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM11 = 26, - TIM1_UP_TIM10 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK_TIM12 = 43, - TIM8_CC = 46, - TIM8_TRG_COM_TIM14 = 45, - TIM8_UP_TIM13 = 44, - UART4 = 52, - UART5 = 53, - UART7 = 82, - UART8 = 83, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USART6 = 71, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(CRYP); - declare!(DCMI); - declare!(DMA1_Stream0); - declare!(DMA1_Stream1); - declare!(DMA1_Stream2); - declare!(DMA1_Stream3); - declare!(DMA1_Stream4); - declare!(DMA1_Stream5); - declare!(DMA1_Stream6); - declare!(DMA1_Stream7); - declare!(DMA2D); - declare!(DMA2_Stream0); - declare!(DMA2_Stream1); - declare!(DMA2_Stream2); - declare!(DMA2_Stream3); - declare!(DMA2_Stream4); - declare!(DMA2_Stream5); - declare!(DMA2_Stream6); - declare!(DMA2_Stream7); - declare!(DSI); - declare!(ETH); - declare!(ETH_WKUP); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OTG_FS); - declare!(OTG_FS_WKUP); - declare!(OTG_HS); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_WKUP); - declare!(PVD); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDIO); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_UP_TIM10); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_UP_TIM13); - declare!(UART4); - declare!(UART5); - declare!(UART7); - declare!(UART8); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USART6); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn CRYP(); - fn DCMI(); - fn DMA1_Stream0(); - fn DMA1_Stream1(); - fn DMA1_Stream2(); - fn DMA1_Stream3(); - fn DMA1_Stream4(); - fn DMA1_Stream5(); - fn DMA1_Stream6(); - fn DMA1_Stream7(); - fn DMA2D(); - fn DMA2_Stream0(); - fn DMA2_Stream1(); - fn DMA2_Stream2(); - fn DMA2_Stream3(); - fn DMA2_Stream4(); - fn DMA2_Stream5(); - fn DMA2_Stream6(); - fn DMA2_Stream7(); - fn DSI(); - fn ETH(); - fn ETH_WKUP(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LTDC(); - fn LTDC_ER(); - fn OTG_FS(); - fn OTG_FS_WKUP(); - fn OTG_HS(); - fn OTG_HS_EP1_IN(); - fn OTG_HS_EP1_OUT(); - fn OTG_HS_WKUP(); - fn PVD(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDIO(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SPI4(); - fn SPI5(); - fn SPI6(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM9(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM11(); - fn TIM1_UP_TIM10(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK_TIM12(); - fn TIM8_CC(); - fn TIM8_TRG_COM_TIM14(); - fn TIM8_UP_TIM13(); - fn UART4(); - fn UART5(); - fn UART7(); - fn UART8(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USART6(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 93] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Stream0, - }, - Vector { - _handler: DMA1_Stream1, - }, - Vector { - _handler: DMA1_Stream2, - }, - Vector { - _handler: DMA1_Stream3, - }, - Vector { - _handler: DMA1_Stream4, - }, - Vector { - _handler: DMA1_Stream5, - }, - Vector { - _handler: DMA1_Stream6, - }, - Vector { _handler: ADC }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM9, - }, - Vector { - _handler: TIM1_UP_TIM10, - }, - Vector { - _handler: TIM1_TRG_COM_TIM11, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: OTG_FS_WKUP, - }, - Vector { - _handler: TIM8_BRK_TIM12, - }, - Vector { - _handler: TIM8_UP_TIM13, - }, - Vector { - _handler: TIM8_TRG_COM_TIM14, - }, - Vector { _handler: TIM8_CC }, - Vector { - _handler: DMA1_Stream7, - }, - Vector { _handler: FMC }, - Vector { _handler: SDIO }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Stream0, - }, - Vector { - _handler: DMA2_Stream1, - }, - Vector { - _handler: DMA2_Stream2, - }, - Vector { - _handler: DMA2_Stream3, - }, - Vector { - _handler: DMA2_Stream4, - }, - Vector { _handler: ETH }, - Vector { _handler: ETH_WKUP }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Stream5, - }, - Vector { - _handler: DMA2_Stream6, - }, - Vector { - _handler: DMA2_Stream7, - }, - Vector { _handler: USART6 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { - _handler: OTG_HS_EP1_OUT, - }, - Vector { - _handler: OTG_HS_EP1_IN, - }, - Vector { - _handler: OTG_HS_WKUP, - }, - Vector { _handler: OTG_HS }, - Vector { _handler: DCMI }, - Vector { _handler: CRYP }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: UART7 }, - Vector { _handler: UART8 }, - Vector { _handler: SPI4 }, - Vector { _handler: SPI5 }, - Vector { _handler: SPI6 }, - Vector { _handler: SAI1 }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: DMA2D }, - Vector { _handler: QUADSPI }, - Vector { _handler: DSI }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_gpio_pin!(PJ0, 9, 0, EXTI0); -impl_gpio_pin!(PJ1, 9, 1, EXTI1); -impl_gpio_pin!(PJ2, 9, 2, EXTI2); -impl_gpio_pin!(PJ3, 9, 3, EXTI3); -impl_gpio_pin!(PJ4, 9, 4, EXTI4); -impl_gpio_pin!(PJ5, 9, 5, EXTI5); -impl_gpio_pin!(PJ6, 9, 6, EXTI6); -impl_gpio_pin!(PJ7, 9, 7, EXTI7); -impl_gpio_pin!(PJ8, 9, 8, EXTI8); -impl_gpio_pin!(PJ9, 9, 9, EXTI9); -impl_gpio_pin!(PJ10, 9, 10, EXTI10); -impl_gpio_pin!(PJ11, 9, 11, EXTI11); -impl_gpio_pin!(PJ12, 9, 12, EXTI12); -impl_gpio_pin!(PJ13, 9, 13, EXTI13); -impl_gpio_pin!(PJ14, 9, 14, EXTI14); -impl_gpio_pin!(PJ15, 9, 15, EXTI15); -impl_gpio_pin!(PK0, 10, 0, EXTI0); -impl_gpio_pin!(PK1, 10, 1, EXTI1); -impl_gpio_pin!(PK2, 10, 2, EXTI2); -impl_gpio_pin!(PK3, 10, 3, EXTI3); -impl_gpio_pin!(PK4, 10, 4, EXTI4); -impl_gpio_pin!(PK5, 10, 5, EXTI5); -impl_gpio_pin!(PK6, 10, 6, EXTI6); -impl_gpio_pin!(PK7, 10, 7, EXTI7); -impl_gpio_pin!(PK8, 10, 8, EXTI8); -impl_gpio_pin!(PK9, 10, 9, EXTI9); -impl_gpio_pin!(PK10, 10, 10, EXTI10); -impl_gpio_pin!(PK11, 10, 11, EXTI11); -impl_gpio_pin!(PK12, 10, 12, EXTI12); -impl_gpio_pin!(PK13, 10, 13, EXTI13); -impl_gpio_pin!(PK14, 10, 14, EXTI14); -impl_gpio_pin!(PK15, 10, 15, EXTI15); -impl_rng!(0x50060800); -impl_usart!(USART1, 0x40011000); -impl_usart_pin!(USART1, RxPin, PA10, 7); -impl_usart_pin!(USART1, CtsPin, PA11, 7); -impl_usart_pin!(USART1, RtsPin, PA12, 7); -impl_usart_pin!(USART1, CkPin, PA8, 7); -impl_usart_pin!(USART1, TxPin, PA9, 7); -impl_usart_pin!(USART1, TxPin, PB6, 7); -impl_usart_pin!(USART1, RxPin, PB7, 7); -impl_usart!(USART2, 0x40004400); -impl_usart_pin!(USART2, CtsPin, PA0, 7); -impl_usart_pin!(USART2, RtsPin, PA1, 7); -impl_usart_pin!(USART2, TxPin, PA2, 7); -impl_usart_pin!(USART2, RxPin, PA3, 7); -impl_usart_pin!(USART2, CkPin, PA4, 7); -impl_usart_pin!(USART2, CtsPin, PD3, 7); -impl_usart_pin!(USART2, RtsPin, PD4, 7); -impl_usart_pin!(USART2, TxPin, PD5, 7); -impl_usart_pin!(USART2, RxPin, PD6, 7); -impl_usart_pin!(USART2, CkPin, PD7, 7); -impl_usart!(USART3, 0x40004800); -impl_usart_pin!(USART3, TxPin, PB10, 7); -impl_usart_pin!(USART3, RxPin, PB11, 7); -impl_usart_pin!(USART3, CkPin, PB12, 7); -impl_usart_pin!(USART3, CtsPin, PB13, 7); -impl_usart_pin!(USART3, RtsPin, PB14, 7); -impl_usart_pin!(USART3, TxPin, PC10, 7); -impl_usart_pin!(USART3, RxPin, PC11, 7); -impl_usart_pin!(USART3, CkPin, PC12, 7); -impl_usart_pin!(USART3, CkPin, PD10, 7); -impl_usart_pin!(USART3, CtsPin, PD11, 7); -impl_usart_pin!(USART3, RtsPin, PD12, 7); -impl_usart_pin!(USART3, TxPin, PD8, 7); -impl_usart_pin!(USART3, RxPin, PD9, 7); -impl_usart!(USART6, 0x40011400); -impl_usart_pin!(USART6, TxPin, PC6, 8); -impl_usart_pin!(USART6, RxPin, PC7, 8); -impl_usart_pin!(USART6, CkPin, PC8, 8); -impl_usart_pin!(USART6, RtsPin, PG12, 8); -impl_usart_pin!(USART6, CtsPin, PG13, 8); -impl_usart_pin!(USART6, TxPin, PG14, 8); -impl_usart_pin!(USART6, CtsPin, PG15, 8); -impl_usart_pin!(USART6, CkPin, PG7, 8); -impl_usart_pin!(USART6, RtsPin, PG8, 8); -impl_usart_pin!(USART6, RxPin, PG9, 8); diff --git a/embassy-stm32/src/chip/stm32l412c8.rs b/embassy-stm32/src/chip/stm32l412c8.rs deleted file mode 100644 index e319e06a7..000000000 --- a/embassy-stm32/src/chip/stm32l412c8.rs +++ /dev/null @@ -1,418 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412cb.rs b/embassy-stm32/src/chip/stm32l412cb.rs deleted file mode 100644 index e319e06a7..000000000 --- a/embassy-stm32/src/chip/stm32l412cb.rs +++ /dev/null @@ -1,418 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412k8.rs b/embassy-stm32/src/chip/stm32l412k8.rs deleted file mode 100644 index 88cc20b04..000000000 --- a/embassy-stm32/src/chip/stm32l412k8.rs +++ /dev/null @@ -1,417 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, - SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412kb.rs b/embassy-stm32/src/chip/stm32l412kb.rs deleted file mode 100644 index 88cc20b04..000000000 --- a/embassy-stm32/src/chip/stm32l412kb.rs +++ /dev/null @@ -1,417 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, - SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412r8.rs b/embassy-stm32/src/chip/stm32l412r8.rs deleted file mode 100644 index e319e06a7..000000000 --- a/embassy-stm32/src/chip/stm32l412r8.rs +++ /dev/null @@ -1,418 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412rb.rs b/embassy-stm32/src/chip/stm32l412rb.rs deleted file mode 100644 index e319e06a7..000000000 --- a/embassy-stm32/src/chip/stm32l412rb.rs +++ /dev/null @@ -1,418 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412t8.rs b/embassy-stm32/src/chip/stm32l412t8.rs deleted file mode 100644 index 88cc20b04..000000000 --- a/embassy-stm32/src/chip/stm32l412t8.rs +++ /dev/null @@ -1,417 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, - SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412tb.rs b/embassy-stm32/src/chip/stm32l412tb.rs deleted file mode 100644 index 88cc20b04..000000000 --- a/embassy-stm32/src/chip/stm32l412tb.rs +++ /dev/null @@ -1,417 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, - PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, - SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l422cb.rs b/embassy-stm32/src/chip/stm32l422cb.rs deleted file mode 100644 index 015b11be3..000000000 --- a/embassy-stm32/src/chip/stm32l422cb.rs +++ /dev/null @@ -1,421 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - AES = 79, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(AES); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn AES(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l422kb.rs b/embassy-stm32/src/chip/stm32l422kb.rs deleted file mode 100644 index 26decd09b..000000000 --- a/embassy-stm32/src/chip/stm32l422kb.rs +++ /dev/null @@ -1,420 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, - SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - AES = 79, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(AES); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn AES(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l422rb.rs b/embassy-stm32/src/chip/stm32l422rb.rs deleted file mode 100644 index 015b11be3..000000000 --- a/embassy-stm32/src/chip/stm32l422rb.rs +++ /dev/null @@ -1,421 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - AES = 79, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(AES); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn AES(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l422tb.rs b/embassy-stm32/src/chip/stm32l422tb.rs deleted file mode 100644 index 26decd09b..000000000 --- a/embassy-stm32/src/chip/stm32l422tb.rs +++ /dev/null @@ -1,420 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, - PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, - PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, - PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, - SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - AES = 79, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SPI1 = 35, - SPI2 = 36, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6 = 54, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(AES); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SPI1); - declare!(SPI2); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn AES(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SPI1(); - fn SPI2(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431cb.rs b/embassy-stm32/src/chip/stm32l431cb.rs deleted file mode 100644 index c4f33502f..000000000 --- a/embassy-stm32/src/chip/stm32l431cb.rs +++ /dev/null @@ -1,459 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, - USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431cc.rs b/embassy-stm32/src/chip/stm32l431cc.rs deleted file mode 100644 index c4f33502f..000000000 --- a/embassy-stm32/src/chip/stm32l431cc.rs +++ /dev/null @@ -1,459 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, - USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431kb.rs b/embassy-stm32/src/chip/stm32l431kb.rs deleted file mode 100644 index a55b3860f..000000000 --- a/embassy-stm32/src/chip/stm32l431kb.rs +++ /dev/null @@ -1,459 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, - SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, USART2, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431kc.rs b/embassy-stm32/src/chip/stm32l431kc.rs deleted file mode 100644 index a55b3860f..000000000 --- a/embassy-stm32/src/chip/stm32l431kc.rs +++ /dev/null @@ -1,459 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, - SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, USART2, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431rb.rs b/embassy-stm32/src/chip/stm32l431rb.rs deleted file mode 100644 index 902c4eb19..000000000 --- a/embassy-stm32/src/chip/stm32l431rb.rs +++ /dev/null @@ -1,459 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, - USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431rc.rs b/embassy-stm32/src/chip/stm32l431rc.rs deleted file mode 100644 index 902c4eb19..000000000 --- a/embassy-stm32/src/chip/stm32l431rc.rs +++ /dev/null @@ -1,459 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, - USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431vc.rs b/embassy-stm32/src/chip/stm32l431vc.rs deleted file mode 100644 index 902c4eb19..000000000 --- a/embassy-stm32/src/chip/stm32l431vc.rs +++ /dev/null @@ -1,459 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, - RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, - USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l432kb.rs b/embassy-stm32/src/chip/stm32l432kb.rs deleted file mode 100644 index 915bbbd6a..000000000 --- a/embassy-stm32/src/chip/stm32l432kb.rs +++ /dev/null @@ -1,413 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, - PH11, PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, - USART2, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SPI1 = 35, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SPI1); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SPI1(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI1 }, - Vector { _reserved: 0 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l432kc.rs b/embassy-stm32/src/chip/stm32l432kc.rs deleted file mode 100644 index 915bbbd6a..000000000 --- a/embassy-stm32/src/chip/stm32l432kc.rs +++ /dev/null @@ -1,413 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, - PH11, PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, - USART2, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SPI1 = 35, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SPI1); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SPI1(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI1 }, - Vector { _reserved: 0 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l433cb.rs b/embassy-stm32/src/chip/stm32l433cb.rs deleted file mode 100644 index 95313ffb0..000000000 --- a/embassy-stm32/src/chip/stm32l433cb.rs +++ /dev/null @@ -1,465 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, - USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l433cc.rs b/embassy-stm32/src/chip/stm32l433cc.rs deleted file mode 100644 index 95313ffb0..000000000 --- a/embassy-stm32/src/chip/stm32l433cc.rs +++ /dev/null @@ -1,465 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, - USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l433rb.rs b/embassy-stm32/src/chip/stm32l433rb.rs deleted file mode 100644 index 38d4b8310..000000000 --- a/embassy-stm32/src/chip/stm32l433rb.rs +++ /dev/null @@ -1,465 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, - TSC, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l433rc.rs b/embassy-stm32/src/chip/stm32l433rc.rs deleted file mode 100644 index 38d4b8310..000000000 --- a/embassy-stm32/src/chip/stm32l433rc.rs +++ /dev/null @@ -1,465 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, - TSC, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l433vc.rs b/embassy-stm32/src/chip/stm32l433vc.rs deleted file mode 100644 index 38d4b8310..000000000 --- a/embassy-stm32/src/chip/stm32l433vc.rs +++ /dev/null @@ -1,465 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, - TSC, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l442kc.rs b/embassy-stm32/src/chip/stm32l442kc.rs deleted file mode 100644 index 4837adef1..000000000 --- a/embassy-stm32/src/chip/stm32l442kc.rs +++ /dev/null @@ -1,416 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, - PH10, PH11, PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, - RCC, RNG, RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, - USART1, USART2, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SPI1 = 35, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SPI1); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SPI1(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI1 }, - Vector { _reserved: 0 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _reserved: 0 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l443cc.rs b/embassy-stm32/src/chip/stm32l443cc.rs deleted file mode 100644 index aa21e3322..000000000 --- a/embassy-stm32/src/chip/stm32l443cc.rs +++ /dev/null @@ -1,468 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, - RCC, RNG, RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, - TSC, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l443rc.rs b/embassy-stm32/src/chip/stm32l443rc.rs deleted file mode 100644 index f3139bc11..000000000 --- a/embassy-stm32/src/chip/stm32l443rc.rs +++ /dev/null @@ -1,468 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, - RCC, RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, - TIM7, TSC, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l443vc.rs b/embassy-stm32/src/chip/stm32l443vc.rs deleted file mode 100644 index f3139bc11..000000000 --- a/embassy-stm32/src/chip/stm32l443vc.rs +++ /dev/null @@ -1,468 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, - RCC, RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, - TIM7, TSC, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM6_DAC = 54, - TIM7 = 55, - TSC = 77, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TSC); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM6_DAC(); - fn TIM7(); - fn TSC(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 83] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451cc.rs b/embassy-stm32/src/chip/stm32l451cc.rs deleted file mode 100644 index 6d8463347..000000000 --- a/embassy-stm32/src/chip/stm32l451cc.rs +++ /dev/null @@ -1,477 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, - USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451ce.rs b/embassy-stm32/src/chip/stm32l451ce.rs deleted file mode 100644 index 6d8463347..000000000 --- a/embassy-stm32/src/chip/stm32l451ce.rs +++ /dev/null @@ -1,477 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, - USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451rc.rs b/embassy-stm32/src/chip/stm32l451rc.rs deleted file mode 100644 index 464fdc4ac..000000000 --- a/embassy-stm32/src/chip/stm32l451rc.rs +++ /dev/null @@ -1,477 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, - UART4, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451re.rs b/embassy-stm32/src/chip/stm32l451re.rs deleted file mode 100644 index 464fdc4ac..000000000 --- a/embassy-stm32/src/chip/stm32l451re.rs +++ /dev/null @@ -1,477 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, - UART4, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451vc.rs b/embassy-stm32/src/chip/stm32l451vc.rs deleted file mode 100644 index 464fdc4ac..000000000 --- a/embassy-stm32/src/chip/stm32l451vc.rs +++ /dev/null @@ -1,477 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, - UART4, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451ve.rs b/embassy-stm32/src/chip/stm32l451ve.rs deleted file mode 100644 index 464fdc4ac..000000000 --- a/embassy-stm32/src/chip/stm32l451ve.rs +++ /dev/null @@ -1,477 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, - UART4, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452cc.rs b/embassy-stm32/src/chip/stm32l452cc.rs deleted file mode 100644 index ef4a256e5..000000000 --- a/embassy-stm32/src/chip/stm32l452cc.rs +++ /dev/null @@ -1,480 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, - USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452ce.rs b/embassy-stm32/src/chip/stm32l452ce.rs deleted file mode 100644 index ef4a256e5..000000000 --- a/embassy-stm32/src/chip/stm32l452ce.rs +++ /dev/null @@ -1,480 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, - USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452rc.rs b/embassy-stm32/src/chip/stm32l452rc.rs deleted file mode 100644 index 05eaeda97..000000000 --- a/embassy-stm32/src/chip/stm32l452rc.rs +++ /dev/null @@ -1,480 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, - UART4, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452re.rs b/embassy-stm32/src/chip/stm32l452re.rs deleted file mode 100644 index 05eaeda97..000000000 --- a/embassy-stm32/src/chip/stm32l452re.rs +++ /dev/null @@ -1,480 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, - UART4, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452vc.rs b/embassy-stm32/src/chip/stm32l452vc.rs deleted file mode 100644 index 05eaeda97..000000000 --- a/embassy-stm32/src/chip/stm32l452vc.rs +++ /dev/null @@ -1,480 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, - UART4, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452ve.rs b/embassy-stm32/src/chip/stm32l452ve.rs deleted file mode 100644 index 05eaeda97..000000000 --- a/embassy-stm32/src/chip/stm32l452ve.rs +++ /dev/null @@ -1,480 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, PA5, - PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, - PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, - PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, - PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, - PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, - RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, - UART4, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l462ce.rs b/embassy-stm32/src/chip/stm32l462ce.rs deleted file mode 100644 index 65b8842cd..000000000 --- a/embassy-stm32/src/chip/stm32l462ce.rs +++ /dev/null @@ -1,483 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, - RCC, RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, - UART4, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l462re.rs b/embassy-stm32/src/chip/stm32l462re.rs deleted file mode 100644 index 4a4055b50..000000000 --- a/embassy-stm32/src/chip/stm32l462re.rs +++ /dev/null @@ -1,483 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, - RCC, RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, - TSC, UART4, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l462ve.rs b/embassy-stm32/src/chip/stm32l462ve.rs deleted file mode 100644 index 4a4055b50..000000000 --- a/embassy-stm32/src/chip/stm32l462ve.rs +++ /dev/null @@ -1,483 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, PA4, - PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, - PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, - PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, - RCC, RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, - TSC, UART4, USART1, USART2, USART3, USB, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM6_DAC = 54, - TSC = 77, - UART4 = 52, - USART1 = 37, - USART2 = 38, - USART3 = 39, - USB = 67, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TSC); - declare!(UART4); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(USB); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM6_DAC(); - fn TSC(); - fn UART4(); - fn USART1(); - fn USART2(); - fn USART3(); - fn USB(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 85] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _reserved: 0 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: SDMMC1 }, - Vector { _reserved: 0 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _reserved: 0 }, - Vector { _handler: TIM6_DAC }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: USB }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471qe.rs b/embassy-stm32/src/chip/stm32l471qe.rs deleted file mode 100644 index 192060c1f..000000000 --- a/embassy-stm32/src/chip/stm32l471qe.rs +++ /dev/null @@ -1,547 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471qg.rs b/embassy-stm32/src/chip/stm32l471qg.rs deleted file mode 100644 index 192060c1f..000000000 --- a/embassy-stm32/src/chip/stm32l471qg.rs +++ /dev/null @@ -1,547 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471re.rs b/embassy-stm32/src/chip/stm32l471re.rs deleted file mode 100644 index 192060c1f..000000000 --- a/embassy-stm32/src/chip/stm32l471re.rs +++ /dev/null @@ -1,547 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471rg.rs b/embassy-stm32/src/chip/stm32l471rg.rs deleted file mode 100644 index 192060c1f..000000000 --- a/embassy-stm32/src/chip/stm32l471rg.rs +++ /dev/null @@ -1,547 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471ve.rs b/embassy-stm32/src/chip/stm32l471ve.rs deleted file mode 100644 index 192060c1f..000000000 --- a/embassy-stm32/src/chip/stm32l471ve.rs +++ /dev/null @@ -1,547 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471vg.rs b/embassy-stm32/src/chip/stm32l471vg.rs deleted file mode 100644 index 192060c1f..000000000 --- a/embassy-stm32/src/chip/stm32l471vg.rs +++ /dev/null @@ -1,547 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471ze.rs b/embassy-stm32/src/chip/stm32l471ze.rs deleted file mode 100644 index 192060c1f..000000000 --- a/embassy-stm32/src/chip/stm32l471ze.rs +++ /dev/null @@ -1,547 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471zg.rs b/embassy-stm32/src/chip/stm32l471zg.rs deleted file mode 100644 index 192060c1f..000000000 --- a/embassy-stm32/src/chip/stm32l471zg.rs +++ /dev/null @@ -1,547 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475rc.rs b/embassy-stm32/src/chip/stm32l475rc.rs deleted file mode 100644 index 7a818be15..000000000 --- a/embassy-stm32/src/chip/stm32l475rc.rs +++ /dev/null @@ -1,551 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475re.rs b/embassy-stm32/src/chip/stm32l475re.rs deleted file mode 100644 index 7a818be15..000000000 --- a/embassy-stm32/src/chip/stm32l475re.rs +++ /dev/null @@ -1,551 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475rg.rs b/embassy-stm32/src/chip/stm32l475rg.rs deleted file mode 100644 index 7a818be15..000000000 --- a/embassy-stm32/src/chip/stm32l475rg.rs +++ /dev/null @@ -1,551 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475vc.rs b/embassy-stm32/src/chip/stm32l475vc.rs deleted file mode 100644 index 7a818be15..000000000 --- a/embassy-stm32/src/chip/stm32l475vc.rs +++ /dev/null @@ -1,551 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475ve.rs b/embassy-stm32/src/chip/stm32l475ve.rs deleted file mode 100644 index 7a818be15..000000000 --- a/embassy-stm32/src/chip/stm32l475ve.rs +++ /dev/null @@ -1,551 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475vg.rs b/embassy-stm32/src/chip/stm32l475vg.rs deleted file mode 100644 index 7a818be15..000000000 --- a/embassy-stm32/src/chip/stm32l475vg.rs +++ /dev/null @@ -1,551 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, - RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, - TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, - WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476je.rs b/embassy-stm32/src/chip/stm32l476je.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476je.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476jg.rs b/embassy-stm32/src/chip/stm32l476jg.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476jg.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476me.rs b/embassy-stm32/src/chip/stm32l476me.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476me.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476mg.rs b/embassy-stm32/src/chip/stm32l476mg.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476mg.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476qe.rs b/embassy-stm32/src/chip/stm32l476qe.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476qe.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476qg.rs b/embassy-stm32/src/chip/stm32l476qg.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476qg.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476rc.rs b/embassy-stm32/src/chip/stm32l476rc.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476rc.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476re.rs b/embassy-stm32/src/chip/stm32l476re.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476re.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476rg.rs b/embassy-stm32/src/chip/stm32l476rg.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476rg.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476vc.rs b/embassy-stm32/src/chip/stm32l476vc.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476vc.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476ve.rs b/embassy-stm32/src/chip/stm32l476ve.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476ve.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476vg.rs b/embassy-stm32/src/chip/stm32l476vg.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476vg.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476ze.rs b/embassy-stm32/src/chip/stm32l476ze.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476ze.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476zg.rs b/embassy-stm32/src/chip/stm32l476zg.rs deleted file mode 100644 index d5b271290..000000000 --- a/embassy-stm32/src/chip/stm32l476zg.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, - RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l485jc.rs b/embassy-stm32/src/chip/stm32l485jc.rs deleted file mode 100644 index 829a5b5a8..000000000 --- a/embassy-stm32/src/chip/stm32l485jc.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, - RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l485je.rs b/embassy-stm32/src/chip/stm32l485je.rs deleted file mode 100644 index 829a5b5a8..000000000 --- a/embassy-stm32/src/chip/stm32l485je.rs +++ /dev/null @@ -1,554 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, - RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, - TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, - USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l486jg.rs b/embassy-stm32/src/chip/stm32l486jg.rs deleted file mode 100644 index 27ce58704..000000000 --- a/embassy-stm32/src/chip/stm32l486jg.rs +++ /dev/null @@ -1,557 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l486qg.rs b/embassy-stm32/src/chip/stm32l486qg.rs deleted file mode 100644 index 27ce58704..000000000 --- a/embassy-stm32/src/chip/stm32l486qg.rs +++ /dev/null @@ -1,557 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l486rg.rs b/embassy-stm32/src/chip/stm32l486rg.rs deleted file mode 100644 index 27ce58704..000000000 --- a/embassy-stm32/src/chip/stm32l486rg.rs +++ /dev/null @@ -1,557 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l486vg.rs b/embassy-stm32/src/chip/stm32l486vg.rs deleted file mode 100644 index 27ce58704..000000000 --- a/embassy-stm32/src/chip/stm32l486vg.rs +++ /dev/null @@ -1,557 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l486zg.rs b/embassy-stm32/src/chip/stm32l486zg.rs deleted file mode 100644 index 27ce58704..000000000 --- a/embassy-stm32/src/chip/stm32l486zg.rs +++ /dev/null @@ -1,557 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 82] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496ae.rs b/embassy-stm32/src/chip/stm32l496ae.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496ae.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496ag.rs b/embassy-stm32/src/chip/stm32l496ag.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496ag.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496qe.rs b/embassy-stm32/src/chip/stm32l496qe.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496qe.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496qg.rs b/embassy-stm32/src/chip/stm32l496qg.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496qg.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496re.rs b/embassy-stm32/src/chip/stm32l496re.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496re.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496rg.rs b/embassy-stm32/src/chip/stm32l496rg.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496rg.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496ve.rs b/embassy-stm32/src/chip/stm32l496ve.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496ve.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496vg.rs b/embassy-stm32/src/chip/stm32l496vg.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496vg.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496wg.rs b/embassy-stm32/src/chip/stm32l496wg.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496wg.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496ze.rs b/embassy-stm32/src/chip/stm32l496ze.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496ze.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496zg.rs b/embassy-stm32/src/chip/stm32l496zg.rs deleted file mode 100644 index e54e0774d..000000000 --- a/embassy-stm32/src/chip/stm32l496zg.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, - PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, - PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, - PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, - PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, - PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, - QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4a6ag.rs b/embassy-stm32/src/chip/stm32l4a6ag.rs deleted file mode 100644 index a3e227f1f..000000000 --- a/embassy-stm32/src/chip/stm32l4a6ag.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, - EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, - PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, - PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, - PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, - PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, - PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, - PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, - PI12, PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, - OPAMP1, OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, - TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4a6qg.rs b/embassy-stm32/src/chip/stm32l4a6qg.rs deleted file mode 100644 index a3e227f1f..000000000 --- a/embassy-stm32/src/chip/stm32l4a6qg.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, - EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, - PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, - PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, - PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, - PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, - PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, - PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, - PI12, PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, - OPAMP1, OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, - TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4a6rg.rs b/embassy-stm32/src/chip/stm32l4a6rg.rs deleted file mode 100644 index a3e227f1f..000000000 --- a/embassy-stm32/src/chip/stm32l4a6rg.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, - EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, - PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, - PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, - PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, - PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, - PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, - PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, - PI12, PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, - OPAMP1, OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, - TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4a6vg.rs b/embassy-stm32/src/chip/stm32l4a6vg.rs deleted file mode 100644 index a3e227f1f..000000000 --- a/embassy-stm32/src/chip/stm32l4a6vg.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, - EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, - PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, - PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, - PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, - PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, - PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, - PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, - PI12, PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, - OPAMP1, OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, - TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4a6zg.rs b/embassy-stm32/src/chip/stm32l4a6zg.rs deleted file mode 100644 index a3e227f1f..000000000 --- a/embassy-stm32/src/chip/stm32l4a6zg.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, - EXTI, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, - PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, - PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, - PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, - PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, - PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, - PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, - PI12, PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, - OPAMP1, OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, - TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - ADC3 = 47, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - CAN2_RX0 = 87, - CAN2_RX1 = 88, - CAN2_SCE = 89, - CAN2_TX = 86, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_RNG = 80, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 84, - I2C4_EV = 83, - LCD = 78, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OTG_FS = 67, - PVD_PVM = 1, - QUADSPI = 71, - RCC = 5, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - SWPMI1 = 76, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(ADC3); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(CAN2_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_RNG); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LCD); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(QUADSPI); - declare!(RCC); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(SWPMI1); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn ADC3(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn CAN2_RX0(); - fn CAN2_RX1(); - fn CAN2_SCE(); - fn CAN2_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_RNG(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LCD(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OTG_FS(); - fn PVD_PVM(); - fn QUADSPI(); - fn RCC(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn SWPMI1(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 91] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: ADC3 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: QUADSPI }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: SWPMI1 }, - Vector { _handler: TSC }, - Vector { _handler: LCD }, - Vector { _handler: AES }, - Vector { _handler: HASH_RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_EV }, - Vector { _handler: I2C4_ER }, - Vector { _handler: DCMI }, - Vector { _handler: CAN2_TX }, - Vector { _handler: CAN2_RX0 }, - Vector { _handler: CAN2_RX1 }, - Vector { _handler: CAN2_SCE }, - Vector { _handler: DMA2D }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5ae.rs b/embassy-stm32/src/chip/stm32l4p5ae.rs deleted file mode 100644 index 66034e537..000000000 --- a/embassy-stm32/src/chip/stm32l4p5ae.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5ag.rs b/embassy-stm32/src/chip/stm32l4p5ag.rs deleted file mode 100644 index 66034e537..000000000 --- a/embassy-stm32/src/chip/stm32l4p5ag.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5ce.rs b/embassy-stm32/src/chip/stm32l4p5ce.rs deleted file mode 100644 index e3622c0ec..000000000 --- a/embassy-stm32/src/chip/stm32l4p5ce.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DMA2D, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC2, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5cg.rs b/embassy-stm32/src/chip/stm32l4p5cg.rs deleted file mode 100644 index e3622c0ec..000000000 --- a/embassy-stm32/src/chip/stm32l4p5cg.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DMA2D, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC2, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5qe.rs b/embassy-stm32/src/chip/stm32l4p5qe.rs deleted file mode 100644 index 66034e537..000000000 --- a/embassy-stm32/src/chip/stm32l4p5qe.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5qg.rs b/embassy-stm32/src/chip/stm32l4p5qg.rs deleted file mode 100644 index 66034e537..000000000 --- a/embassy-stm32/src/chip/stm32l4p5qg.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5re.rs b/embassy-stm32/src/chip/stm32l4p5re.rs deleted file mode 100644 index c60e21456..000000000 --- a/embassy-stm32/src/chip/stm32l4p5re.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5rg.rs b/embassy-stm32/src/chip/stm32l4p5rg.rs deleted file mode 100644 index c60e21456..000000000 --- a/embassy-stm32/src/chip/stm32l4p5rg.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5ve.rs b/embassy-stm32/src/chip/stm32l4p5ve.rs deleted file mode 100644 index 66034e537..000000000 --- a/embassy-stm32/src/chip/stm32l4p5ve.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5vg.rs b/embassy-stm32/src/chip/stm32l4p5vg.rs deleted file mode 100644 index 66034e537..000000000 --- a/embassy-stm32/src/chip/stm32l4p5vg.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5ze.rs b/embassy-stm32/src/chip/stm32l4p5ze.rs deleted file mode 100644 index 66034e537..000000000 --- a/embassy-stm32/src/chip/stm32l4p5ze.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5zg.rs b/embassy-stm32/src/chip/stm32l4p5zg.rs deleted file mode 100644 index 66034e537..000000000 --- a/embassy-stm32/src/chip/stm32l4p5zg.rs +++ /dev/null @@ -1,599 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5ag.rs b/embassy-stm32/src/chip/stm32l4q5ag.rs deleted file mode 100644 index 64643dc4e..000000000 --- a/embassy-stm32/src/chip/stm32l4q5ag.rs +++ /dev/null @@ -1,605 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PKA = 86, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PKA); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PKA(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _handler: PKA }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5cg.rs b/embassy-stm32/src/chip/stm32l4q5cg.rs deleted file mode 100644 index 75adefddd..000000000 --- a/embassy-stm32/src/chip/stm32l4q5cg.rs +++ /dev/null @@ -1,605 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, RCC, RNG, RTC, SAI1, SAI2, SDMMC2, SPI1, SPI2, SPI3, - SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, - USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PKA = 86, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PKA); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PKA(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _handler: PKA }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5qg.rs b/embassy-stm32/src/chip/stm32l4q5qg.rs deleted file mode 100644 index 64643dc4e..000000000 --- a/embassy-stm32/src/chip/stm32l4q5qg.rs +++ /dev/null @@ -1,605 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PKA = 86, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PKA); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PKA(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _handler: PKA }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5rg.rs b/embassy-stm32/src/chip/stm32l4q5rg.rs deleted file mode 100644 index bbf0c47db..000000000 --- a/embassy-stm32/src/chip/stm32l4q5rg.rs +++ /dev/null @@ -1,605 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PKA = 86, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PKA); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PKA(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _handler: PKA }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5vg.rs b/embassy-stm32/src/chip/stm32l4q5vg.rs deleted file mode 100644 index 64643dc4e..000000000 --- a/embassy-stm32/src/chip/stm32l4q5vg.rs +++ /dev/null @@ -1,605 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PKA = 86, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PKA); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PKA(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _handler: PKA }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5zg.rs b/embassy-stm32/src/chip/stm32l4q5zg.rs deleted file mode 100644 index 64643dc4e..000000000 --- a/embassy-stm32/src/chip/stm32l4q5zg.rs +++ /dev/null @@ -1,605 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, - SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, - UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1_2 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI_PSSI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PKA = 86, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SDMMC2 = 47, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1_2); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI_PSSI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PKA); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SDMMC2); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1_2(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI_PSSI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PKA(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SDMMC2(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1_2 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { _reserved: 0 }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _handler: SDMMC2 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { _reserved: 0 }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { - _handler: DCMI_PSSI, - }, - Vector { _handler: PKA }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5ag.rs b/embassy-stm32/src/chip/stm32l4r5ag.rs deleted file mode 100644 index 9c98d1f88..000000000 --- a/embassy-stm32/src/chip/stm32l4r5ag.rs +++ /dev/null @@ -1,598 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, - OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5ai.rs b/embassy-stm32/src/chip/stm32l4r5ai.rs deleted file mode 100644 index 9c98d1f88..000000000 --- a/embassy-stm32/src/chip/stm32l4r5ai.rs +++ /dev/null @@ -1,598 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, - OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5qg.rs b/embassy-stm32/src/chip/stm32l4r5qg.rs deleted file mode 100644 index 9c98d1f88..000000000 --- a/embassy-stm32/src/chip/stm32l4r5qg.rs +++ /dev/null @@ -1,598 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, - OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5qi.rs b/embassy-stm32/src/chip/stm32l4r5qi.rs deleted file mode 100644 index 9c98d1f88..000000000 --- a/embassy-stm32/src/chip/stm32l4r5qi.rs +++ /dev/null @@ -1,598 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, - OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5vg.rs b/embassy-stm32/src/chip/stm32l4r5vg.rs deleted file mode 100644 index 9c98d1f88..000000000 --- a/embassy-stm32/src/chip/stm32l4r5vg.rs +++ /dev/null @@ -1,598 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, - OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5vi.rs b/embassy-stm32/src/chip/stm32l4r5vi.rs deleted file mode 100644 index 9c98d1f88..000000000 --- a/embassy-stm32/src/chip/stm32l4r5vi.rs +++ /dev/null @@ -1,598 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, - OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5zg.rs b/embassy-stm32/src/chip/stm32l4r5zg.rs deleted file mode 100644 index 9c98d1f88..000000000 --- a/embassy-stm32/src/chip/stm32l4r5zg.rs +++ /dev/null @@ -1,598 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, - OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5zi.rs b/embassy-stm32/src/chip/stm32l4r5zi.rs deleted file mode 100644 index 9c98d1f88..000000000 --- a/embassy-stm32/src/chip/stm32l4r5zi.rs +++ /dev/null @@ -1,598 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, PA3, - PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, - PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, - PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, - PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, - PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, - PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, - PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, - PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, - PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, - OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, - TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, - USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r7ai.rs b/embassy-stm32/src/chip/stm32l4r7ai.rs deleted file mode 100644 index d3d635c43..000000000 --- a/embassy-stm32/src/chip/stm32l4r7ai.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r7vi.rs b/embassy-stm32/src/chip/stm32l4r7vi.rs deleted file mode 100644 index d3d635c43..000000000 --- a/embassy-stm32/src/chip/stm32l4r7vi.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r7zi.rs b/embassy-stm32/src/chip/stm32l4r7zi.rs deleted file mode 100644 index d3d635c43..000000000 --- a/embassy-stm32/src/chip/stm32l4r7zi.rs +++ /dev/null @@ -1,607 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9ag.rs b/embassy-stm32/src/chip/stm32l4r9ag.rs deleted file mode 100644 index 9d994d7a1..000000000 --- a/embassy-stm32/src/chip/stm32l4r9ag.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - DSI = 78, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(DSI); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn DSI(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _handler: DSI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9ai.rs b/embassy-stm32/src/chip/stm32l4r9ai.rs deleted file mode 100644 index 9d994d7a1..000000000 --- a/embassy-stm32/src/chip/stm32l4r9ai.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - DSI = 78, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(DSI); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn DSI(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _handler: DSI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9vg.rs b/embassy-stm32/src/chip/stm32l4r9vg.rs deleted file mode 100644 index 9d994d7a1..000000000 --- a/embassy-stm32/src/chip/stm32l4r9vg.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - DSI = 78, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(DSI); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn DSI(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _handler: DSI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9vi.rs b/embassy-stm32/src/chip/stm32l4r9vi.rs deleted file mode 100644 index 9d994d7a1..000000000 --- a/embassy-stm32/src/chip/stm32l4r9vi.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - DSI = 78, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(DSI); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn DSI(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _handler: DSI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9zg.rs b/embassy-stm32/src/chip/stm32l4r9zg.rs deleted file mode 100644 index 9d994d7a1..000000000 --- a/embassy-stm32/src/chip/stm32l4r9zg.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - DSI = 78, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(DSI); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn DSI(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _handler: DSI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9zi.rs b/embassy-stm32/src/chip/stm32l4r9zi.rs deleted file mode 100644 index 9d994d7a1..000000000 --- a/embassy-stm32/src/chip/stm32l4r9zi.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, PA1, - PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, - PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, - PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, - PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - CRS = 82, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - DSI = 78, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(CRS); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(DSI); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn CRS(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn DSI(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _handler: DSI }, - Vector { _reserved: 0 }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s5ai.rs b/embassy-stm32/src/chip/stm32l4s5ai.rs deleted file mode 100644 index cac7ba52a..000000000 --- a/embassy-stm32/src/chip/stm32l4s5ai.rs +++ /dev/null @@ -1,601 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s5qi.rs b/embassy-stm32/src/chip/stm32l4s5qi.rs deleted file mode 100644 index cac7ba52a..000000000 --- a/embassy-stm32/src/chip/stm32l4s5qi.rs +++ /dev/null @@ -1,601 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s5vi.rs b/embassy-stm32/src/chip/stm32l4s5vi.rs deleted file mode 100644 index cac7ba52a..000000000 --- a/embassy-stm32/src/chip/stm32l4s5vi.rs +++ /dev/null @@ -1,601 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s5zi.rs b/embassy-stm32/src/chip/stm32l4s5zi.rs deleted file mode 100644 index cac7ba52a..000000000 --- a/embassy-stm32/src/chip/stm32l4s5zi.rs +++ /dev/null @@ -1,601 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, PA0, PA1, PA2, - PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, - PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, - PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, - PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, - PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, - PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, - PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, - PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, - PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, - OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, - TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, - USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s7ai.rs b/embassy-stm32/src/chip/stm32l4s7ai.rs deleted file mode 100644 index 5cef4a852..000000000 --- a/embassy-stm32/src/chip/stm32l4s7ai.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, - SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, - USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s7vi.rs b/embassy-stm32/src/chip/stm32l4s7vi.rs deleted file mode 100644 index 5cef4a852..000000000 --- a/embassy-stm32/src/chip/stm32l4s7vi.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, - SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, - USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s7zi.rs b/embassy-stm32/src/chip/stm32l4s7zi.rs deleted file mode 100644 index 5cef4a852..000000000 --- a/embassy-stm32/src/chip/stm32l4s7zi.rs +++ /dev/null @@ -1,610 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, - SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, - USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _reserved: 0 }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s9ai.rs b/embassy-stm32/src/chip/stm32l4s9ai.rs deleted file mode 100644 index a79938e3e..000000000 --- a/embassy-stm32/src/chip/stm32l4s9ai.rs +++ /dev/null @@ -1,613 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, - SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, - USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - DSI = 78, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(DSI); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn DSI(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _handler: DSI }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s9vi.rs b/embassy-stm32/src/chip/stm32l4s9vi.rs deleted file mode 100644 index a79938e3e..000000000 --- a/embassy-stm32/src/chip/stm32l4s9vi.rs +++ /dev/null @@ -1,613 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, - SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, - USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - DSI = 78, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(DSI); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn DSI(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _handler: DSI }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s9zi.rs b/embassy-stm32/src/chip/stm32l4s9zi.rs deleted file mode 100644 index a79938e3e..000000000 --- a/embassy-stm32/src/chip/stm32l4s9zi.rs +++ /dev/null @@ -1,613 +0,0 @@ -use embassy_extras::peripherals; -peripherals!( - EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, - EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, EXTI, GFXMMU, PA0, - PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, - PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, - PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, - PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, - PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, - PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, - PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, - PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, - PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, - OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, - SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, - USART1, USART2, USART3, USB_OTG_FS, WWDG -); -pub const SYSCFG_BASE: usize = 0x40010000; -pub const EXTI_BASE: usize = 0x40010400; -pub const GPIO_BASE: usize = 0x48000000; -pub const GPIO_STRIDE: usize = 0x400; - -pub mod interrupt { - pub use cortex_m::interrupt::{CriticalSection, Mutex}; - pub use embassy::interrupt::{declare, take, Interrupt}; - pub use embassy_extras::interrupt::Priority4 as Priority; - - #[derive(Copy, Clone, Debug, PartialEq, Eq)] - #[allow(non_camel_case_types)] - enum InterruptEnum { - ADC1 = 18, - AES = 79, - CAN1_RX0 = 20, - CAN1_RX1 = 21, - CAN1_SCE = 22, - CAN1_TX = 19, - COMP = 64, - DCMI = 85, - DFSDM1_FLT0 = 61, - DFSDM1_FLT1 = 62, - DFSDM1_FLT2 = 63, - DFSDM1_FLT3 = 42, - DMA1_Channel1 = 11, - DMA1_Channel2 = 12, - DMA1_Channel3 = 13, - DMA1_Channel4 = 14, - DMA1_Channel5 = 15, - DMA1_Channel6 = 16, - DMA1_Channel7 = 17, - DMA2D = 90, - DMA2_Channel1 = 56, - DMA2_Channel2 = 57, - DMA2_Channel3 = 58, - DMA2_Channel4 = 59, - DMA2_Channel5 = 60, - DMA2_Channel6 = 68, - DMA2_Channel7 = 69, - DMAMUX1_OVR = 94, - DSI = 78, - EXTI0 = 6, - EXTI1 = 7, - EXTI15_10 = 40, - EXTI2 = 8, - EXTI3 = 9, - EXTI4 = 10, - EXTI9_5 = 23, - FLASH = 4, - FMC = 48, - FPU = 81, - GFXMMU = 93, - HASH_CRS = 82, - I2C1_ER = 32, - I2C1_EV = 31, - I2C2_ER = 34, - I2C2_EV = 33, - I2C3_ER = 73, - I2C3_EV = 72, - I2C4_ER = 83, - I2C4_EV = 84, - LPTIM1 = 65, - LPTIM2 = 66, - LPUART1 = 70, - LTDC = 91, - LTDC_ER = 92, - OCTOSPI1 = 71, - OCTOSPI2 = 76, - OTG_FS = 67, - PVD_PVM = 1, - RCC = 5, - RNG = 80, - RTC_Alarm = 41, - RTC_WKUP = 3, - SAI1 = 74, - SAI2 = 75, - SDMMC1 = 49, - SPI1 = 35, - SPI2 = 36, - SPI3 = 51, - TAMP_STAMP = 2, - TIM1_BRK_TIM15 = 24, - TIM1_CC = 27, - TIM1_TRG_COM_TIM17 = 26, - TIM1_UP_TIM16 = 25, - TIM2 = 28, - TIM3 = 29, - TIM4 = 30, - TIM5 = 50, - TIM6_DAC = 54, - TIM7 = 55, - TIM8_BRK = 43, - TIM8_CC = 46, - TIM8_TRG_COM = 45, - TIM8_UP = 44, - TSC = 77, - UART4 = 52, - UART5 = 53, - USART1 = 37, - USART2 = 38, - USART3 = 39, - WWDG = 0, - } - unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } - } - - declare!(ADC1); - declare!(AES); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(CAN1_TX); - declare!(COMP); - declare!(DCMI); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(DFSDM1_FLT2); - declare!(DFSDM1_FLT3); - declare!(DMA1_Channel1); - declare!(DMA1_Channel2); - declare!(DMA1_Channel3); - declare!(DMA1_Channel4); - declare!(DMA1_Channel5); - declare!(DMA1_Channel6); - declare!(DMA1_Channel7); - declare!(DMA2D); - declare!(DMA2_Channel1); - declare!(DMA2_Channel2); - declare!(DMA2_Channel3); - declare!(DMA2_Channel4); - declare!(DMA2_Channel5); - declare!(DMA2_Channel6); - declare!(DMA2_Channel7); - declare!(DMAMUX1_OVR); - declare!(DSI); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI15_10); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(EXTI9_5); - declare!(FLASH); - declare!(FMC); - declare!(FPU); - declare!(GFXMMU); - declare!(HASH_CRS); - declare!(I2C1_ER); - declare!(I2C1_EV); - declare!(I2C2_ER); - declare!(I2C2_EV); - declare!(I2C3_ER); - declare!(I2C3_EV); - declare!(I2C4_ER); - declare!(I2C4_EV); - declare!(LPTIM1); - declare!(LPTIM2); - declare!(LPUART1); - declare!(LTDC); - declare!(LTDC_ER); - declare!(OCTOSPI1); - declare!(OCTOSPI2); - declare!(OTG_FS); - declare!(PVD_PVM); - declare!(RCC); - declare!(RNG); - declare!(RTC_Alarm); - declare!(RTC_WKUP); - declare!(SAI1); - declare!(SAI2); - declare!(SDMMC1); - declare!(SPI1); - declare!(SPI2); - declare!(SPI3); - declare!(TAMP_STAMP); - declare!(TIM1_BRK_TIM15); - declare!(TIM1_CC); - declare!(TIM1_TRG_COM_TIM17); - declare!(TIM1_UP_TIM16); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(TIM5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM8_BRK); - declare!(TIM8_CC); - declare!(TIM8_TRG_COM); - declare!(TIM8_UP); - declare!(TSC); - declare!(UART4); - declare!(UART5); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(WWDG); -} -mod interrupt_vector { - extern "C" { - fn ADC1(); - fn AES(); - fn CAN1_RX0(); - fn CAN1_RX1(); - fn CAN1_SCE(); - fn CAN1_TX(); - fn COMP(); - fn DCMI(); - fn DFSDM1_FLT0(); - fn DFSDM1_FLT1(); - fn DFSDM1_FLT2(); - fn DFSDM1_FLT3(); - fn DMA1_Channel1(); - fn DMA1_Channel2(); - fn DMA1_Channel3(); - fn DMA1_Channel4(); - fn DMA1_Channel5(); - fn DMA1_Channel6(); - fn DMA1_Channel7(); - fn DMA2D(); - fn DMA2_Channel1(); - fn DMA2_Channel2(); - fn DMA2_Channel3(); - fn DMA2_Channel4(); - fn DMA2_Channel5(); - fn DMA2_Channel6(); - fn DMA2_Channel7(); - fn DMAMUX1_OVR(); - fn DSI(); - fn EXTI0(); - fn EXTI1(); - fn EXTI15_10(); - fn EXTI2(); - fn EXTI3(); - fn EXTI4(); - fn EXTI9_5(); - fn FLASH(); - fn FMC(); - fn FPU(); - fn GFXMMU(); - fn HASH_CRS(); - fn I2C1_ER(); - fn I2C1_EV(); - fn I2C2_ER(); - fn I2C2_EV(); - fn I2C3_ER(); - fn I2C3_EV(); - fn I2C4_ER(); - fn I2C4_EV(); - fn LPTIM1(); - fn LPTIM2(); - fn LPUART1(); - fn LTDC(); - fn LTDC_ER(); - fn OCTOSPI1(); - fn OCTOSPI2(); - fn OTG_FS(); - fn PVD_PVM(); - fn RCC(); - fn RNG(); - fn RTC_Alarm(); - fn RTC_WKUP(); - fn SAI1(); - fn SAI2(); - fn SDMMC1(); - fn SPI1(); - fn SPI2(); - fn SPI3(); - fn TAMP_STAMP(); - fn TIM1_BRK_TIM15(); - fn TIM1_CC(); - fn TIM1_TRG_COM_TIM17(); - fn TIM1_UP_TIM16(); - fn TIM2(); - fn TIM3(); - fn TIM4(); - fn TIM5(); - fn TIM6_DAC(); - fn TIM7(); - fn TIM8_BRK(); - fn TIM8_CC(); - fn TIM8_TRG_COM(); - fn TIM8_UP(); - fn TSC(); - fn UART4(); - fn UART5(); - fn USART1(); - fn USART2(); - fn USART3(); - fn WWDG(); - } - pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, - } - #[link_section = ".vector_table.interrupts"] - #[no_mangle] - pub static __INTERRUPTS: [Vector; 95] = [ - Vector { _handler: WWDG }, - Vector { _handler: PVD_PVM }, - Vector { - _handler: TAMP_STAMP, - }, - Vector { _handler: RTC_WKUP }, - Vector { _handler: FLASH }, - Vector { _handler: RCC }, - Vector { _handler: EXTI0 }, - Vector { _handler: EXTI1 }, - Vector { _handler: EXTI2 }, - Vector { _handler: EXTI3 }, - Vector { _handler: EXTI4 }, - Vector { - _handler: DMA1_Channel1, - }, - Vector { - _handler: DMA1_Channel2, - }, - Vector { - _handler: DMA1_Channel3, - }, - Vector { - _handler: DMA1_Channel4, - }, - Vector { - _handler: DMA1_Channel5, - }, - Vector { - _handler: DMA1_Channel6, - }, - Vector { - _handler: DMA1_Channel7, - }, - Vector { _handler: ADC1 }, - Vector { _handler: CAN1_TX }, - Vector { _handler: CAN1_RX0 }, - Vector { _handler: CAN1_RX1 }, - Vector { _handler: CAN1_SCE }, - Vector { _handler: EXTI9_5 }, - Vector { - _handler: TIM1_BRK_TIM15, - }, - Vector { - _handler: TIM1_UP_TIM16, - }, - Vector { - _handler: TIM1_TRG_COM_TIM17, - }, - Vector { _handler: TIM1_CC }, - Vector { _handler: TIM2 }, - Vector { _handler: TIM3 }, - Vector { _handler: TIM4 }, - Vector { _handler: I2C1_EV }, - Vector { _handler: I2C1_ER }, - Vector { _handler: I2C2_EV }, - Vector { _handler: I2C2_ER }, - Vector { _handler: SPI1 }, - Vector { _handler: SPI2 }, - Vector { _handler: USART1 }, - Vector { _handler: USART2 }, - Vector { _handler: USART3 }, - Vector { - _handler: EXTI15_10, - }, - Vector { - _handler: RTC_Alarm, - }, - Vector { - _handler: DFSDM1_FLT3, - }, - Vector { _handler: TIM8_BRK }, - Vector { _handler: TIM8_UP }, - Vector { - _handler: TIM8_TRG_COM, - }, - Vector { _handler: TIM8_CC }, - Vector { _reserved: 0 }, - Vector { _handler: FMC }, - Vector { _handler: SDMMC1 }, - Vector { _handler: TIM5 }, - Vector { _handler: SPI3 }, - Vector { _handler: UART4 }, - Vector { _handler: UART5 }, - Vector { _handler: TIM6_DAC }, - Vector { _handler: TIM7 }, - Vector { - _handler: DMA2_Channel1, - }, - Vector { - _handler: DMA2_Channel2, - }, - Vector { - _handler: DMA2_Channel3, - }, - Vector { - _handler: DMA2_Channel4, - }, - Vector { - _handler: DMA2_Channel5, - }, - Vector { - _handler: DFSDM1_FLT0, - }, - Vector { - _handler: DFSDM1_FLT1, - }, - Vector { - _handler: DFSDM1_FLT2, - }, - Vector { _handler: COMP }, - Vector { _handler: LPTIM1 }, - Vector { _handler: LPTIM2 }, - Vector { _handler: OTG_FS }, - Vector { - _handler: DMA2_Channel6, - }, - Vector { - _handler: DMA2_Channel7, - }, - Vector { _handler: LPUART1 }, - Vector { _handler: OCTOSPI1 }, - Vector { _handler: I2C3_EV }, - Vector { _handler: I2C3_ER }, - Vector { _handler: SAI1 }, - Vector { _handler: SAI2 }, - Vector { _handler: OCTOSPI2 }, - Vector { _handler: TSC }, - Vector { _handler: DSI }, - Vector { _handler: AES }, - Vector { _handler: RNG }, - Vector { _handler: FPU }, - Vector { _handler: HASH_CRS }, - Vector { _handler: I2C4_ER }, - Vector { _handler: I2C4_EV }, - Vector { _handler: DCMI }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: DMA2D }, - Vector { _handler: LTDC }, - Vector { _handler: LTDC_ER }, - Vector { _handler: GFXMMU }, - Vector { - _handler: DMAMUX1_OVR, - }, - ]; -} -impl_gpio_pin!(PA0, 0, 0, EXTI0); -impl_gpio_pin!(PA1, 0, 1, EXTI1); -impl_gpio_pin!(PA2, 0, 2, EXTI2); -impl_gpio_pin!(PA3, 0, 3, EXTI3); -impl_gpio_pin!(PA4, 0, 4, EXTI4); -impl_gpio_pin!(PA5, 0, 5, EXTI5); -impl_gpio_pin!(PA6, 0, 6, EXTI6); -impl_gpio_pin!(PA7, 0, 7, EXTI7); -impl_gpio_pin!(PA8, 0, 8, EXTI8); -impl_gpio_pin!(PA9, 0, 9, EXTI9); -impl_gpio_pin!(PA10, 0, 10, EXTI10); -impl_gpio_pin!(PA11, 0, 11, EXTI11); -impl_gpio_pin!(PA12, 0, 12, EXTI12); -impl_gpio_pin!(PA13, 0, 13, EXTI13); -impl_gpio_pin!(PA14, 0, 14, EXTI14); -impl_gpio_pin!(PA15, 0, 15, EXTI15); -impl_gpio_pin!(PB0, 1, 0, EXTI0); -impl_gpio_pin!(PB1, 1, 1, EXTI1); -impl_gpio_pin!(PB2, 1, 2, EXTI2); -impl_gpio_pin!(PB3, 1, 3, EXTI3); -impl_gpio_pin!(PB4, 1, 4, EXTI4); -impl_gpio_pin!(PB5, 1, 5, EXTI5); -impl_gpio_pin!(PB6, 1, 6, EXTI6); -impl_gpio_pin!(PB7, 1, 7, EXTI7); -impl_gpio_pin!(PB8, 1, 8, EXTI8); -impl_gpio_pin!(PB9, 1, 9, EXTI9); -impl_gpio_pin!(PB10, 1, 10, EXTI10); -impl_gpio_pin!(PB11, 1, 11, EXTI11); -impl_gpio_pin!(PB12, 1, 12, EXTI12); -impl_gpio_pin!(PB13, 1, 13, EXTI13); -impl_gpio_pin!(PB14, 1, 14, EXTI14); -impl_gpio_pin!(PB15, 1, 15, EXTI15); -impl_gpio_pin!(PC0, 2, 0, EXTI0); -impl_gpio_pin!(PC1, 2, 1, EXTI1); -impl_gpio_pin!(PC2, 2, 2, EXTI2); -impl_gpio_pin!(PC3, 2, 3, EXTI3); -impl_gpio_pin!(PC4, 2, 4, EXTI4); -impl_gpio_pin!(PC5, 2, 5, EXTI5); -impl_gpio_pin!(PC6, 2, 6, EXTI6); -impl_gpio_pin!(PC7, 2, 7, EXTI7); -impl_gpio_pin!(PC8, 2, 8, EXTI8); -impl_gpio_pin!(PC9, 2, 9, EXTI9); -impl_gpio_pin!(PC10, 2, 10, EXTI10); -impl_gpio_pin!(PC11, 2, 11, EXTI11); -impl_gpio_pin!(PC12, 2, 12, EXTI12); -impl_gpio_pin!(PC13, 2, 13, EXTI13); -impl_gpio_pin!(PC14, 2, 14, EXTI14); -impl_gpio_pin!(PC15, 2, 15, EXTI15); -impl_gpio_pin!(PD0, 3, 0, EXTI0); -impl_gpio_pin!(PD1, 3, 1, EXTI1); -impl_gpio_pin!(PD2, 3, 2, EXTI2); -impl_gpio_pin!(PD3, 3, 3, EXTI3); -impl_gpio_pin!(PD4, 3, 4, EXTI4); -impl_gpio_pin!(PD5, 3, 5, EXTI5); -impl_gpio_pin!(PD6, 3, 6, EXTI6); -impl_gpio_pin!(PD7, 3, 7, EXTI7); -impl_gpio_pin!(PD8, 3, 8, EXTI8); -impl_gpio_pin!(PD9, 3, 9, EXTI9); -impl_gpio_pin!(PD10, 3, 10, EXTI10); -impl_gpio_pin!(PD11, 3, 11, EXTI11); -impl_gpio_pin!(PD12, 3, 12, EXTI12); -impl_gpio_pin!(PD13, 3, 13, EXTI13); -impl_gpio_pin!(PD14, 3, 14, EXTI14); -impl_gpio_pin!(PD15, 3, 15, EXTI15); -impl_gpio_pin!(PE0, 4, 0, EXTI0); -impl_gpio_pin!(PE1, 4, 1, EXTI1); -impl_gpio_pin!(PE2, 4, 2, EXTI2); -impl_gpio_pin!(PE3, 4, 3, EXTI3); -impl_gpio_pin!(PE4, 4, 4, EXTI4); -impl_gpio_pin!(PE5, 4, 5, EXTI5); -impl_gpio_pin!(PE6, 4, 6, EXTI6); -impl_gpio_pin!(PE7, 4, 7, EXTI7); -impl_gpio_pin!(PE8, 4, 8, EXTI8); -impl_gpio_pin!(PE9, 4, 9, EXTI9); -impl_gpio_pin!(PE10, 4, 10, EXTI10); -impl_gpio_pin!(PE11, 4, 11, EXTI11); -impl_gpio_pin!(PE12, 4, 12, EXTI12); -impl_gpio_pin!(PE13, 4, 13, EXTI13); -impl_gpio_pin!(PE14, 4, 14, EXTI14); -impl_gpio_pin!(PE15, 4, 15, EXTI15); -impl_gpio_pin!(PF0, 5, 0, EXTI0); -impl_gpio_pin!(PF1, 5, 1, EXTI1); -impl_gpio_pin!(PF2, 5, 2, EXTI2); -impl_gpio_pin!(PF3, 5, 3, EXTI3); -impl_gpio_pin!(PF4, 5, 4, EXTI4); -impl_gpio_pin!(PF5, 5, 5, EXTI5); -impl_gpio_pin!(PF6, 5, 6, EXTI6); -impl_gpio_pin!(PF7, 5, 7, EXTI7); -impl_gpio_pin!(PF8, 5, 8, EXTI8); -impl_gpio_pin!(PF9, 5, 9, EXTI9); -impl_gpio_pin!(PF10, 5, 10, EXTI10); -impl_gpio_pin!(PF11, 5, 11, EXTI11); -impl_gpio_pin!(PF12, 5, 12, EXTI12); -impl_gpio_pin!(PF13, 5, 13, EXTI13); -impl_gpio_pin!(PF14, 5, 14, EXTI14); -impl_gpio_pin!(PF15, 5, 15, EXTI15); -impl_gpio_pin!(PG0, 6, 0, EXTI0); -impl_gpio_pin!(PG1, 6, 1, EXTI1); -impl_gpio_pin!(PG2, 6, 2, EXTI2); -impl_gpio_pin!(PG3, 6, 3, EXTI3); -impl_gpio_pin!(PG4, 6, 4, EXTI4); -impl_gpio_pin!(PG5, 6, 5, EXTI5); -impl_gpio_pin!(PG6, 6, 6, EXTI6); -impl_gpio_pin!(PG7, 6, 7, EXTI7); -impl_gpio_pin!(PG8, 6, 8, EXTI8); -impl_gpio_pin!(PG9, 6, 9, EXTI9); -impl_gpio_pin!(PG10, 6, 10, EXTI10); -impl_gpio_pin!(PG11, 6, 11, EXTI11); -impl_gpio_pin!(PG12, 6, 12, EXTI12); -impl_gpio_pin!(PG13, 6, 13, EXTI13); -impl_gpio_pin!(PG14, 6, 14, EXTI14); -impl_gpio_pin!(PG15, 6, 15, EXTI15); -impl_gpio_pin!(PH0, 7, 0, EXTI0); -impl_gpio_pin!(PH1, 7, 1, EXTI1); -impl_gpio_pin!(PH2, 7, 2, EXTI2); -impl_gpio_pin!(PH3, 7, 3, EXTI3); -impl_gpio_pin!(PH4, 7, 4, EXTI4); -impl_gpio_pin!(PH5, 7, 5, EXTI5); -impl_gpio_pin!(PH6, 7, 6, EXTI6); -impl_gpio_pin!(PH7, 7, 7, EXTI7); -impl_gpio_pin!(PH8, 7, 8, EXTI8); -impl_gpio_pin!(PH9, 7, 9, EXTI9); -impl_gpio_pin!(PH10, 7, 10, EXTI10); -impl_gpio_pin!(PH11, 7, 11, EXTI11); -impl_gpio_pin!(PH12, 7, 12, EXTI12); -impl_gpio_pin!(PH13, 7, 13, EXTI13); -impl_gpio_pin!(PH14, 7, 14, EXTI14); -impl_gpio_pin!(PH15, 7, 15, EXTI15); -impl_gpio_pin!(PI0, 8, 0, EXTI0); -impl_gpio_pin!(PI1, 8, 1, EXTI1); -impl_gpio_pin!(PI2, 8, 2, EXTI2); -impl_gpio_pin!(PI3, 8, 3, EXTI3); -impl_gpio_pin!(PI4, 8, 4, EXTI4); -impl_gpio_pin!(PI5, 8, 5, EXTI5); -impl_gpio_pin!(PI6, 8, 6, EXTI6); -impl_gpio_pin!(PI7, 8, 7, EXTI7); -impl_gpio_pin!(PI8, 8, 8, EXTI8); -impl_gpio_pin!(PI9, 8, 9, EXTI9); -impl_gpio_pin!(PI10, 8, 10, EXTI10); -impl_gpio_pin!(PI11, 8, 11, EXTI11); -impl_gpio_pin!(PI12, 8, 12, EXTI12); -impl_gpio_pin!(PI13, 8, 13, EXTI13); -impl_gpio_pin!(PI14, 8, 14, EXTI14); -impl_gpio_pin!(PI15, 8, 15, EXTI15); -impl_rng!(0x50060800); diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs index 8fd9d91ac..375e77825 100644 --- a/embassy-stm32/src/exti.rs +++ b/embassy-stm32/src/exti.rs @@ -13,11 +13,9 @@ use crate::fmt::*; use crate::gpio::{AnyPin, Input, Pin as GpioPin}; use crate::interrupt; use crate::pac; +use crate::pac::{EXTI, SYSCFG}; use crate::peripherals; -const SYSCFG: pac::syscfg::Syscfg = pac::syscfg::Syscfg(crate::chip::SYSCFG_BASE as *mut _); -const EXTI: pac::exti::Exti = pac::exti::Exti(crate::chip::EXTI_BASE as *mut _); - const EXTI_COUNT: usize = 16; const NEW_AW: AtomicWaker = AtomicWaker::new(); static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [NEW_AW; EXTI_COUNT]; diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs index cbe967f6e..43330d9e5 100644 --- a/embassy-stm32/src/gpio.rs +++ b/embassy-stm32/src/gpio.rs @@ -3,10 +3,9 @@ use core::marker::PhantomData; use embassy::util::Unborrow; use embassy_extras::{impl_unborrow, unborrow}; use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin}; -use gpio::vals; -use crate::chip; -use crate::pac::gpio_v2 as gpio; +use crate::pac; +use crate::pac::gpio::{self, vals}; /// Pull setting for an input. #[derive(Debug, Eq, PartialEq)] @@ -164,9 +163,7 @@ pub(crate) mod sealed { #[inline] fn block(&self) -> gpio::Gpio { - // TODO hardcoding peripheral addrs until we figure out how these are handled in the metapac - let p = chip::GPIO_BASE + (self._port() as usize) * chip::GPIO_STRIDE; - gpio::Gpio(p as *mut u8) + pac::GPIO(self._port() as _) } /// Set the output as high. diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index 6bdd0c26b..122998c97 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs @@ -10,18 +10,6 @@ pub mod fmt; use embassy::interrupt::{Interrupt, InterruptExt}; -//pub(crate) use stm32_metapac as pac; - -pub(crate) mod pac { - pub use stm32_metapac::*; - - #[cfg(any(feature = "_syscfg_f4"))] - pub use stm32_metapac::syscfg_f4 as syscfg; - - #[cfg(any(feature = "_syscfg_l4"))] - pub use stm32_metapac::syscfg_l4 as syscfg; -} - #[macro_use] pub mod exti; @@ -35,9 +23,12 @@ pub mod usart; pub mod rng; // This must go LAST so that it sees the `impl_foo!` macros -mod chip; -pub use chip::{interrupt, peripherals, Peripherals}; +mod pac; pub use embassy_macros::interrupt; +pub use pac::{interrupt, peripherals, Peripherals}; + +// workaround for svd2rust-generated code using `use crate::generic::*;` +pub(crate) use pac::generic; #[non_exhaustive] pub struct Config { diff --git a/embassy-stm32/src/pac/mod.rs b/embassy-stm32/src/pac/mod.rs new file mode 100644 index 000000000..35fff08c0 --- /dev/null +++ b/embassy-stm32/src/pac/mod.rs @@ -0,0 +1,292 @@ +#[cfg_attr(feature = "stm32f401cb", path = "stm32f401cb.rs")] +#[cfg_attr(feature = "stm32f401cc", path = "stm32f401cc.rs")] +#[cfg_attr(feature = "stm32f401cd", path = "stm32f401cd.rs")] +#[cfg_attr(feature = "stm32f401ce", path = "stm32f401ce.rs")] +#[cfg_attr(feature = "stm32f401rb", path = "stm32f401rb.rs")] +#[cfg_attr(feature = "stm32f401rc", path = "stm32f401rc.rs")] +#[cfg_attr(feature = "stm32f401rd", path = "stm32f401rd.rs")] +#[cfg_attr(feature = "stm32f401re", path = "stm32f401re.rs")] +#[cfg_attr(feature = "stm32f401vb", path = "stm32f401vb.rs")] +#[cfg_attr(feature = "stm32f401vc", path = "stm32f401vc.rs")] +#[cfg_attr(feature = "stm32f401vd", path = "stm32f401vd.rs")] +#[cfg_attr(feature = "stm32f401ve", path = "stm32f401ve.rs")] +#[cfg_attr(feature = "stm32f405oe", path = "stm32f405oe.rs")] +#[cfg_attr(feature = "stm32f405og", path = "stm32f405og.rs")] +#[cfg_attr(feature = "stm32f405rg", path = "stm32f405rg.rs")] +#[cfg_attr(feature = "stm32f405vg", path = "stm32f405vg.rs")] +#[cfg_attr(feature = "stm32f405zg", path = "stm32f405zg.rs")] +#[cfg_attr(feature = "stm32f407ie", path = "stm32f407ie.rs")] +#[cfg_attr(feature = "stm32f407ig", path = "stm32f407ig.rs")] +#[cfg_attr(feature = "stm32f407ve", path = "stm32f407ve.rs")] +#[cfg_attr(feature = "stm32f407vg", path = "stm32f407vg.rs")] +#[cfg_attr(feature = "stm32f407ze", path = "stm32f407ze.rs")] +#[cfg_attr(feature = "stm32f407zg", path = "stm32f407zg.rs")] +#[cfg_attr(feature = "stm32f410c8", path = "stm32f410c8.rs")] +#[cfg_attr(feature = "stm32f410cb", path = "stm32f410cb.rs")] +#[cfg_attr(feature = "stm32f410r8", path = "stm32f410r8.rs")] +#[cfg_attr(feature = "stm32f410rb", path = "stm32f410rb.rs")] +#[cfg_attr(feature = "stm32f410t8", path = "stm32f410t8.rs")] +#[cfg_attr(feature = "stm32f410tb", path = "stm32f410tb.rs")] +#[cfg_attr(feature = "stm32f411cc", path = "stm32f411cc.rs")] +#[cfg_attr(feature = "stm32f411ce", path = "stm32f411ce.rs")] +#[cfg_attr(feature = "stm32f411rc", path = "stm32f411rc.rs")] +#[cfg_attr(feature = "stm32f411re", path = "stm32f411re.rs")] +#[cfg_attr(feature = "stm32f411vc", path = "stm32f411vc.rs")] +#[cfg_attr(feature = "stm32f411ve", path = "stm32f411ve.rs")] +#[cfg_attr(feature = "stm32f412ce", path = "stm32f412ce.rs")] +#[cfg_attr(feature = "stm32f412cg", path = "stm32f412cg.rs")] +#[cfg_attr(feature = "stm32f412re", path = "stm32f412re.rs")] +#[cfg_attr(feature = "stm32f412rg", path = "stm32f412rg.rs")] +#[cfg_attr(feature = "stm32f412ve", path = "stm32f412ve.rs")] +#[cfg_attr(feature = "stm32f412vg", path = "stm32f412vg.rs")] +#[cfg_attr(feature = "stm32f412ze", path = "stm32f412ze.rs")] +#[cfg_attr(feature = "stm32f412zg", path = "stm32f412zg.rs")] +#[cfg_attr(feature = "stm32f413cg", path = "stm32f413cg.rs")] +#[cfg_attr(feature = "stm32f413ch", path = "stm32f413ch.rs")] +#[cfg_attr(feature = "stm32f413mg", path = "stm32f413mg.rs")] +#[cfg_attr(feature = "stm32f413mh", path = "stm32f413mh.rs")] +#[cfg_attr(feature = "stm32f413rg", path = "stm32f413rg.rs")] +#[cfg_attr(feature = "stm32f413rh", path = "stm32f413rh.rs")] +#[cfg_attr(feature = "stm32f413vg", path = "stm32f413vg.rs")] +#[cfg_attr(feature = "stm32f413vh", path = "stm32f413vh.rs")] +#[cfg_attr(feature = "stm32f413zg", path = "stm32f413zg.rs")] +#[cfg_attr(feature = "stm32f413zh", path = "stm32f413zh.rs")] +#[cfg_attr(feature = "stm32f415og", path = "stm32f415og.rs")] +#[cfg_attr(feature = "stm32f415rg", path = "stm32f415rg.rs")] +#[cfg_attr(feature = "stm32f415vg", path = "stm32f415vg.rs")] +#[cfg_attr(feature = "stm32f415zg", path = "stm32f415zg.rs")] +#[cfg_attr(feature = "stm32f417ie", path = "stm32f417ie.rs")] +#[cfg_attr(feature = "stm32f417ig", path = "stm32f417ig.rs")] +#[cfg_attr(feature = "stm32f417ve", path = "stm32f417ve.rs")] +#[cfg_attr(feature = "stm32f417vg", path = "stm32f417vg.rs")] +#[cfg_attr(feature = "stm32f417ze", path = "stm32f417ze.rs")] +#[cfg_attr(feature = "stm32f417zg", path = "stm32f417zg.rs")] +#[cfg_attr(feature = "stm32f423ch", path = "stm32f423ch.rs")] +#[cfg_attr(feature = "stm32f423mh", path = "stm32f423mh.rs")] +#[cfg_attr(feature = "stm32f423rh", path = "stm32f423rh.rs")] +#[cfg_attr(feature = "stm32f423vh", path = "stm32f423vh.rs")] +#[cfg_attr(feature = "stm32f423zh", path = "stm32f423zh.rs")] +#[cfg_attr(feature = "stm32f427ag", path = "stm32f427ag.rs")] +#[cfg_attr(feature = "stm32f427ai", path = "stm32f427ai.rs")] +#[cfg_attr(feature = "stm32f427ig", path = "stm32f427ig.rs")] +#[cfg_attr(feature = "stm32f427ii", path = "stm32f427ii.rs")] +#[cfg_attr(feature = "stm32f427vg", path = "stm32f427vg.rs")] +#[cfg_attr(feature = "stm32f427vi", path = "stm32f427vi.rs")] +#[cfg_attr(feature = "stm32f427zg", path = "stm32f427zg.rs")] +#[cfg_attr(feature = "stm32f427zi", path = "stm32f427zi.rs")] +#[cfg_attr(feature = "stm32f429ag", path = "stm32f429ag.rs")] +#[cfg_attr(feature = "stm32f429ai", path = "stm32f429ai.rs")] +#[cfg_attr(feature = "stm32f429be", path = "stm32f429be.rs")] +#[cfg_attr(feature = "stm32f429bg", path = "stm32f429bg.rs")] +#[cfg_attr(feature = "stm32f429bi", path = "stm32f429bi.rs")] +#[cfg_attr(feature = "stm32f429ie", path = "stm32f429ie.rs")] +#[cfg_attr(feature = "stm32f429ig", path = "stm32f429ig.rs")] +#[cfg_attr(feature = "stm32f429ii", path = "stm32f429ii.rs")] +#[cfg_attr(feature = "stm32f429ne", path = "stm32f429ne.rs")] +#[cfg_attr(feature = "stm32f429ng", path = "stm32f429ng.rs")] +#[cfg_attr(feature = "stm32f429ni", path = "stm32f429ni.rs")] +#[cfg_attr(feature = "stm32f429ve", path = "stm32f429ve.rs")] +#[cfg_attr(feature = "stm32f429vg", path = "stm32f429vg.rs")] +#[cfg_attr(feature = "stm32f429vi", path = "stm32f429vi.rs")] +#[cfg_attr(feature = "stm32f429ze", path = "stm32f429ze.rs")] +#[cfg_attr(feature = "stm32f429zg", path = "stm32f429zg.rs")] +#[cfg_attr(feature = "stm32f429zi", path = "stm32f429zi.rs")] +#[cfg_attr(feature = "stm32f437ai", path = "stm32f437ai.rs")] +#[cfg_attr(feature = "stm32f437ig", path = "stm32f437ig.rs")] +#[cfg_attr(feature = "stm32f437ii", path = "stm32f437ii.rs")] +#[cfg_attr(feature = "stm32f437vg", path = "stm32f437vg.rs")] +#[cfg_attr(feature = "stm32f437vi", path = "stm32f437vi.rs")] +#[cfg_attr(feature = "stm32f437zg", path = "stm32f437zg.rs")] +#[cfg_attr(feature = "stm32f437zi", path = "stm32f437zi.rs")] +#[cfg_attr(feature = "stm32f439ai", path = "stm32f439ai.rs")] +#[cfg_attr(feature = "stm32f439bg", path = "stm32f439bg.rs")] +#[cfg_attr(feature = "stm32f439bi", path = "stm32f439bi.rs")] +#[cfg_attr(feature = "stm32f439ig", path = "stm32f439ig.rs")] +#[cfg_attr(feature = "stm32f439ii", path = "stm32f439ii.rs")] +#[cfg_attr(feature = "stm32f439ng", path = "stm32f439ng.rs")] +#[cfg_attr(feature = "stm32f439ni", path = "stm32f439ni.rs")] +#[cfg_attr(feature = "stm32f439vg", path = "stm32f439vg.rs")] +#[cfg_attr(feature = "stm32f439vi", path = "stm32f439vi.rs")] +#[cfg_attr(feature = "stm32f439zg", path = "stm32f439zg.rs")] +#[cfg_attr(feature = "stm32f439zi", path = "stm32f439zi.rs")] +#[cfg_attr(feature = "stm32f446mc", path = "stm32f446mc.rs")] +#[cfg_attr(feature = "stm32f446me", path = "stm32f446me.rs")] +#[cfg_attr(feature = "stm32f446rc", path = "stm32f446rc.rs")] +#[cfg_attr(feature = "stm32f446re", path = "stm32f446re.rs")] +#[cfg_attr(feature = "stm32f446vc", path = "stm32f446vc.rs")] +#[cfg_attr(feature = "stm32f446ve", path = "stm32f446ve.rs")] +#[cfg_attr(feature = "stm32f446zc", path = "stm32f446zc.rs")] +#[cfg_attr(feature = "stm32f446ze", path = "stm32f446ze.rs")] +#[cfg_attr(feature = "stm32f469ae", path = "stm32f469ae.rs")] +#[cfg_attr(feature = "stm32f469ag", path = "stm32f469ag.rs")] +#[cfg_attr(feature = "stm32f469ai", path = "stm32f469ai.rs")] +#[cfg_attr(feature = "stm32f469be", path = "stm32f469be.rs")] +#[cfg_attr(feature = "stm32f469bg", path = "stm32f469bg.rs")] +#[cfg_attr(feature = "stm32f469bi", path = "stm32f469bi.rs")] +#[cfg_attr(feature = "stm32f469ie", path = "stm32f469ie.rs")] +#[cfg_attr(feature = "stm32f469ig", path = "stm32f469ig.rs")] +#[cfg_attr(feature = "stm32f469ii", path = "stm32f469ii.rs")] +#[cfg_attr(feature = "stm32f469ne", path = "stm32f469ne.rs")] +#[cfg_attr(feature = "stm32f469ng", path = "stm32f469ng.rs")] +#[cfg_attr(feature = "stm32f469ni", path = "stm32f469ni.rs")] +#[cfg_attr(feature = "stm32f469ve", path = "stm32f469ve.rs")] +#[cfg_attr(feature = "stm32f469vg", path = "stm32f469vg.rs")] +#[cfg_attr(feature = "stm32f469vi", path = "stm32f469vi.rs")] +#[cfg_attr(feature = "stm32f469ze", path = "stm32f469ze.rs")] +#[cfg_attr(feature = "stm32f469zg", path = "stm32f469zg.rs")] +#[cfg_attr(feature = "stm32f469zi", path = "stm32f469zi.rs")] +#[cfg_attr(feature = "stm32f479ag", path = "stm32f479ag.rs")] +#[cfg_attr(feature = "stm32f479ai", path = "stm32f479ai.rs")] +#[cfg_attr(feature = "stm32f479bg", path = "stm32f479bg.rs")] +#[cfg_attr(feature = "stm32f479bi", path = "stm32f479bi.rs")] +#[cfg_attr(feature = "stm32f479ig", path = "stm32f479ig.rs")] +#[cfg_attr(feature = "stm32f479ii", path = "stm32f479ii.rs")] +#[cfg_attr(feature = "stm32f479ng", path = "stm32f479ng.rs")] +#[cfg_attr(feature = "stm32f479ni", path = "stm32f479ni.rs")] +#[cfg_attr(feature = "stm32f479vg", path = "stm32f479vg.rs")] +#[cfg_attr(feature = "stm32f479vi", path = "stm32f479vi.rs")] +#[cfg_attr(feature = "stm32f479zg", path = "stm32f479zg.rs")] +#[cfg_attr(feature = "stm32f479zi", path = "stm32f479zi.rs")] +#[cfg_attr(feature = "stm32l412c8", path = "stm32l412c8.rs")] +#[cfg_attr(feature = "stm32l412cb", path = "stm32l412cb.rs")] +#[cfg_attr(feature = "stm32l412k8", path = "stm32l412k8.rs")] +#[cfg_attr(feature = "stm32l412kb", path = "stm32l412kb.rs")] +#[cfg_attr(feature = "stm32l412r8", path = "stm32l412r8.rs")] +#[cfg_attr(feature = "stm32l412rb", path = "stm32l412rb.rs")] +#[cfg_attr(feature = "stm32l412t8", path = "stm32l412t8.rs")] +#[cfg_attr(feature = "stm32l412tb", path = "stm32l412tb.rs")] +#[cfg_attr(feature = "stm32l422cb", path = "stm32l422cb.rs")] +#[cfg_attr(feature = "stm32l422kb", path = "stm32l422kb.rs")] +#[cfg_attr(feature = "stm32l422rb", path = "stm32l422rb.rs")] +#[cfg_attr(feature = "stm32l422tb", path = "stm32l422tb.rs")] +#[cfg_attr(feature = "stm32l431cb", path = "stm32l431cb.rs")] +#[cfg_attr(feature = "stm32l431cc", path = "stm32l431cc.rs")] +#[cfg_attr(feature = "stm32l431kb", path = "stm32l431kb.rs")] +#[cfg_attr(feature = "stm32l431kc", path = "stm32l431kc.rs")] +#[cfg_attr(feature = "stm32l431rb", path = "stm32l431rb.rs")] +#[cfg_attr(feature = "stm32l431rc", path = "stm32l431rc.rs")] +#[cfg_attr(feature = "stm32l431vc", path = "stm32l431vc.rs")] +#[cfg_attr(feature = "stm32l432kb", path = "stm32l432kb.rs")] +#[cfg_attr(feature = "stm32l432kc", path = "stm32l432kc.rs")] +#[cfg_attr(feature = "stm32l433cb", path = "stm32l433cb.rs")] +#[cfg_attr(feature = "stm32l433cc", path = "stm32l433cc.rs")] +#[cfg_attr(feature = "stm32l433rb", path = "stm32l433rb.rs")] +#[cfg_attr(feature = "stm32l433rc", path = "stm32l433rc.rs")] +#[cfg_attr(feature = "stm32l433vc", path = "stm32l433vc.rs")] +#[cfg_attr(feature = "stm32l442kc", path = "stm32l442kc.rs")] +#[cfg_attr(feature = "stm32l443cc", path = "stm32l443cc.rs")] +#[cfg_attr(feature = "stm32l443rc", path = "stm32l443rc.rs")] +#[cfg_attr(feature = "stm32l443vc", path = "stm32l443vc.rs")] +#[cfg_attr(feature = "stm32l451cc", path = "stm32l451cc.rs")] +#[cfg_attr(feature = "stm32l451ce", path = "stm32l451ce.rs")] +#[cfg_attr(feature = "stm32l451rc", path = "stm32l451rc.rs")] +#[cfg_attr(feature = "stm32l451re", path = "stm32l451re.rs")] +#[cfg_attr(feature = "stm32l451vc", path = "stm32l451vc.rs")] +#[cfg_attr(feature = "stm32l451ve", path = "stm32l451ve.rs")] +#[cfg_attr(feature = "stm32l452cc", path = "stm32l452cc.rs")] +#[cfg_attr(feature = "stm32l452ce", path = "stm32l452ce.rs")] +#[cfg_attr(feature = "stm32l452rc", path = "stm32l452rc.rs")] +#[cfg_attr(feature = "stm32l452re", path = "stm32l452re.rs")] +#[cfg_attr(feature = "stm32l452vc", path = "stm32l452vc.rs")] +#[cfg_attr(feature = "stm32l452ve", path = "stm32l452ve.rs")] +#[cfg_attr(feature = "stm32l462ce", path = "stm32l462ce.rs")] +#[cfg_attr(feature = "stm32l462re", path = "stm32l462re.rs")] +#[cfg_attr(feature = "stm32l462ve", path = "stm32l462ve.rs")] +#[cfg_attr(feature = "stm32l471qe", path = "stm32l471qe.rs")] +#[cfg_attr(feature = "stm32l471qg", path = "stm32l471qg.rs")] +#[cfg_attr(feature = "stm32l471re", path = "stm32l471re.rs")] +#[cfg_attr(feature = "stm32l471rg", path = "stm32l471rg.rs")] +#[cfg_attr(feature = "stm32l471ve", path = "stm32l471ve.rs")] +#[cfg_attr(feature = "stm32l471vg", path = "stm32l471vg.rs")] +#[cfg_attr(feature = "stm32l471ze", path = "stm32l471ze.rs")] +#[cfg_attr(feature = "stm32l471zg", path = "stm32l471zg.rs")] +#[cfg_attr(feature = "stm32l475rc", path = "stm32l475rc.rs")] +#[cfg_attr(feature = "stm32l475re", path = "stm32l475re.rs")] +#[cfg_attr(feature = "stm32l475rg", path = "stm32l475rg.rs")] +#[cfg_attr(feature = "stm32l475vc", path = "stm32l475vc.rs")] +#[cfg_attr(feature = "stm32l475ve", path = "stm32l475ve.rs")] +#[cfg_attr(feature = "stm32l475vg", path = "stm32l475vg.rs")] +#[cfg_attr(feature = "stm32l476je", path = "stm32l476je.rs")] +#[cfg_attr(feature = "stm32l476jg", path = "stm32l476jg.rs")] +#[cfg_attr(feature = "stm32l476me", path = "stm32l476me.rs")] +#[cfg_attr(feature = "stm32l476mg", path = "stm32l476mg.rs")] +#[cfg_attr(feature = "stm32l476qe", path = "stm32l476qe.rs")] +#[cfg_attr(feature = "stm32l476qg", path = "stm32l476qg.rs")] +#[cfg_attr(feature = "stm32l476rc", path = "stm32l476rc.rs")] +#[cfg_attr(feature = "stm32l476re", path = "stm32l476re.rs")] +#[cfg_attr(feature = "stm32l476rg", path = "stm32l476rg.rs")] +#[cfg_attr(feature = "stm32l476vc", path = "stm32l476vc.rs")] +#[cfg_attr(feature = "stm32l476ve", path = "stm32l476ve.rs")] +#[cfg_attr(feature = "stm32l476vg", path = "stm32l476vg.rs")] +#[cfg_attr(feature = "stm32l476ze", path = "stm32l476ze.rs")] +#[cfg_attr(feature = "stm32l476zg", path = "stm32l476zg.rs")] +#[cfg_attr(feature = "stm32l485jc", path = "stm32l485jc.rs")] +#[cfg_attr(feature = "stm32l485je", path = "stm32l485je.rs")] +#[cfg_attr(feature = "stm32l486jg", path = "stm32l486jg.rs")] +#[cfg_attr(feature = "stm32l486qg", path = "stm32l486qg.rs")] +#[cfg_attr(feature = "stm32l486rg", path = "stm32l486rg.rs")] +#[cfg_attr(feature = "stm32l486vg", path = "stm32l486vg.rs")] +#[cfg_attr(feature = "stm32l486zg", path = "stm32l486zg.rs")] +#[cfg_attr(feature = "stm32l496ae", path = "stm32l496ae.rs")] +#[cfg_attr(feature = "stm32l496ag", path = "stm32l496ag.rs")] +#[cfg_attr(feature = "stm32l496qe", path = "stm32l496qe.rs")] +#[cfg_attr(feature = "stm32l496qg", path = "stm32l496qg.rs")] +#[cfg_attr(feature = "stm32l496re", path = "stm32l496re.rs")] +#[cfg_attr(feature = "stm32l496rg", path = "stm32l496rg.rs")] +#[cfg_attr(feature = "stm32l496ve", path = "stm32l496ve.rs")] +#[cfg_attr(feature = "stm32l496vg", path = "stm32l496vg.rs")] +#[cfg_attr(feature = "stm32l496wg", path = "stm32l496wg.rs")] +#[cfg_attr(feature = "stm32l496ze", path = "stm32l496ze.rs")] +#[cfg_attr(feature = "stm32l496zg", path = "stm32l496zg.rs")] +#[cfg_attr(feature = "stm32l4a6ag", path = "stm32l4a6ag.rs")] +#[cfg_attr(feature = "stm32l4a6qg", path = "stm32l4a6qg.rs")] +#[cfg_attr(feature = "stm32l4a6rg", path = "stm32l4a6rg.rs")] +#[cfg_attr(feature = "stm32l4a6vg", path = "stm32l4a6vg.rs")] +#[cfg_attr(feature = "stm32l4a6zg", path = "stm32l4a6zg.rs")] +#[cfg_attr(feature = "stm32l4p5ae", path = "stm32l4p5ae.rs")] +#[cfg_attr(feature = "stm32l4p5ag", path = "stm32l4p5ag.rs")] +#[cfg_attr(feature = "stm32l4p5ce", path = "stm32l4p5ce.rs")] +#[cfg_attr(feature = "stm32l4p5cg", path = "stm32l4p5cg.rs")] +#[cfg_attr(feature = "stm32l4p5qe", path = "stm32l4p5qe.rs")] +#[cfg_attr(feature = "stm32l4p5qg", path = "stm32l4p5qg.rs")] +#[cfg_attr(feature = "stm32l4p5re", path = "stm32l4p5re.rs")] +#[cfg_attr(feature = "stm32l4p5rg", path = "stm32l4p5rg.rs")] +#[cfg_attr(feature = "stm32l4p5ve", path = "stm32l4p5ve.rs")] +#[cfg_attr(feature = "stm32l4p5vg", path = "stm32l4p5vg.rs")] +#[cfg_attr(feature = "stm32l4p5ze", path = "stm32l4p5ze.rs")] +#[cfg_attr(feature = "stm32l4p5zg", path = "stm32l4p5zg.rs")] +#[cfg_attr(feature = "stm32l4q5ag", path = "stm32l4q5ag.rs")] +#[cfg_attr(feature = "stm32l4q5cg", path = "stm32l4q5cg.rs")] +#[cfg_attr(feature = "stm32l4q5qg", path = "stm32l4q5qg.rs")] +#[cfg_attr(feature = "stm32l4q5rg", path = "stm32l4q5rg.rs")] +#[cfg_attr(feature = "stm32l4q5vg", path = "stm32l4q5vg.rs")] +#[cfg_attr(feature = "stm32l4q5zg", path = "stm32l4q5zg.rs")] +#[cfg_attr(feature = "stm32l4r5ag", path = "stm32l4r5ag.rs")] +#[cfg_attr(feature = "stm32l4r5ai", path = "stm32l4r5ai.rs")] +#[cfg_attr(feature = "stm32l4r5qg", path = "stm32l4r5qg.rs")] +#[cfg_attr(feature = "stm32l4r5qi", path = "stm32l4r5qi.rs")] +#[cfg_attr(feature = "stm32l4r5vg", path = "stm32l4r5vg.rs")] +#[cfg_attr(feature = "stm32l4r5vi", path = "stm32l4r5vi.rs")] +#[cfg_attr(feature = "stm32l4r5zg", path = "stm32l4r5zg.rs")] +#[cfg_attr(feature = "stm32l4r5zi", path = "stm32l4r5zi.rs")] +#[cfg_attr(feature = "stm32l4r7ai", path = "stm32l4r7ai.rs")] +#[cfg_attr(feature = "stm32l4r7vi", path = "stm32l4r7vi.rs")] +#[cfg_attr(feature = "stm32l4r7zi", path = "stm32l4r7zi.rs")] +#[cfg_attr(feature = "stm32l4r9ag", path = "stm32l4r9ag.rs")] +#[cfg_attr(feature = "stm32l4r9ai", path = "stm32l4r9ai.rs")] +#[cfg_attr(feature = "stm32l4r9vg", path = "stm32l4r9vg.rs")] +#[cfg_attr(feature = "stm32l4r9vi", path = "stm32l4r9vi.rs")] +#[cfg_attr(feature = "stm32l4r9zg", path = "stm32l4r9zg.rs")] +#[cfg_attr(feature = "stm32l4r9zi", path = "stm32l4r9zi.rs")] +#[cfg_attr(feature = "stm32l4s5ai", path = "stm32l4s5ai.rs")] +#[cfg_attr(feature = "stm32l4s5qi", path = "stm32l4s5qi.rs")] +#[cfg_attr(feature = "stm32l4s5vi", path = "stm32l4s5vi.rs")] +#[cfg_attr(feature = "stm32l4s5zi", path = "stm32l4s5zi.rs")] +#[cfg_attr(feature = "stm32l4s7ai", path = "stm32l4s7ai.rs")] +#[cfg_attr(feature = "stm32l4s7vi", path = "stm32l4s7vi.rs")] +#[cfg_attr(feature = "stm32l4s7zi", path = "stm32l4s7zi.rs")] +#[cfg_attr(feature = "stm32l4s9ai", path = "stm32l4s9ai.rs")] +#[cfg_attr(feature = "stm32l4s9vi", path = "stm32l4s9vi.rs")] +#[cfg_attr(feature = "stm32l4s9zi", path = "stm32l4s9zi.rs")] +mod chip; +pub use chip::*; diff --git a/embassy-stm32/src/pac/regs.rs b/embassy-stm32/src/pac/regs.rs new file mode 100644 index 000000000..a31ef04ca --- /dev/null +++ b/embassy-stm32/src/pac/regs.rs @@ -0,0 +1,5517 @@ +#![no_std] +#![doc = "Peripheral access API (generated using svd2rust v0.17.0 (507115a 2021-04-19))"] +pub mod gpio_v1 { + use crate::generic::*; + #[doc = "General purpose I/O"] + #[derive(Copy, Clone)] + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "Port configuration register low (GPIOn_CRL)"] + pub fn cr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } + } + #[doc = "Port input data register (GPIOn_IDR)"] + pub fn idr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Port output data register (GPIOn_ODR)"] + pub fn odr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + pub fn bsrr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Port bit reset register (GPIOn_BRR)"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Port configuration lock register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port A Lock bit"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) + } + #[doc = "Port A Lock bit"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Lock key"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) + } + #[doc = "Lock key"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + } + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) + } + } + #[doc = "Port output data register (GPIOn_ODR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Set bit"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Set bit"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Reset bit"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Reset bit"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) + } + } + #[doc = "Port configuration register (GPIOn_CRx)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Port n mode bits"] + pub fn mode(&self, n: usize) -> super::vals::Mode { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Mode(val as u8) + } + #[doc = "Port n mode bits"] + pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Port n configuration bits"] + pub fn cnf(&self, n: usize) -> super::vals::Cnf { + assert!(n < 8usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Cnf(val as u8) + } + #[doc = "Port n configuration bits"] + pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) { + assert!(n < 8usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "Port bit reset register (GPIOn_BRR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "Reset bit"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Reset bit"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Port input data register (GPIOn_IDR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mode(pub u8); + impl Mode { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "Output mode 10 MHz"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Output mode 2 MHz"] + pub const OUTPUT2: Self = Self(0x02); + #[doc = "Output mode 50 MHz"] + pub const OUTPUT50: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Brw(pub u8); + impl Brw { + #[doc = "No action on the corresponding ODx bit"] + pub const NOACTION: Self = Self(0); + #[doc = "Reset the ODx bit"] + pub const RESET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] + pub const LOW: Self = Self(0); + #[doc = "Input is logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "No action on the corresponding ODx bit"] + pub const NOACTION: Self = Self(0); + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cnf(pub u8); + impl Cnf { + #[doc = "Analog mode / Push-Pull mode"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Floating input (reset state) / Open Drain-Mode"] + pub const OPENDRAIN: Self = Self(0x01); + #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] + pub const ALTPUSHPULL: Self = Self(0x02); + #[doc = "Alternate Function Open-Drain Mode"] + pub const ALTOPENDRAIN: Self = Self(0x03); + } + } +} +pub mod syscfg_f4 { + use crate::generic::*; + #[doc = "System configuration controller"] + #[derive(Copy, Clone)] + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "memory remap register"] + pub fn memrm(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "peripheral mode configuration register"] + pub fn pmc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "external interrupt configuration register"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "Compensation cell control register"] + pub fn cmpcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "peripheral mode configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pmc(pub u32); + impl Pmc { + #[doc = "ADC1DC2"] + pub const fn adc1dc2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "ADC1DC2"] + pub fn set_adc1dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "ADC2DC2"] + pub const fn adc2dc2(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "ADC2DC2"] + pub fn set_adc2dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "ADC3DC2"] + pub const fn adc3dc2(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "ADC3DC2"] + pub fn set_adc3dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Ethernet PHY interface selection"] + pub const fn mii_rmii_sel(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Ethernet PHY interface selection"] + pub fn set_mii_rmii_sel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + } + impl Default for Pmc { + fn default() -> Pmc { + Pmc(0) + } + } + #[doc = "memory remap register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Memrm(pub u32); + impl Memrm { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "Flash bank mode selection"] + pub const fn fb_mode(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Flash bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FMC memory mapping swap"] + pub const fn swp_fmc(&self) -> u8 { + let val = (self.0 >> 10usize) & 0x03; + val as u8 + } + #[doc = "FMC memory mapping swap"] + pub fn set_swp_fmc(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize); + } + } + impl Default for Memrm { + fn default() -> Memrm { + Memrm(0) + } + } + #[doc = "external interrupt configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI x configuration"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI x configuration"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "Compensation cell control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cmpcr(pub u32); + impl Cmpcr { + #[doc = "Compensation cell power-down"] + pub const fn cmp_pd(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Compensation cell power-down"] + pub fn set_cmp_pd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "READY"] + pub const fn ready(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "READY"] + pub fn set_ready(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Cmpcr { + fn default() -> Cmpcr { + Cmpcr(0) + } + } + } +} +pub mod generic { + use core::marker::PhantomData; + #[derive(Copy, Clone)] + pub struct RW; + #[derive(Copy, Clone)] + pub struct R; + #[derive(Copy, Clone)] + pub struct W; + mod sealed { + use super::*; + pub trait Access {} + impl Access for R {} + impl Access for W {} + impl Access for RW {} + } + pub trait Access: sealed::Access + Copy {} + impl Access for R {} + impl Access for W {} + impl Access for RW {} + pub trait Read: Access {} + impl Read for RW {} + impl Read for R {} + pub trait Write: Access {} + impl Write for RW {} + impl Write for W {} + #[derive(Copy, Clone)] + pub struct Reg { + ptr: *mut u8, + phantom: PhantomData<*mut (T, A)>, + } + unsafe impl Send for Reg {} + unsafe impl Sync for Reg {} + impl Reg { + pub fn from_ptr(ptr: *mut u8) -> Self { + Self { + ptr, + phantom: PhantomData, + } + } + pub fn ptr(&self) -> *mut T { + self.ptr as _ + } + } + impl Reg { + pub unsafe fn read(&self) -> T { + (self.ptr as *mut T).read_volatile() + } + } + impl Reg { + pub unsafe fn write_value(&self, val: T) { + (self.ptr as *mut T).write_volatile(val) + } + } + impl Reg { + pub unsafe fn write(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = Default::default(); + let res = f(&mut val); + self.write_value(val); + res + } + } + impl Reg { + pub unsafe fn modify(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = self.read(); + let res = f(&mut val); + self.write_value(val); + res + } + } +} +pub mod gpio_v2 { + use crate::generic::*; + #[doc = "General-purpose I/Os"] + #[derive(Copy, Clone)] + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "GPIO port mode register"] + pub fn moder(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "GPIO port output type register"] + pub fn otyper(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "GPIO port output speed register"] + pub fn ospeedr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "GPIO port pull-up/pull-down register"] + pub fn pupdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "GPIO port input data register"] + pub fn idr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "GPIO port output data register"] + pub fn odr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "GPIO port bit set/reset register"] + pub fn bsrr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "GPIO port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "GPIO alternate function register (low, high)"] + pub fn afr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ot(pub u8); + impl Ot { + #[doc = "Output push-pull (reset state)"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Output open-drain"] + pub const OPENDRAIN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pupdr(pub u8); + impl Pupdr { + #[doc = "No pull-up, pull-down"] + pub const FLOATING: Self = Self(0); + #[doc = "Pull-up"] + pub const PULLUP: Self = Self(0x01); + #[doc = "Pull-down"] + pub const PULLDOWN: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Moder(pub u8); + impl Moder { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "General purpose output mode"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Alternate function mode"] + pub const ALTERNATE: Self = Self(0x02); + #[doc = "Analog mode"] + pub const ANALOG: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Afr(pub u8); + impl Afr { + #[doc = "AF0"] + pub const AF0: Self = Self(0); + #[doc = "AF1"] + pub const AF1: Self = Self(0x01); + #[doc = "AF2"] + pub const AF2: Self = Self(0x02); + #[doc = "AF3"] + pub const AF3: Self = Self(0x03); + #[doc = "AF4"] + pub const AF4: Self = Self(0x04); + #[doc = "AF5"] + pub const AF5: Self = Self(0x05); + #[doc = "AF6"] + pub const AF6: Self = Self(0x06); + #[doc = "AF7"] + pub const AF7: Self = Self(0x07); + #[doc = "AF8"] + pub const AF8: Self = Self(0x08); + #[doc = "AF9"] + pub const AF9: Self = Self(0x09); + #[doc = "AF10"] + pub const AF10: Self = Self(0x0a); + #[doc = "AF11"] + pub const AF11: Self = Self(0x0b); + #[doc = "AF12"] + pub const AF12: Self = Self(0x0c); + #[doc = "AF13"] + pub const AF13: Self = Self(0x0d); + #[doc = "AF14"] + pub const AF14: Self = Self(0x0e); + #[doc = "AF15"] + pub const AF15: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Brw(pub u8); + impl Brw { + #[doc = "Resets the corresponding ODRx bit"] + pub const RESET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] + pub const LOW: Self = Self(0); + #[doc = "Input is logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ospeedr(pub u8); + impl Ospeedr { + #[doc = "Low speed"] + pub const LOWSPEED: Self = Self(0); + #[doc = "Medium speed"] + pub const MEDIUMSPEED: Self = Self(0x01); + #[doc = "High speed"] + pub const HIGHSPEED: Self = Self(0x02); + #[doc = "Very high speed"] + pub const VERYHIGHSPEED: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "GPIO port mode register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Moder(pub u32); + impl Moder { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn moder(&self, n: usize) -> super::vals::Moder { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Moder(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Moder { + fn default() -> Moder { + Moder(0) + } + } + #[doc = "GPIO port output type register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Otyper(pub u32); + impl Otyper { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ot(&self, n: usize) -> super::vals::Ot { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ot(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Otyper { + fn default() -> Otyper { + Otyper(0) + } + } + #[doc = "GPIO port output speed register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ospeedr(pub u32); + impl Ospeedr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Ospeedr(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Ospeedr { + fn default() -> Ospeedr { + Ospeedr(0) + } + } + #[doc = "GPIO port bit set/reset register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Port x set bit y (y= 0..15)"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) + } + } + #[doc = "GPIO alternate function register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Afr(pub u32); + impl Afr { + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn afr(&self, n: usize) -> super::vals::Afr { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Afr(val as u8) + } + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for Afr { + fn default() -> Afr { + Afr(0) + } + } + #[doc = "GPIO port configuration lock register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + } + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) + } + } + #[doc = "GPIO port input data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data (y = 0..15)"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data (y = 0..15)"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + #[doc = "GPIO port pull-up/pull-down register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pupdr(pub u32); + impl Pupdr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn pupdr(&self, n: usize) -> super::vals::Pupdr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Pupdr(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Pupdr { + fn default() -> Pupdr { + Pupdr(0) + } + } + #[doc = "GPIO port output data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data (y = 0..15)"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data (y = 0..15)"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } + } +} +pub mod timer_v1 { + use crate::generic::*; + #[doc = "General purpose 32-bit timer"] + #[derive(Copy, Clone)] + pub struct TimGp32(pub *mut u8); + unsafe impl Send for TimGp32 {} + unsafe impl Sync for TimGp32 {} + impl TimGp32 { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "Basic timer"] + #[derive(Copy, Clone)] + pub struct TimBasic(pub *mut u8); + unsafe impl Send for TimBasic {} + unsafe impl Sync for TimBasic {} + impl TimBasic { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + } + #[doc = "General purpose 16-bit timer"] + #[derive(Copy, Clone)] + pub struct TimGp16(pub *mut u8); + unsafe impl Send for TimGp16 {} + unsafe impl Sync for TimGp16 {} + impl TimGp16 { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "Advanced-timers"] + #[derive(Copy, Clone)] + pub struct TimAdv(pub *mut u8); + unsafe impl Send for TimAdv {} + unsafe impl Sync for TimAdv {} + impl TimAdv { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "repetition counter register"] + pub fn rcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(48usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "break and dead-time register"] + pub fn bdtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(68usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Counter used as upcounter"] + pub const UP: Self = Self(0); + #[doc = "Counter used as downcounter"] + pub const DOWN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Opm(pub u8); + impl Opm { + #[doc = "Counter is not stopped at update event"] + pub const DISABLED: Self = Self(0); + #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cms(pub u8); + impl Cms { + #[doc = "The counter counts up or down depending on the direction bit"] + pub const EDGEALIGNED: Self = Self(0); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] + pub const CENTERALIGNED1: Self = Self(0x01); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] + pub const CENTERALIGNED2: Self = Self(0x02); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] + pub const CENTERALIGNED3: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ts(pub u8); + impl Ts { + #[doc = "Internal Trigger 0 (ITR0)"] + pub const ITR0: Self = Self(0); + #[doc = "Internal Trigger 1 (ITR1)"] + pub const ITR1: Self = Self(0x01); + #[doc = "Internal Trigger 2 (ITR2)"] + pub const ITR2: Self = Self(0x02); + #[doc = "TI1 Edge Detector (TI1F_ED)"] + pub const TI1F_ED: Self = Self(0x04); + #[doc = "Filtered Timer Input 1 (TI1FP1)"] + pub const TI1FP1: Self = Self(0x05); + #[doc = "Filtered Timer Input 2 (TI2FP2)"] + pub const TI2FP2: Self = Self(0x06); + #[doc = "External Trigger input (ETRF)"] + pub const ETRF: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrOutputCcs(pub u8); + impl CcmrOutputCcs { + #[doc = "CCx channel is configured as output"] + pub const OUTPUT: Self = Self(0); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etps(pub u8); + impl Etps { + #[doc = "Prescaler OFF"] + pub const DIV1: Self = Self(0); + #[doc = "ETRP frequency divided by 2"] + pub const DIV2: Self = Self(0x01); + #[doc = "ETRP frequency divided by 4"] + pub const DIV4: Self = Self(0x02); + #[doc = "ETRP frequency divided by 8"] + pub const DIV8: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Tis(pub u8); + impl Tis { + #[doc = "The TIMx_CH1 pin is connected to TI1 input"] + pub const NORMAL: Self = Self(0); + #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] + pub const XOR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etp(pub u8); + impl Etp { + #[doc = "ETR is noninverted, active at high level or rising edge"] + pub const NOTINVERTED: Self = Self(0); + #[doc = "ETR is inverted, active at low level or falling edge"] + pub const INVERTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrInputCcs(pub u8); + impl CcmrInputCcs { + #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"] + pub const TI4: Self = Self(0x01); + #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"] + pub const TI3: Self = Self(0x02); + #[doc = "CCx channel is configured as input, ICx is mapped on TRC"] + pub const TRC: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocpe(pub u8); + impl Ocpe { + #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] + pub const DISABLED: Self = Self(0); + #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mms(pub u8); + impl Mms { + #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"] + pub const RESET: Self = Self(0); + #[doc = "The counter enable signal, CNT_EN, is used as trigger output"] + pub const ENABLE: Self = Self(0x01); + #[doc = "The update event is selected as trigger output"] + pub const UPDATE: Self = Self(0x02); + #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] + pub const COMPAREPULSE: Self = Self(0x03); + #[doc = "OC1REF signal is used as trigger output"] + pub const COMPAREOC1: Self = Self(0x04); + #[doc = "OC2REF signal is used as trigger output"] + pub const COMPAREOC2: Self = Self(0x05); + #[doc = "OC3REF signal is used as trigger output"] + pub const COMPAREOC3: Self = Self(0x06); + #[doc = "OC4REF signal is used as trigger output"] + pub const COMPAREOC4: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Arpe(pub u8); + impl Arpe { + #[doc = "TIMx_APRR register is not buffered"] + pub const DISABLED: Self = Self(0); + #[doc = "TIMx_APRR register is buffered"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ccds(pub u8); + impl Ccds { + #[doc = "CCx DMA request sent when CCx event occurs"] + pub const ONCOMPARE: Self = Self(0); + #[doc = "CCx DMA request sent when update event occurs"] + pub const ONUPDATE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ckd(pub u8); + impl Ckd { + #[doc = "t_DTS = t_CK_INT"] + pub const DIV1: Self = Self(0); + #[doc = "t_DTS = 2 × t_CK_INT"] + pub const DIV2: Self = Self(0x01); + #[doc = "t_DTS = 4 × t_CK_INT"] + pub const DIV4: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Msm(pub u8); + impl Msm { + #[doc = "No action"] + pub const NOSYNC: Self = Self(0); + #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] + pub const SYNC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Icf(pub u8); + impl Icf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ece(pub u8); + impl Ece { + #[doc = "External clock mode 2 disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sms(pub u8); + impl Sms { + #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + pub const DISABLED: Self = Self(0); + #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] + pub const ENCODER_MODE_1: Self = Self(0x01); + #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] + pub const ENCODER_MODE_2: Self = Self(0x02); + #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] + pub const ENCODER_MODE_3: Self = Self(0x03); + #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] + pub const RESET_MODE: Self = Self(0x04); + #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] + pub const GATED_MODE: Self = Self(0x05); + #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] + pub const TRIGGER_MODE: Self = Self(0x06); + #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] + pub const EXT_CLOCK_MODE: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossr(pub u8); + impl Ossr { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossi(pub u8); + impl Ossi { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are forced to idle level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocm(pub u8); + impl Ocm { + #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] + pub const FROZEN: Self = Self(0); + #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] + pub const ACTIVEONMATCH: Self = Self(0x01); + #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] + pub const INACTIVEONMATCH: Self = Self(0x02); + #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] + pub const TOGGLE: Self = Self(0x03); + #[doc = "OCyREF is forced low"] + pub const FORCEINACTIVE: Self = Self(0x04); + #[doc = "OCyREF is forced high"] + pub const FORCEACTIVE: Self = Self(0x05); + #[doc = "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] + pub const PWMMODE1: Self = Self(0x06); + #[doc = "Inversely to PwmMode1"] + pub const PWMMODE2: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Urs(pub u8); + impl Urs { + #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] + pub const ANYEVENT: Self = Self(0); + #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] + pub const COUNTERONLY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etf(pub u8); + impl Etf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr16(pub u32); + impl Ccr16 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ccr16 { + fn default() -> Ccr16 { + Ccr16(0) + } + } + #[doc = "capture/compare mode register 2 (output mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrOutput(pub u32); + impl CcmrOutput { + #[doc = "Capture/Compare 3 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrOutputCcs(val as u8) + } + #[doc = "Capture/Compare 3 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Output compare 3 fast enable"] + pub fn ocfe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 fast enable"] + pub fn set_ocfe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 preload enable"] + pub fn ocpe(&self, n: usize) -> super::vals::Ocpe { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ocpe(val as u8) + } + #[doc = "Output compare 3 preload enable"] + pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 mode"] + pub fn ocm(&self, n: usize) -> super::vals::Ocm { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x07; + super::vals::Ocm(val as u8) + } + #[doc = "Output compare 3 mode"] + pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs); + } + #[doc = "Output compare 3 clear enable"] + pub fn occe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 clear enable"] + pub fn set_occe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcmrOutput { + fn default() -> CcmrOutput { + CcmrOutput(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierBasic(pub u32); + impl DierBasic { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for DierBasic { + fn default() -> DierBasic { + DierBasic(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr32(pub u32); + impl Ccr32 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Ccr32 { + fn default() -> Ccr32 { + Ccr32(0) + } + } + #[doc = "prescaler"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Psc(pub u32); + impl Psc { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Psc { + fn default() -> Psc { + Psc(0) + } + } + #[doc = "break and dead-time register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bdtr(pub u32); + impl Bdtr { + #[doc = "Dead-time generator setup"] + pub const fn dtg(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Dead-time generator setup"] + pub fn set_dtg(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Lock configuration"] + pub const fn lock(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x03; + val as u8 + } + #[doc = "Lock configuration"] + pub fn set_lock(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + } + #[doc = "Off-state selection for Idle mode"] + pub const fn ossi(&self) -> super::vals::Ossi { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Ossi(val as u8) + } + #[doc = "Off-state selection for Idle mode"] + pub fn set_ossi(&mut self, val: super::vals::Ossi) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Off-state selection for Run mode"] + pub const fn ossr(&self) -> super::vals::Ossr { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Ossr(val as u8) + } + #[doc = "Off-state selection for Run mode"] + pub fn set_ossr(&mut self, val: super::vals::Ossr) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Break enable"] + pub const fn bke(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Break enable"] + pub fn set_bke(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Break polarity"] + pub const fn bkp(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Break polarity"] + pub fn set_bkp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Automatic output enable"] + pub const fn aoe(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Automatic output enable"] + pub fn set_aoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Main output enable"] + pub const fn moe(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Main output enable"] + pub fn set_moe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + } + impl Default for Bdtr { + fn default() -> Bdtr { + Bdtr(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrBasic(pub u32); + impl SrBasic { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for SrBasic { + fn default() -> SrBasic { + SrBasic(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrGp(pub u32); + impl SrGp { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for SrGp { + fn default() -> SrGp { + SrGp(0) + } + } + #[doc = "DMA address for full transfer"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dmar(pub u32); + impl Dmar { + #[doc = "DMA register for burst accesses"] + pub const fn dmab(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "DMA register for burst accesses"] + pub fn set_dmab(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dmar { + fn default() -> Dmar { + Dmar(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrAdv(pub u32); + impl EgrAdv { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrAdv { + fn default() -> EgrAdv { + EgrAdv(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrBasic(pub u32); + impl EgrBasic { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for EgrBasic { + fn default() -> EgrBasic { + EgrBasic(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt32(pub u32); + impl Cnt32 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Cnt32 { + fn default() -> Cnt32 { + Cnt32(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierGp(pub u32); + impl DierGp { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for DierGp { + fn default() -> DierGp { + DierGp(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Gp(pub u32); + impl Cr1Gp { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Center-aligned mode selection"] + pub const fn cms(&self) -> super::vals::Cms { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Cms(val as u8) + } + #[doc = "Center-aligned mode selection"] + pub fn set_cms(&mut self, val: super::vals::Cms) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Clock division"] + pub const fn ckd(&self) -> super::vals::Ckd { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Ckd(val as u8) + } + #[doc = "Clock division"] + pub fn set_ckd(&mut self, val: super::vals::Ckd) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + } + impl Default for Cr1Gp { + fn default() -> Cr1Gp { + Cr1Gp(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Adv(pub u32); + impl Cr2Adv { + #[doc = "Capture/compare preloaded control"] + pub const fn ccpc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare preloaded control"] + pub fn set_ccpc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare control update selection"] + pub const fn ccus(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare control update selection"] + pub fn set_ccus(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Output Idle state 1"] + pub fn ois(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output Idle state 1"] + pub const fn ois1n(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois1n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Output Idle state 2"] + pub const fn ois2n(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 2"] + pub fn set_ois2n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Output Idle state 3"] + pub const fn ois3n(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 3"] + pub fn set_ois3n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr2Adv { + fn default() -> Cr2Adv { + Cr2Adv(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr16(pub u32); + impl Arr16 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Arr16 { + fn default() -> Arr16 { + Arr16(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierAdv(pub u32); + impl DierAdv { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt enable"] + pub const fn comie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt enable"] + pub fn set_comie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt enable"] + pub const fn bie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt enable"] + pub fn set_bie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM DMA request enable"] + pub const fn comde(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "COM DMA request enable"] + pub fn set_comde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for DierAdv { + fn default() -> DierAdv { + DierAdv(0) + } + } + #[doc = "DMA control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dcr(pub u32); + impl Dcr { + #[doc = "DMA base address"] + pub const fn dba(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DMA base address"] + pub fn set_dba(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DMA burst length"] + pub const fn dbl(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DMA burst length"] + pub fn set_dbl(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + } + impl Default for Dcr { + fn default() -> Dcr { + Dcr(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr32(pub u32); + impl Arr32 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Arr32 { + fn default() -> Arr32 { + Arr32(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerAdv(pub u32); + impl CcerAdv { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn ccne(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn set_ccne(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerAdv { + fn default() -> CcerAdv { + CcerAdv(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Basic(pub u32); + impl Cr2Basic { + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + } + impl Default for Cr2Basic { + fn default() -> Cr2Basic { + Cr2Basic(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerGp(pub u32); + impl CcerGp { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerGp { + fn default() -> CcerGp { + CcerGp(0) + } + } + #[doc = "slave mode control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Smcr(pub u32); + impl Smcr { + #[doc = "Slave mode selection"] + pub const fn sms(&self) -> super::vals::Sms { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Sms(val as u8) + } + #[doc = "Slave mode selection"] + pub fn set_sms(&mut self, val: super::vals::Sms) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize); + } + #[doc = "Trigger selection"] + pub const fn ts(&self) -> super::vals::Ts { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Ts(val as u8) + } + #[doc = "Trigger selection"] + pub fn set_ts(&mut self, val: super::vals::Ts) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "Master/Slave mode"] + pub const fn msm(&self) -> super::vals::Msm { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Msm(val as u8) + } + #[doc = "Master/Slave mode"] + pub fn set_msm(&mut self, val: super::vals::Msm) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "External trigger filter"] + pub const fn etf(&self) -> super::vals::Etf { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Etf(val as u8) + } + #[doc = "External trigger filter"] + pub fn set_etf(&mut self, val: super::vals::Etf) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); + } + #[doc = "External trigger prescaler"] + pub const fn etps(&self) -> super::vals::Etps { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Etps(val as u8) + } + #[doc = "External trigger prescaler"] + pub fn set_etps(&mut self, val: super::vals::Etps) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "External clock enable"] + pub const fn ece(&self) -> super::vals::Ece { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Ece(val as u8) + } + #[doc = "External clock enable"] + pub fn set_ece(&mut self, val: super::vals::Ece) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "External trigger polarity"] + pub const fn etp(&self) -> super::vals::Etp { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Etp(val as u8) + } + #[doc = "External trigger polarity"] + pub fn set_etp(&mut self, val: super::vals::Etp) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Smcr { + fn default() -> Smcr { + Smcr(0) + } + } + #[doc = "capture/compare mode register 1 (input mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrInput(pub u32); + impl CcmrInput { + #[doc = "Capture/Compare 1 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrInputCcs(val as u8) + } + #[doc = "Capture/Compare 1 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 prescaler"] + pub fn icpsc(&self, n: usize) -> u8 { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + val as u8 + } + #[doc = "Input capture 1 prescaler"] + pub fn set_icpsc(&mut self, n: usize, val: u8) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 filter"] + pub fn icf(&self, n: usize) -> super::vals::Icf { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Icf(val as u8) + } + #[doc = "Input capture 1 filter"] + pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for CcmrInput { + fn default() -> CcmrInput { + CcmrInput(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrGp(pub u32); + impl EgrGp { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrGp { + fn default() -> EgrGp { + EgrGp(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Gp(pub u32); + impl Cr2Gp { + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr2Gp { + fn default() -> Cr2Gp { + Cr2Gp(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt16(pub u32); + impl Cnt16 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Cnt16 { + fn default() -> Cnt16 { + Cnt16(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Basic(pub u32); + impl Cr1Basic { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr1Basic { + fn default() -> Cr1Basic { + Cr1Basic(0) + } + } + #[doc = "repetition counter register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rcr(pub u32); + impl Rcr { + #[doc = "Repetition counter value"] + pub const fn rep(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Repetition counter value"] + pub fn set_rep(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Rcr { + fn default() -> Rcr { + Rcr(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrAdv(pub u32); + impl SrAdv { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for SrAdv { + fn default() -> SrAdv { + SrAdv(0) + } + } + } +} +pub mod dma_v2 { + use crate::generic::*; + #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] + #[derive(Copy, Clone)] + pub struct St(pub *mut u8); + unsafe impl Send for St {} + unsafe impl Sync for St {} + impl St { + #[doc = "stream x configuration register"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "stream x number of data register"] + pub fn ndtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "stream x peripheral address register"] + pub fn par(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "stream x memory 0 address register"] + pub fn m0ar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "stream x memory 1 address register"] + pub fn m1ar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "stream x FIFO control register"] + pub fn fcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + #[doc = "DMA controller"] + #[derive(Copy, Clone)] + pub struct Dma(pub *mut u8); + unsafe impl Send for Dma {} + unsafe impl Sync for Dma {} + impl Dma { + #[doc = "low interrupt status register"] + pub fn isr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } + } + #[doc = "low interrupt flag clear register"] + pub fn ifcr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] + pub fn st(self, n: usize) -> St { + assert!(n < 8usize); + unsafe { St(self.0.add(16usize + n * 24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "stream x number of data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ndtr(pub u32); + impl Ndtr { + #[doc = "Number of data items to transfer"] + pub const fn ndt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Number of data items to transfer"] + pub fn set_ndt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ndtr { + fn default() -> Ndtr { + Ndtr(0) + } + } + #[doc = "stream x FIFO control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Fcr(pub u32); + impl Fcr { + #[doc = "FIFO threshold selection"] + pub const fn fth(&self) -> super::vals::Fth { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Fth(val as u8) + } + #[doc = "FIFO threshold selection"] + pub fn set_fth(&mut self, val: super::vals::Fth) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize); + } + #[doc = "Direct mode disable"] + pub const fn dmdis(&self) -> super::vals::Dmdis { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Dmdis(val as u8) + } + #[doc = "Direct mode disable"] + pub fn set_dmdis(&mut self, val: super::vals::Dmdis) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "FIFO status"] + pub const fn fs(&self) -> super::vals::Fs { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Fs(val as u8) + } + #[doc = "FIFO status"] + pub fn set_fs(&mut self, val: super::vals::Fs) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "FIFO error interrupt enable"] + pub const fn feie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "FIFO error interrupt enable"] + pub fn set_feie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Fcr { + fn default() -> Fcr { + Fcr(0) + } + } + #[doc = "stream x configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Stream enable / flag stream ready when read low"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Stream enable / flag stream ready when read low"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Direct mode error interrupt enable"] + pub const fn dmeie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Direct mode error interrupt enable"] + pub fn set_dmeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Transfer error interrupt enable"] + pub const fn teie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Transfer error interrupt enable"] + pub fn set_teie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Half transfer interrupt enable"] + pub const fn htie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Half transfer interrupt enable"] + pub fn set_htie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Transfer complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Transfer complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Peripheral flow controller"] + pub const fn pfctrl(&self) -> super::vals::Pfctrl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Pfctrl(val as u8) + } + #[doc = "Peripheral flow controller"] + pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "Data transfer direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 6usize) & 0x03; + super::vals::Dir(val as u8) + } + #[doc = "Data transfer direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize); + } + #[doc = "Circular mode"] + pub const fn circ(&self) -> super::vals::Circ { + let val = (self.0 >> 8usize) & 0x01; + super::vals::Circ(val as u8) + } + #[doc = "Circular mode"] + pub fn set_circ(&mut self, val: super::vals::Circ) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize); + } + #[doc = "Peripheral increment mode"] + pub const fn pinc(&self) -> super::vals::Inc { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Peripheral increment mode"] + pub fn set_pinc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Memory increment mode"] + pub const fn minc(&self) -> super::vals::Inc { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Memory increment mode"] + pub fn set_minc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Peripheral data size"] + pub const fn psize(&self) -> super::vals::Size { + let val = (self.0 >> 11usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Peripheral data size"] + pub fn set_psize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize); + } + #[doc = "Memory data size"] + pub const fn msize(&self) -> super::vals::Size { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Memory data size"] + pub fn set_msize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize); + } + #[doc = "Peripheral increment offset size"] + pub const fn pincos(&self) -> super::vals::Pincos { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Pincos(val as u8) + } + #[doc = "Peripheral increment offset size"] + pub fn set_pincos(&mut self, val: super::vals::Pincos) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + #[doc = "Priority level"] + pub const fn pl(&self) -> super::vals::Pl { + let val = (self.0 >> 16usize) & 0x03; + super::vals::Pl(val as u8) + } + #[doc = "Priority level"] + pub fn set_pl(&mut self, val: super::vals::Pl) { + self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize); + } + #[doc = "Double buffer mode"] + pub const fn dbm(&self) -> super::vals::Dbm { + let val = (self.0 >> 18usize) & 0x01; + super::vals::Dbm(val as u8) + } + #[doc = "Double buffer mode"] + pub fn set_dbm(&mut self, val: super::vals::Dbm) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize); + } + #[doc = "Current target (only in double buffer mode)"] + pub const fn ct(&self) -> super::vals::Ct { + let val = (self.0 >> 19usize) & 0x01; + super::vals::Ct(val as u8) + } + #[doc = "Current target (only in double buffer mode)"] + pub fn set_ct(&mut self, val: super::vals::Ct) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize); + } + #[doc = "Peripheral burst transfer configuration"] + pub const fn pburst(&self) -> super::vals::Burst { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Burst(val as u8) + } + #[doc = "Peripheral burst transfer configuration"] + pub fn set_pburst(&mut self, val: super::vals::Burst) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize); + } + #[doc = "Memory burst transfer configuration"] + pub const fn mburst(&self) -> super::vals::Burst { + let val = (self.0 >> 23usize) & 0x03; + super::vals::Burst(val as u8) + } + #[doc = "Memory burst transfer configuration"] + pub fn set_mburst(&mut self, val: super::vals::Burst) { + self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize); + } + #[doc = "Channel selection"] + pub const fn chsel(&self) -> u8 { + let val = (self.0 >> 25usize) & 0x0f; + val as u8 + } + #[doc = "Channel selection"] + pub fn set_chsel(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "low interrupt status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Isr(pub u32); + impl Isr { + #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] + pub fn feif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] + pub fn set_feif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] + pub fn dmeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] + pub fn set_dmeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x transfer error interrupt flag (x=3..0)"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x transfer error interrupt flag (x=3..0)"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x half transfer interrupt flag (x=3..0)"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x half transfer interrupt flag (x=3..0)"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Isr { + fn default() -> Isr { + Isr(0) + } + } + #[doc = "low interrupt flag clear register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ifcr(pub u32); + impl Ifcr { + #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] + pub fn cfeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] + pub fn set_cfeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"] + pub fn cdmeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"] + pub fn set_cdmeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"] + pub fn cteif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"] + pub fn set_cteif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"] + pub fn chtif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"] + pub fn set_chtif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] + pub fn ctcif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] + pub fn set_ctcif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Ifcr { + fn default() -> Ifcr { + Ifcr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Inc(pub u8); + impl Inc { + #[doc = "Address pointer is fixed"] + pub const FIXED: Self = Self(0); + #[doc = "Address pointer is incremented after each data transfer"] + pub const INCREMENTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pfctrl(pub u8); + impl Pfctrl { + #[doc = "The DMA is the flow controller"] + pub const DMA: Self = Self(0); + #[doc = "The peripheral is the flow controller"] + pub const PERIPHERAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Fth(pub u8); + impl Fth { + #[doc = "1/4 full FIFO"] + pub const QUARTER: Self = Self(0); + #[doc = "1/2 full FIFO"] + pub const HALF: Self = Self(0x01); + #[doc = "3/4 full FIFO"] + pub const THREEQUARTERS: Self = Self(0x02); + #[doc = "Full FIFO"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Fs(pub u8); + impl Fs { + #[doc = "0 < fifo_level < 1/4"] + pub const QUARTER1: Self = Self(0); + #[doc = "1/4 <= fifo_level < 1/2"] + pub const QUARTER2: Self = Self(0x01); + #[doc = "1/2 <= fifo_level < 3/4"] + pub const QUARTER3: Self = Self(0x02); + #[doc = "3/4 <= fifo_level < full"] + pub const QUARTER4: Self = Self(0x03); + #[doc = "FIFO is empty"] + pub const EMPTY: Self = Self(0x04); + #[doc = "FIFO is full"] + pub const FULL: Self = Self(0x05); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dbm(pub u8); + impl Dbm { + #[doc = "No buffer switching at the end of transfer"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory target switched at the end of the DMA transfer"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Size(pub u8); + impl Size { + #[doc = "Byte (8-bit)"] + pub const BITS8: Self = Self(0); + #[doc = "Half-word (16-bit)"] + pub const BITS16: Self = Self(0x01); + #[doc = "Word (32-bit)"] + pub const BITS32: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dmdis(pub u8); + impl Dmdis { + #[doc = "Direct mode is enabled"] + pub const ENABLED: Self = Self(0); + #[doc = "Direct mode is disabled"] + pub const DISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pincos(pub u8); + impl Pincos { + #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] + pub const PSIZE: Self = Self(0); + #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] + pub const FIXED4: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Burst(pub u8); + impl Burst { + #[doc = "Single transfer"] + pub const SINGLE: Self = Self(0); + #[doc = "Incremental burst of 4 beats"] + pub const INCR4: Self = Self(0x01); + #[doc = "Incremental burst of 8 beats"] + pub const INCR8: Self = Self(0x02); + #[doc = "Incremental burst of 16 beats"] + pub const INCR16: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low"] + pub const LOW: Self = Self(0); + #[doc = "Medium"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high"] + pub const VERYHIGH: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Peripheral-to-memory"] + pub const PERIPHERALTOMEMORY: Self = Self(0); + #[doc = "Memory-to-peripheral"] + pub const MEMORYTOPERIPHERAL: Self = Self(0x01); + #[doc = "Memory-to-memory"] + pub const MEMORYTOMEMORY: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ct(pub u8); + impl Ct { + #[doc = "The current target memory is Memory 0"] + pub const MEMORY0: Self = Self(0); + #[doc = "The current target memory is Memory 1"] + pub const MEMORY1: Self = Self(0x01); + } + } +} +pub mod dma_v1 { + use crate::generic::*; + #[doc = "DMA controller"] + #[derive(Copy, Clone)] + pub struct Dma(pub *mut u8); + unsafe impl Send for Dma {} + unsafe impl Sync for Dma {} + impl Dma { + #[doc = "DMA interrupt status register (DMA_ISR)"] + pub fn isr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + pub fn ifcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + pub fn ch(self, n: usize) -> Ch { + assert!(n < 7usize); + unsafe { Ch(self.0.add(8usize + n * 20usize)) } + } + } + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + #[derive(Copy, Clone)] + pub struct Ch(pub *mut u8); + unsafe impl Send for Ch {} + unsafe impl Sync for Ch {} + impl Ch { + #[doc = "DMA channel configuration register (DMA_CCR)"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA channel 1 number of data register"] + pub fn ndtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA channel 1 peripheral address register"] + pub fn par(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA channel 1 memory address register"] + pub fn mar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular buffer disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular buffer enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low priority"] + pub const LOW: Self = Self(0); + #[doc = "Medium priority"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High priority"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high priority"] + pub const VERYHIGH: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Inc(pub u8); + impl Inc { + #[doc = "Increment mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Increment mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Memmem(pub u8); + impl Memmem { + #[doc = "Memory to memory mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory to memory mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Read from peripheral"] + pub const FROMPERIPHERAL: Self = Self(0); + #[doc = "Read from memory"] + pub const FROMMEMORY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Size(pub u8); + impl Size { + #[doc = "8-bit size"] + pub const BITS8: Self = Self(0); + #[doc = "16-bit size"] + pub const BITS16: Self = Self(0x01); + #[doc = "32-bit size"] + pub const BITS32: Self = Self(0x02); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ifcr(pub u32); + impl Ifcr { + #[doc = "Channel 1 Global interrupt clear"] + pub fn cgif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Global interrupt clear"] + pub fn set_cgif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Complete clear"] + pub fn ctcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Complete clear"] + pub fn set_ctcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer clear"] + pub fn chtif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer clear"] + pub fn set_chtif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn cteif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn set_cteif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Ifcr { + fn default() -> Ifcr { + Ifcr(0) + } + } + #[doc = "DMA channel configuration register (DMA_CCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Channel enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Channel enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transfer complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transfer complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Half Transfer interrupt enable"] + pub const fn htie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Half Transfer interrupt enable"] + pub fn set_htie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transfer error interrupt enable"] + pub const fn teie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transfer error interrupt enable"] + pub fn set_teie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Data transfer direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Data transfer direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Circular mode"] + pub const fn circ(&self) -> super::vals::Circ { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Circ(val as u8) + } + #[doc = "Circular mode"] + pub fn set_circ(&mut self, val: super::vals::Circ) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "Peripheral increment mode"] + pub const fn pinc(&self) -> super::vals::Inc { + let val = (self.0 >> 6usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Peripheral increment mode"] + pub fn set_pinc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize); + } + #[doc = "Memory increment mode"] + pub const fn minc(&self) -> super::vals::Inc { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Memory increment mode"] + pub fn set_minc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Peripheral size"] + pub const fn psize(&self) -> super::vals::Size { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Peripheral size"] + pub fn set_psize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + #[doc = "Memory size"] + pub const fn msize(&self) -> super::vals::Size { + let val = (self.0 >> 10usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Memory size"] + pub fn set_msize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize); + } + #[doc = "Channel Priority level"] + pub const fn pl(&self) -> super::vals::Pl { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Pl(val as u8) + } + #[doc = "Channel Priority level"] + pub fn set_pl(&mut self, val: super::vals::Pl) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "Memory to memory mode"] + pub const fn mem2mem(&self) -> super::vals::Memmem { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Memmem(val as u8) + } + #[doc = "Memory to memory mode"] + pub fn set_mem2mem(&mut self, val: super::vals::Memmem) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "DMA channel 1 number of data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ndtr(pub u32); + impl Ndtr { + #[doc = "Number of data to transfer"] + pub const fn ndt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Number of data to transfer"] + pub fn set_ndt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ndtr { + fn default() -> Ndtr { + Ndtr(0) + } + } + #[doc = "DMA interrupt status register (DMA_ISR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Isr(pub u32); + impl Isr { + #[doc = "Channel 1 Global interrupt flag"] + pub fn gif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Global interrupt flag"] + pub fn set_gif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Complete flag"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Complete flag"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Isr { + fn default() -> Isr { + Isr(0) + } + } + } +} +pub mod rng_v1 { + use crate::generic::*; + #[doc = "Random number generator"] + #[derive(Copy, Clone)] + pub struct Rng(pub *mut u8); + unsafe impl Send for Rng {} + unsafe impl Sync for Rng {} + impl Rng { + #[doc = "control register"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Data ready"] + pub const fn drdy(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Data ready"] + pub fn set_drdy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Clock error current status"] + pub const fn cecs(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Clock error current status"] + pub fn set_cecs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Seed error current status"] + pub const fn secs(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Seed error current status"] + pub fn set_secs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Clock error interrupt status"] + pub const fn ceis(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Clock error interrupt status"] + pub fn set_ceis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Seed error interrupt status"] + pub const fn seis(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Seed error interrupt status"] + pub fn set_seis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Random number generator enable"] + pub const fn rngen(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Random number generator enable"] + pub fn set_rngen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Interrupt enable"] + pub const fn ie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Interrupt enable"] + pub fn set_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + } +} +pub mod exti_v1 { + use crate::generic::*; + #[doc = "External interrupt/event controller"] + #[derive(Copy, Clone)] + pub struct Exti(pub *mut u8); + unsafe impl Send for Exti {} + unsafe impl Sync for Exti {} + impl Exti { + #[doc = "Interrupt mask register (EXTI_IMR)"] + pub fn imr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Event mask register (EXTI_EMR)"] + pub fn emr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Rising Trigger selection register (EXTI_RTSR)"] + pub fn rtsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Falling Trigger selection register (EXTI_FTSR)"] + pub fn ftsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Software interrupt event register (EXTI_SWIER)"] + pub fn swier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Pending register (EXTI_PR)"] + pub fn pr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Software interrupt event register (EXTI_SWIER)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Swier(pub u32); + impl Swier { + #[doc = "Software Interrupt on line 0"] + pub fn swier(&self, n: usize) -> bool { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Software Interrupt on line 0"] + pub fn set_swier(&mut self, n: usize, val: bool) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Swier { + fn default() -> Swier { + Swier(0) + } + } + #[doc = "Pending register (EXTI_PR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pr(pub u32); + impl Pr { + #[doc = "Pending bit 0"] + pub fn pr(&self, n: usize) -> bool { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Pending bit 0"] + pub fn set_pr(&mut self, n: usize, val: bool) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Pr { + fn default() -> Pr { + Pr(0) + } + } + #[doc = "Falling Trigger selection register (EXTI_FTSR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ftsr(pub u32); + impl Ftsr { + #[doc = "Falling trigger event configuration of line 0"] + pub fn tr(&self, n: usize) -> super::vals::Tr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Tr(val as u8) + } + #[doc = "Falling trigger event configuration of line 0"] + pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Ftsr { + fn default() -> Ftsr { + Ftsr(0) + } + } + #[doc = "Event mask register (EXTI_EMR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Emr(pub u32); + impl Emr { + #[doc = "Event Mask on line 0"] + pub fn mr(&self, n: usize) -> super::vals::Mr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Mr(val as u8) + } + #[doc = "Event Mask on line 0"] + pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Emr { + fn default() -> Emr { + Emr(0) + } + } + #[doc = "Interrupt mask register (EXTI_IMR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Imr(pub u32); + impl Imr { + #[doc = "Interrupt Mask on line 0"] + pub fn mr(&self, n: usize) -> super::vals::Mr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Mr(val as u8) + } + #[doc = "Interrupt Mask on line 0"] + pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Imr { + fn default() -> Imr { + Imr(0) + } + } + #[doc = "Rising Trigger selection register (EXTI_RTSR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rtsr(pub u32); + impl Rtsr { + #[doc = "Rising trigger event configuration of line 0"] + pub fn tr(&self, n: usize) -> super::vals::Tr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Tr(val as u8) + } + #[doc = "Rising trigger event configuration of line 0"] + pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Rtsr { + fn default() -> Rtsr { + Rtsr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Prw(pub u8); + impl Prw { + #[doc = "Clears pending bit"] + pub const CLEAR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Swierw(pub u8); + impl Swierw { + #[doc = "Generates an interrupt request"] + pub const PEND: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mr(pub u8); + impl Mr { + #[doc = "Interrupt request line is masked"] + pub const MASKED: Self = Self(0); + #[doc = "Interrupt request line is unmasked"] + pub const UNMASKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Prr(pub u8); + impl Prr { + #[doc = "No trigger request occurred"] + pub const NOTPENDING: Self = Self(0); + #[doc = "Selected trigger request occurred"] + pub const PENDING: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Tr(pub u8); + impl Tr { + #[doc = "Falling edge trigger is disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Falling edge trigger is enabled"] + pub const ENABLED: Self = Self(0x01); + } + } +} +pub mod syscfg_l4 { + use crate::generic::*; + #[doc = "System configuration controller"] + #[derive(Copy, Clone)] + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "memory remap register"] + pub fn memrmp(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "configuration register 1"] + pub fn cfgr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "external interrupt configuration register 1"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "SCSR"] + pub fn scsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "CFGR2"] + pub fn cfgr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "SWPR"] + pub fn swpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "SKR"] + pub fn skr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "CFGR2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cfgr2(pub u32); + impl Cfgr2 { + #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] + pub const fn cll(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] + pub fn set_cll(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 parity lock bit"] + pub const fn spl(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity lock bit"] + pub fn set_spl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "PVD lock enable bit"] + pub const fn pvdl(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "PVD lock enable bit"] + pub fn set_pvdl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "ECC Lock"] + pub const fn eccl(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "ECC Lock"] + pub fn set_eccl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "SRAM2 parity error flag"] + pub const fn spf(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity error flag"] + pub fn set_spf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Cfgr2 { + fn default() -> Cfgr2 { + Cfgr2(0) + } + } + #[doc = "memory remap register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Memrmp(pub u32); + impl Memrmp { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "QUADSPI memory mapping swap"] + pub const fn qfs(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "QUADSPI memory mapping swap"] + pub fn set_qfs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Flash Bank mode selection"] + pub const fn fb_mode(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Flash Bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Memrmp { + fn default() -> Memrmp { + Memrmp(0) + } + } + #[doc = "SCSR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Scsr(pub u32); + impl Scsr { + #[doc = "SRAM2 Erase"] + pub const fn sram2er(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 Erase"] + pub fn set_sram2er(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 busy by erase operation"] + pub const fn sram2bsy(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 busy by erase operation"] + pub fn set_sram2bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + } + impl Default for Scsr { + fn default() -> Scsr { + Scsr(0) + } + } + #[doc = "external interrupt configuration register 4"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI12 configuration bits"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI12 configuration bits"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "configuration register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cfgr1(pub u32); + impl Cfgr1 { + #[doc = "Firewall disable"] + pub const fn fwdis(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Firewall disable"] + pub fn set_fwdis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "I/O analog switch voltage booster enable"] + pub const fn boosten(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "I/O analog switch voltage booster enable"] + pub fn set_boosten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] + pub const fn i2c_pb6_fmp(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] + pub fn set_i2c_pb6_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] + pub const fn i2c_pb7_fmp(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] + pub fn set_i2c_pb7_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] + pub const fn i2c_pb8_fmp(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] + pub fn set_i2c_pb8_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] + pub const fn i2c_pb9_fmp(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] + pub fn set_i2c_pb9_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "I2C1 Fast-mode Plus driving capability activation"] + pub const fn i2c1_fmp(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "I2C1 Fast-mode Plus driving capability activation"] + pub fn set_i2c1_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "I2C2 Fast-mode Plus driving capability activation"] + pub const fn i2c2_fmp(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "I2C2 Fast-mode Plus driving capability activation"] + pub fn set_i2c2_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "I2C3 Fast-mode Plus driving capability activation"] + pub const fn i2c3_fmp(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "I2C3 Fast-mode Plus driving capability activation"] + pub fn set_i2c3_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Floating Point Unit interrupts enable bits"] + pub const fn fpu_ie(&self) -> u8 { + let val = (self.0 >> 26usize) & 0x3f; + val as u8 + } + #[doc = "Floating Point Unit interrupts enable bits"] + pub fn set_fpu_ie(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize); + } + } + impl Default for Cfgr1 { + fn default() -> Cfgr1 { + Cfgr1(0) + } + } + #[doc = "SWPR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Swpr(pub u32); + impl Swpr { + #[doc = "SRAWM2 write protection."] + pub fn pwp(&self, n: usize) -> bool { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "SRAWM2 write protection."] + pub fn set_pwp(&mut self, n: usize, val: bool) { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Swpr { + fn default() -> Swpr { + Swpr(0) + } + } + #[doc = "SKR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Skr(pub u32); + impl Skr { + #[doc = "SRAM2 write protection key for software erase"] + pub const fn key(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "SRAM2 write protection key for software erase"] + pub fn set_key(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Skr { + fn default() -> Skr { + Skr(0) + } + } + } +} +pub mod usart_v1 { + use crate::generic::*; + #[doc = "Universal asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Uart(pub *mut u8); + unsafe impl Send for Uart {} + unsafe impl Sync for Uart {} + impl Uart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + #[doc = "Universal synchronous asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Usart(pub *mut u8); + unsafe impl Send for Usart {} + unsafe impl Sync for Usart {} + impl Usart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Guard time and prescaler register"] + pub fn gtpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrUsart(pub u32); + impl SrUsart { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS flag"] + pub const fn cts(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS flag"] + pub fn set_cts(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + } + impl Default for SrUsart { + fn default() -> SrUsart { + SrUsart(0) + } + } + #[doc = "Baud rate register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "fraction of USARTDIV"] + pub const fn div_fraction(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "fraction of USARTDIV"] + pub fn set_div_fraction(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "mantissa of USARTDIV"] + pub const fn div_mantissa(&self) -> u16 { + let val = (self.0 >> 4usize) & 0x0fff; + val as u16 + } + #[doc = "mantissa of USARTDIV"] + pub fn set_div_mantissa(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "Control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Send break"] + pub const fn sbk(&self) -> super::vals::Sbk { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Sbk(val as u8) + } + #[doc = "Send break"] + pub fn set_sbk(&mut self, val: super::vals::Sbk) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Receiver wakeup"] + pub const fn rwu(&self) -> super::vals::Rwu { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Rwu(val as u8) + } + #[doc = "Receiver wakeup"] + pub fn set_rwu(&mut self, val: super::vals::Rwu) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Receiver enable"] + pub const fn re(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receiver enable"] + pub fn set_re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transmitter enable"] + pub const fn te(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transmitter enable"] + pub fn set_te(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE interrupt enable"] + pub const fn idleie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE interrupt enable"] + pub fn set_idleie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXNE interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXNE interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "TXE interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "TXE interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "PE interrupt enable"] + pub const fn peie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "PE interrupt enable"] + pub fn set_peie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Parity selection"] + pub const fn ps(&self) -> super::vals::Ps { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Ps(val as u8) + } + #[doc = "Parity selection"] + pub fn set_ps(&mut self, val: super::vals::Ps) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Parity control enable"] + pub const fn pce(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Parity control enable"] + pub fn set_pce(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Wakeup method"] + pub const fn wake(&self) -> super::vals::Wake { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Wake(val as u8) + } + #[doc = "Wakeup method"] + pub fn set_wake(&mut self, val: super::vals::Wake) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Word length"] + pub const fn m(&self) -> super::vals::M { + let val = (self.0 >> 12usize) & 0x01; + super::vals::M(val as u8) + } + #[doc = "Word length"] + pub fn set_m(&mut self, val: super::vals::M) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "USART enable"] + pub const fn ue(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "USART enable"] + pub fn set_ue(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3Usart(pub u32); + impl Cr3Usart { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Smartcard NACK enable"] + pub const fn nack(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Smartcard NACK enable"] + pub fn set_nack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Smartcard mode enable"] + pub const fn scen(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Smartcard mode enable"] + pub fn set_scen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "RTS enable"] + pub const fn rtse(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "RTS enable"] + pub fn set_rtse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS enable"] + pub const fn ctse(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS enable"] + pub fn set_ctse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "CTS interrupt enable"] + pub const fn ctsie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CTS interrupt enable"] + pub fn set_ctsie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + } + impl Default for Cr3Usart { + fn default() -> Cr3Usart { + Cr3Usart(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Usart(pub u32); + impl Cr2Usart { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Last bit clock pulse"] + pub const fn lbcl(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Last bit clock pulse"] + pub fn set_lbcl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Clock enable"] + pub const fn clken(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Clock enable"] + pub fn set_clken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2Usart { + fn default() -> Cr2Usart { + Cr2Usart(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3(pub u32); + impl Cr3 { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Cr3 { + fn default() -> Cr3 { + Cr3(0) + } + } + #[doc = "Guard time and prescaler register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Gtpr(pub u32); + impl Gtpr { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Guard time value"] + pub const fn gt(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "Guard time value"] + pub fn set_gt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } + } + impl Default for Gtpr { + fn default() -> Gtpr { + Gtpr(0) + } + } + #[doc = "Data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data value"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x01ff; + val as u16 + } + #[doc = "Data value"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "Steady low value on CK pin outside transmission window"] + pub const LOW: Self = Self(0); + #[doc = "Steady high value on CK pin outside transmission window"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Stop(pub u8); + impl Stop { + #[doc = "1 stop bit"] + pub const STOP1: Self = Self(0); + #[doc = "0.5 stop bits"] + pub const STOP0P5: Self = Self(0x01); + #[doc = "2 stop bits"] + pub const STOP2: Self = Self(0x02); + #[doc = "1.5 stop bits"] + pub const STOP1P5: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rwu(pub u8); + impl Rwu { + #[doc = "Receiver in active mode"] + pub const ACTIVE: Self = Self(0); + #[doc = "Receiver in mute mode"] + pub const MUTE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sbk(pub u8); + impl Sbk { + #[doc = "No break character is transmitted"] + pub const NOBREAK: Self = Self(0); + #[doc = "Break character transmitted"] + pub const BREAK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct M(pub u8); + impl M { + #[doc = "8 data bits"] + pub const M8: Self = Self(0); + #[doc = "9 data bits"] + pub const M9: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lbdl(pub u8); + impl Lbdl { + #[doc = "10-bit break detection"] + pub const LBDL10: Self = Self(0); + #[doc = "11-bit break detection"] + pub const LBDL11: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRST: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECOND: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Hdsel(pub u8); + impl Hdsel { + #[doc = "Half duplex mode is not selected"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Half duplex mode is selected"] + pub const HALFDUPLEX: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Wake(pub u8); + impl Wake { + #[doc = "USART wakeup on idle line"] + pub const IDLELINE: Self = Self(0); + #[doc = "USART wakeup on address mark"] + pub const ADDRESSMARK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Irlp(pub u8); + impl Irlp { + #[doc = "Normal mode"] + pub const NORMAL: Self = Self(0); + #[doc = "Low-power mode"] + pub const LOWPOWER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ps(pub u8); + impl Ps { + #[doc = "Even parity"] + pub const EVEN: Self = Self(0); + #[doc = "Odd parity"] + pub const ODD: Self = Self(0x01); + } + } +} diff --git a/embassy-stm32/src/pac/stm32f401cb.rs b/embassy-stm32/src/pac/stm32f401cb.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401cb.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401cc.rs b/embassy-stm32/src/pac/stm32f401cc.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401cc.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401cd.rs b/embassy-stm32/src/pac/stm32f401cd.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401cd.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401ce.rs b/embassy-stm32/src/pac/stm32f401ce.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401ce.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401rb.rs b/embassy-stm32/src/pac/stm32f401rb.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401rb.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401rc.rs b/embassy-stm32/src/pac/stm32f401rc.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401rc.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401rd.rs b/embassy-stm32/src/pac/stm32f401rd.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401rd.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401re.rs b/embassy-stm32/src/pac/stm32f401re.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401re.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401vb.rs b/embassy-stm32/src/pac/stm32f401vb.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401vb.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401vc.rs b/embassy-stm32/src/pac/stm32f401vc.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401vc.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401vd.rs b/embassy-stm32/src/pac/stm32f401vd.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401vd.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401ve.rs b/embassy-stm32/src/pac/stm32f401ve.rs new file mode 100644 index 000000000..c243b7b21 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401ve.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f405oe.rs b/embassy-stm32/src/pac/stm32f405oe.rs new file mode 100644 index 000000000..55def9b77 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f405oe.rs @@ -0,0 +1,637 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f405og.rs b/embassy-stm32/src/pac/stm32f405og.rs new file mode 100644 index 000000000..55def9b77 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f405og.rs @@ -0,0 +1,637 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f405rg.rs b/embassy-stm32/src/pac/stm32f405rg.rs new file mode 100644 index 000000000..55def9b77 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f405rg.rs @@ -0,0 +1,637 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f405vg.rs b/embassy-stm32/src/pac/stm32f405vg.rs new file mode 100644 index 000000000..55def9b77 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f405vg.rs @@ -0,0 +1,637 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f405zg.rs b/embassy-stm32/src/pac/stm32f405zg.rs new file mode 100644 index 000000000..55def9b77 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f405zg.rs @@ -0,0 +1,637 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407ie.rs b/embassy-stm32/src/pac/stm32f407ie.rs new file mode 100644 index 000000000..d54d54fe8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407ie.rs @@ -0,0 +1,646 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407ig.rs b/embassy-stm32/src/pac/stm32f407ig.rs new file mode 100644 index 000000000..d54d54fe8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407ig.rs @@ -0,0 +1,646 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407ve.rs b/embassy-stm32/src/pac/stm32f407ve.rs new file mode 100644 index 000000000..d54d54fe8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407ve.rs @@ -0,0 +1,646 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407vg.rs b/embassy-stm32/src/pac/stm32f407vg.rs new file mode 100644 index 000000000..d54d54fe8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407vg.rs @@ -0,0 +1,646 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407ze.rs b/embassy-stm32/src/pac/stm32f407ze.rs new file mode 100644 index 000000000..d54d54fe8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407ze.rs @@ -0,0 +1,646 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407zg.rs b/embassy-stm32/src/pac/stm32f407zg.rs new file mode 100644 index 000000000..d54d54fe8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407zg.rs @@ -0,0 +1,646 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410c8.rs b/embassy-stm32/src/pac/stm32f410c8.rs new file mode 100644 index 000000000..c5eb48a7f --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410c8.rs @@ -0,0 +1,450 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410cb.rs b/embassy-stm32/src/pac/stm32f410cb.rs new file mode 100644 index 000000000..c5eb48a7f --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410cb.rs @@ -0,0 +1,450 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410r8.rs b/embassy-stm32/src/pac/stm32f410r8.rs new file mode 100644 index 000000000..c5eb48a7f --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410r8.rs @@ -0,0 +1,450 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410rb.rs b/embassy-stm32/src/pac/stm32f410rb.rs new file mode 100644 index 000000000..c5eb48a7f --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410rb.rs @@ -0,0 +1,450 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410t8.rs b/embassy-stm32/src/pac/stm32f410t8.rs new file mode 100644 index 000000000..1eb28b9fc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410t8.rs @@ -0,0 +1,434 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410tb.rs b/embassy-stm32/src/pac/stm32f410tb.rs new file mode 100644 index 000000000..1eb28b9fc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410tb.rs @@ -0,0 +1,434 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411cc.rs b/embassy-stm32/src/pac/stm32f411cc.rs new file mode 100644 index 000000000..c747fc063 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411cc.rs @@ -0,0 +1,491 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411ce.rs b/embassy-stm32/src/pac/stm32f411ce.rs new file mode 100644 index 000000000..c747fc063 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411ce.rs @@ -0,0 +1,491 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411rc.rs b/embassy-stm32/src/pac/stm32f411rc.rs new file mode 100644 index 000000000..c747fc063 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411rc.rs @@ -0,0 +1,491 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411re.rs b/embassy-stm32/src/pac/stm32f411re.rs new file mode 100644 index 000000000..c747fc063 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411re.rs @@ -0,0 +1,491 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411vc.rs b/embassy-stm32/src/pac/stm32f411vc.rs new file mode 100644 index 000000000..c747fc063 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411vc.rs @@ -0,0 +1,491 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411ve.rs b/embassy-stm32/src/pac/stm32f411ve.rs new file mode 100644 index 000000000..c747fc063 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411ve.rs @@ -0,0 +1,491 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, + USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412ce.rs b/embassy-stm32/src/pac/stm32f412ce.rs new file mode 100644 index 000000000..0684b55da --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412ce.rs @@ -0,0 +1,549 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412cg.rs b/embassy-stm32/src/pac/stm32f412cg.rs new file mode 100644 index 000000000..0684b55da --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412cg.rs @@ -0,0 +1,549 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412re.rs b/embassy-stm32/src/pac/stm32f412re.rs new file mode 100644 index 000000000..1c1d5221d --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412re.rs @@ -0,0 +1,580 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412rg.rs b/embassy-stm32/src/pac/stm32f412rg.rs new file mode 100644 index 000000000..1c1d5221d --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412rg.rs @@ -0,0 +1,580 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412ve.rs b/embassy-stm32/src/pac/stm32f412ve.rs new file mode 100644 index 000000000..b45a90fad --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412ve.rs @@ -0,0 +1,641 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412vg.rs b/embassy-stm32/src/pac/stm32f412vg.rs new file mode 100644 index 000000000..b45a90fad --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412vg.rs @@ -0,0 +1,641 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412ze.rs b/embassy-stm32/src/pac/stm32f412ze.rs new file mode 100644 index 000000000..b45a90fad --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412ze.rs @@ -0,0 +1,641 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412zg.rs b/embassy-stm32/src/pac/stm32f412zg.rs new file mode 100644 index 000000000..b45a90fad --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412zg.rs @@ -0,0 +1,641 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413cg.rs b/embassy-stm32/src/pac/stm32f413cg.rs new file mode 100644 index 000000000..3ac805c97 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413cg.rs @@ -0,0 +1,686 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413ch.rs b/embassy-stm32/src/pac/stm32f413ch.rs new file mode 100644 index 000000000..3ac805c97 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413ch.rs @@ -0,0 +1,686 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413mg.rs b/embassy-stm32/src/pac/stm32f413mg.rs new file mode 100644 index 000000000..d841d79f5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413mg.rs @@ -0,0 +1,702 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413mh.rs b/embassy-stm32/src/pac/stm32f413mh.rs new file mode 100644 index 000000000..d841d79f5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413mh.rs @@ -0,0 +1,702 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413rg.rs b/embassy-stm32/src/pac/stm32f413rg.rs new file mode 100644 index 000000000..d841d79f5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413rg.rs @@ -0,0 +1,702 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413rh.rs b/embassy-stm32/src/pac/stm32f413rh.rs new file mode 100644 index 000000000..d841d79f5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413rh.rs @@ -0,0 +1,702 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413vg.rs b/embassy-stm32/src/pac/stm32f413vg.rs new file mode 100644 index 000000000..d841d79f5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413vg.rs @@ -0,0 +1,702 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413vh.rs b/embassy-stm32/src/pac/stm32f413vh.rs new file mode 100644 index 000000000..d841d79f5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413vh.rs @@ -0,0 +1,702 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413zg.rs b/embassy-stm32/src/pac/stm32f413zg.rs new file mode 100644 index 000000000..d841d79f5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413zg.rs @@ -0,0 +1,702 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413zh.rs b/embassy-stm32/src/pac/stm32f413zh.rs new file mode 100644 index 000000000..d841d79f5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413zh.rs @@ -0,0 +1,702 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f415og.rs b/embassy-stm32/src/pac/stm32f415og.rs new file mode 100644 index 000000000..df71f8770 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f415og.rs @@ -0,0 +1,640 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f415rg.rs b/embassy-stm32/src/pac/stm32f415rg.rs new file mode 100644 index 000000000..df71f8770 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f415rg.rs @@ -0,0 +1,640 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f415vg.rs b/embassy-stm32/src/pac/stm32f415vg.rs new file mode 100644 index 000000000..df71f8770 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f415vg.rs @@ -0,0 +1,640 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f415zg.rs b/embassy-stm32/src/pac/stm32f415zg.rs new file mode 100644 index 000000000..df71f8770 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f415zg.rs @@ -0,0 +1,640 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417ie.rs b/embassy-stm32/src/pac/stm32f417ie.rs new file mode 100644 index 000000000..2e802e9e9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417ie.rs @@ -0,0 +1,649 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417ig.rs b/embassy-stm32/src/pac/stm32f417ig.rs new file mode 100644 index 000000000..2e802e9e9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417ig.rs @@ -0,0 +1,649 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417ve.rs b/embassy-stm32/src/pac/stm32f417ve.rs new file mode 100644 index 000000000..2e802e9e9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417ve.rs @@ -0,0 +1,649 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417vg.rs b/embassy-stm32/src/pac/stm32f417vg.rs new file mode 100644 index 000000000..2e802e9e9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417vg.rs @@ -0,0 +1,649 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417ze.rs b/embassy-stm32/src/pac/stm32f417ze.rs new file mode 100644 index 000000000..2e802e9e9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417ze.rs @@ -0,0 +1,649 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417zg.rs b/embassy-stm32/src/pac/stm32f417zg.rs new file mode 100644 index 000000000..2e802e9e9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417zg.rs @@ -0,0 +1,649 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f423ch.rs b/embassy-stm32/src/pac/stm32f423ch.rs new file mode 100644 index 000000000..3dd033251 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f423ch.rs @@ -0,0 +1,689 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f423mh.rs b/embassy-stm32/src/pac/stm32f423mh.rs new file mode 100644 index 000000000..0e844e7db --- /dev/null +++ b/embassy-stm32/src/pac/stm32f423mh.rs @@ -0,0 +1,705 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f423rh.rs b/embassy-stm32/src/pac/stm32f423rh.rs new file mode 100644 index 000000000..0e844e7db --- /dev/null +++ b/embassy-stm32/src/pac/stm32f423rh.rs @@ -0,0 +1,705 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f423vh.rs b/embassy-stm32/src/pac/stm32f423vh.rs new file mode 100644 index 000000000..0e844e7db --- /dev/null +++ b/embassy-stm32/src/pac/stm32f423vh.rs @@ -0,0 +1,705 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f423zh.rs b/embassy-stm32/src/pac/stm32f423zh.rs new file mode 100644 index 000000000..0e844e7db --- /dev/null +++ b/embassy-stm32/src/pac/stm32f423zh.rs @@ -0,0 +1,705 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427ag.rs b/embassy-stm32/src/pac/stm32f427ag.rs new file mode 100644 index 000000000..36a117c12 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427ag.rs @@ -0,0 +1,711 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427ai.rs b/embassy-stm32/src/pac/stm32f427ai.rs new file mode 100644 index 000000000..36a117c12 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427ai.rs @@ -0,0 +1,711 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427ig.rs b/embassy-stm32/src/pac/stm32f427ig.rs new file mode 100644 index 000000000..36a117c12 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427ig.rs @@ -0,0 +1,711 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427ii.rs b/embassy-stm32/src/pac/stm32f427ii.rs new file mode 100644 index 000000000..36a117c12 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427ii.rs @@ -0,0 +1,711 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427vg.rs b/embassy-stm32/src/pac/stm32f427vg.rs new file mode 100644 index 000000000..36a117c12 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427vg.rs @@ -0,0 +1,711 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427vi.rs b/embassy-stm32/src/pac/stm32f427vi.rs new file mode 100644 index 000000000..36a117c12 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427vi.rs @@ -0,0 +1,711 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427zg.rs b/embassy-stm32/src/pac/stm32f427zg.rs new file mode 100644 index 000000000..36a117c12 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427zg.rs @@ -0,0 +1,711 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427zi.rs b/embassy-stm32/src/pac/stm32f427zi.rs new file mode 100644 index 000000000..36a117c12 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427zi.rs @@ -0,0 +1,711 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ag.rs b/embassy-stm32/src/pac/stm32f429ag.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ag.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ai.rs b/embassy-stm32/src/pac/stm32f429ai.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ai.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429be.rs b/embassy-stm32/src/pac/stm32f429be.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429be.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429bg.rs b/embassy-stm32/src/pac/stm32f429bg.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429bg.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429bi.rs b/embassy-stm32/src/pac/stm32f429bi.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429bi.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ie.rs b/embassy-stm32/src/pac/stm32f429ie.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ie.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ig.rs b/embassy-stm32/src/pac/stm32f429ig.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ig.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ii.rs b/embassy-stm32/src/pac/stm32f429ii.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ii.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ne.rs b/embassy-stm32/src/pac/stm32f429ne.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ne.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ng.rs b/embassy-stm32/src/pac/stm32f429ng.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ng.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ni.rs b/embassy-stm32/src/pac/stm32f429ni.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ni.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ve.rs b/embassy-stm32/src/pac/stm32f429ve.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ve.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429vg.rs b/embassy-stm32/src/pac/stm32f429vg.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429vg.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429vi.rs b/embassy-stm32/src/pac/stm32f429vi.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429vi.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ze.rs b/embassy-stm32/src/pac/stm32f429ze.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ze.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429zg.rs b/embassy-stm32/src/pac/stm32f429zg.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429zg.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429zi.rs b/embassy-stm32/src/pac/stm32f429zi.rs new file mode 100644 index 000000000..2e314d2f3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429zi.rs @@ -0,0 +1,717 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437ai.rs b/embassy-stm32/src/pac/stm32f437ai.rs new file mode 100644 index 000000000..a0f5e14ea --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437ai.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437ig.rs b/embassy-stm32/src/pac/stm32f437ig.rs new file mode 100644 index 000000000..a0f5e14ea --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437ig.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437ii.rs b/embassy-stm32/src/pac/stm32f437ii.rs new file mode 100644 index 000000000..a0f5e14ea --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437ii.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437vg.rs b/embassy-stm32/src/pac/stm32f437vg.rs new file mode 100644 index 000000000..a0f5e14ea --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437vg.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437vi.rs b/embassy-stm32/src/pac/stm32f437vi.rs new file mode 100644 index 000000000..a0f5e14ea --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437vi.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437zg.rs b/embassy-stm32/src/pac/stm32f437zg.rs new file mode 100644 index 000000000..a0f5e14ea --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437zg.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437zi.rs b/embassy-stm32/src/pac/stm32f437zi.rs new file mode 100644 index 000000000..a0f5e14ea --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437zi.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439ai.rs b/embassy-stm32/src/pac/stm32f439ai.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439ai.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439bg.rs b/embassy-stm32/src/pac/stm32f439bg.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439bg.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439bi.rs b/embassy-stm32/src/pac/stm32f439bi.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439bi.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439ig.rs b/embassy-stm32/src/pac/stm32f439ig.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439ig.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439ii.rs b/embassy-stm32/src/pac/stm32f439ii.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439ii.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439ng.rs b/embassy-stm32/src/pac/stm32f439ng.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439ng.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439ni.rs b/embassy-stm32/src/pac/stm32f439ni.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439ni.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439vg.rs b/embassy-stm32/src/pac/stm32f439vg.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439vg.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439vi.rs b/embassy-stm32/src/pac/stm32f439vi.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439vi.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439zg.rs b/embassy-stm32/src/pac/stm32f439zg.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439zg.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439zi.rs b/embassy-stm32/src/pac/stm32f439zi.rs new file mode 100644 index 000000000..80e31cb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439zi.rs @@ -0,0 +1,720 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446mc.rs b/embassy-stm32/src/pac/stm32f446mc.rs new file mode 100644 index 000000000..00a5175d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446mc.rs @@ -0,0 +1,660 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446me.rs b/embassy-stm32/src/pac/stm32f446me.rs new file mode 100644 index 000000000..00a5175d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446me.rs @@ -0,0 +1,660 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446rc.rs b/embassy-stm32/src/pac/stm32f446rc.rs new file mode 100644 index 000000000..00a5175d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446rc.rs @@ -0,0 +1,660 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446re.rs b/embassy-stm32/src/pac/stm32f446re.rs new file mode 100644 index 000000000..00a5175d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446re.rs @@ -0,0 +1,660 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446vc.rs b/embassy-stm32/src/pac/stm32f446vc.rs new file mode 100644 index 000000000..00a5175d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446vc.rs @@ -0,0 +1,660 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446ve.rs b/embassy-stm32/src/pac/stm32f446ve.rs new file mode 100644 index 000000000..00a5175d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446ve.rs @@ -0,0 +1,660 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446zc.rs b/embassy-stm32/src/pac/stm32f446zc.rs new file mode 100644 index 000000000..00a5175d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446zc.rs @@ -0,0 +1,660 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446ze.rs b/embassy-stm32/src/pac/stm32f446ze.rs new file mode 100644 index 000000000..00a5175d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446ze.rs @@ -0,0 +1,660 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ae.rs b/embassy-stm32/src/pac/stm32f469ae.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ae.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ag.rs b/embassy-stm32/src/pac/stm32f469ag.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ag.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ai.rs b/embassy-stm32/src/pac/stm32f469ai.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ai.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469be.rs b/embassy-stm32/src/pac/stm32f469be.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469be.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469bg.rs b/embassy-stm32/src/pac/stm32f469bg.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469bg.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469bi.rs b/embassy-stm32/src/pac/stm32f469bi.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469bi.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ie.rs b/embassy-stm32/src/pac/stm32f469ie.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ie.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ig.rs b/embassy-stm32/src/pac/stm32f469ig.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ig.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ii.rs b/embassy-stm32/src/pac/stm32f469ii.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ii.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ne.rs b/embassy-stm32/src/pac/stm32f469ne.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ne.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ng.rs b/embassy-stm32/src/pac/stm32f469ng.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ng.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ni.rs b/embassy-stm32/src/pac/stm32f469ni.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ni.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ve.rs b/embassy-stm32/src/pac/stm32f469ve.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ve.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469vg.rs b/embassy-stm32/src/pac/stm32f469vg.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469vg.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469vi.rs b/embassy-stm32/src/pac/stm32f469vi.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469vi.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ze.rs b/embassy-stm32/src/pac/stm32f469ze.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ze.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469zg.rs b/embassy-stm32/src/pac/stm32f469zg.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469zg.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469zi.rs b/embassy-stm32/src/pac/stm32f469zi.rs new file mode 100644 index 000000000..77d327564 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469zi.rs @@ -0,0 +1,725 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ag.rs b/embassy-stm32/src/pac/stm32f479ag.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ag.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ai.rs b/embassy-stm32/src/pac/stm32f479ai.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ai.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479bg.rs b/embassy-stm32/src/pac/stm32f479bg.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479bg.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479bi.rs b/embassy-stm32/src/pac/stm32f479bi.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479bi.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ig.rs b/embassy-stm32/src/pac/stm32f479ig.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ig.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ii.rs b/embassy-stm32/src/pac/stm32f479ii.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ii.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ng.rs b/embassy-stm32/src/pac/stm32f479ng.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ng.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ni.rs b/embassy-stm32/src/pac/stm32f479ni.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ni.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479vg.rs b/embassy-stm32/src/pac/stm32f479vg.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479vg.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479vi.rs b/embassy-stm32/src/pac/stm32f479vi.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479vi.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479zg.rs b/embassy-stm32/src/pac/stm32f479zg.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479zg.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479zi.rs b/embassy-stm32/src/pac/stm32f479zi.rs new file mode 100644 index 000000000..47f8e0ffd --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479zi.rs @@ -0,0 +1,728 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412c8.rs b/embassy-stm32/src/pac/stm32l412c8.rs new file mode 100644 index 000000000..1976a7823 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412c8.rs @@ -0,0 +1,437 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412cb.rs b/embassy-stm32/src/pac/stm32l412cb.rs new file mode 100644 index 000000000..1976a7823 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412cb.rs @@ -0,0 +1,437 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412k8.rs b/embassy-stm32/src/pac/stm32l412k8.rs new file mode 100644 index 000000000..884b1ef0e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412k8.rs @@ -0,0 +1,436 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412kb.rs b/embassy-stm32/src/pac/stm32l412kb.rs new file mode 100644 index 000000000..884b1ef0e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412kb.rs @@ -0,0 +1,436 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412r8.rs b/embassy-stm32/src/pac/stm32l412r8.rs new file mode 100644 index 000000000..1976a7823 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412r8.rs @@ -0,0 +1,437 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412rb.rs b/embassy-stm32/src/pac/stm32l412rb.rs new file mode 100644 index 000000000..1976a7823 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412rb.rs @@ -0,0 +1,437 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412t8.rs b/embassy-stm32/src/pac/stm32l412t8.rs new file mode 100644 index 000000000..884b1ef0e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412t8.rs @@ -0,0 +1,436 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412tb.rs b/embassy-stm32/src/pac/stm32l412tb.rs new file mode 100644 index 000000000..884b1ef0e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412tb.rs @@ -0,0 +1,436 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l422cb.rs b/embassy-stm32/src/pac/stm32l422cb.rs new file mode 100644 index 000000000..7b50a7139 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l422cb.rs @@ -0,0 +1,440 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l422kb.rs b/embassy-stm32/src/pac/stm32l422kb.rs new file mode 100644 index 000000000..92021a645 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l422kb.rs @@ -0,0 +1,439 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l422rb.rs b/embassy-stm32/src/pac/stm32l422rb.rs new file mode 100644 index 000000000..7b50a7139 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l422rb.rs @@ -0,0 +1,440 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l422tb.rs b/embassy-stm32/src/pac/stm32l422tb.rs new file mode 100644 index 000000000..92021a645 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l422tb.rs @@ -0,0 +1,439 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, + RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431cb.rs b/embassy-stm32/src/pac/stm32l431cb.rs new file mode 100644 index 000000000..c3951c751 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431cb.rs @@ -0,0 +1,479 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431cc.rs b/embassy-stm32/src/pac/stm32l431cc.rs new file mode 100644 index 000000000..c3951c751 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431cc.rs @@ -0,0 +1,479 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431kb.rs b/embassy-stm32/src/pac/stm32l431kb.rs new file mode 100644 index 000000000..7d974d49d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431kb.rs @@ -0,0 +1,478 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431kc.rs b/embassy-stm32/src/pac/stm32l431kc.rs new file mode 100644 index 000000000..7d974d49d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431kc.rs @@ -0,0 +1,478 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431rb.rs b/embassy-stm32/src/pac/stm32l431rb.rs new file mode 100644 index 000000000..c3951c751 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431rb.rs @@ -0,0 +1,479 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431rc.rs b/embassy-stm32/src/pac/stm32l431rc.rs new file mode 100644 index 000000000..c3951c751 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431rc.rs @@ -0,0 +1,479 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431vc.rs b/embassy-stm32/src/pac/stm32l431vc.rs new file mode 100644 index 000000000..c3951c751 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431vc.rs @@ -0,0 +1,479 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l432kb.rs b/embassy-stm32/src/pac/stm32l432kb.rs new file mode 100644 index 000000000..e0e534faa --- /dev/null +++ b/embassy-stm32/src/pac/stm32l432kb.rs @@ -0,0 +1,430 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SPI1 = 35, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SPI1); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SPI1(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l432kc.rs b/embassy-stm32/src/pac/stm32l432kc.rs new file mode 100644 index 000000000..e0e534faa --- /dev/null +++ b/embassy-stm32/src/pac/stm32l432kc.rs @@ -0,0 +1,430 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SPI1 = 35, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SPI1); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SPI1(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l433cb.rs b/embassy-stm32/src/pac/stm32l433cb.rs new file mode 100644 index 000000000..5e10d9721 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l433cb.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l433cc.rs b/embassy-stm32/src/pac/stm32l433cc.rs new file mode 100644 index 000000000..5e10d9721 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l433cc.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l433rb.rs b/embassy-stm32/src/pac/stm32l433rb.rs new file mode 100644 index 000000000..5e10d9721 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l433rb.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l433rc.rs b/embassy-stm32/src/pac/stm32l433rc.rs new file mode 100644 index 000000000..5e10d9721 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l433rc.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l433vc.rs b/embassy-stm32/src/pac/stm32l433vc.rs new file mode 100644 index 000000000..5e10d9721 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l433vc.rs @@ -0,0 +1,485 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l442kc.rs b/embassy-stm32/src/pac/stm32l442kc.rs new file mode 100644 index 000000000..2f1bead4c --- /dev/null +++ b/embassy-stm32/src/pac/stm32l442kc.rs @@ -0,0 +1,433 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, + EXTI, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SPI1 = 35, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SPI1); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SPI1(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l443cc.rs b/embassy-stm32/src/pac/stm32l443cc.rs new file mode 100644 index 000000000..e1860a9de --- /dev/null +++ b/embassy-stm32/src/pac/stm32l443cc.rs @@ -0,0 +1,488 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l443rc.rs b/embassy-stm32/src/pac/stm32l443rc.rs new file mode 100644 index 000000000..e1860a9de --- /dev/null +++ b/embassy-stm32/src/pac/stm32l443rc.rs @@ -0,0 +1,488 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l443vc.rs b/embassy-stm32/src/pac/stm32l443vc.rs new file mode 100644 index 000000000..e1860a9de --- /dev/null +++ b/embassy-stm32/src/pac/stm32l443vc.rs @@ -0,0 +1,488 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451cc.rs b/embassy-stm32/src/pac/stm32l451cc.rs new file mode 100644 index 000000000..29565d76d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451cc.rs @@ -0,0 +1,497 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451ce.rs b/embassy-stm32/src/pac/stm32l451ce.rs new file mode 100644 index 000000000..29565d76d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451ce.rs @@ -0,0 +1,497 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451rc.rs b/embassy-stm32/src/pac/stm32l451rc.rs new file mode 100644 index 000000000..29565d76d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451rc.rs @@ -0,0 +1,497 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451re.rs b/embassy-stm32/src/pac/stm32l451re.rs new file mode 100644 index 000000000..29565d76d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451re.rs @@ -0,0 +1,497 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451vc.rs b/embassy-stm32/src/pac/stm32l451vc.rs new file mode 100644 index 000000000..29565d76d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451vc.rs @@ -0,0 +1,497 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451ve.rs b/embassy-stm32/src/pac/stm32l451ve.rs new file mode 100644 index 000000000..29565d76d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451ve.rs @@ -0,0 +1,497 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452cc.rs b/embassy-stm32/src/pac/stm32l452cc.rs new file mode 100644 index 000000000..e6faacf14 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452cc.rs @@ -0,0 +1,500 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452ce.rs b/embassy-stm32/src/pac/stm32l452ce.rs new file mode 100644 index 000000000..e6faacf14 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452ce.rs @@ -0,0 +1,500 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452rc.rs b/embassy-stm32/src/pac/stm32l452rc.rs new file mode 100644 index 000000000..e6faacf14 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452rc.rs @@ -0,0 +1,500 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452re.rs b/embassy-stm32/src/pac/stm32l452re.rs new file mode 100644 index 000000000..e6faacf14 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452re.rs @@ -0,0 +1,500 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452vc.rs b/embassy-stm32/src/pac/stm32l452vc.rs new file mode 100644 index 000000000..e6faacf14 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452vc.rs @@ -0,0 +1,500 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452ve.rs b/embassy-stm32/src/pac/stm32l452ve.rs new file mode 100644 index 000000000..e6faacf14 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452ve.rs @@ -0,0 +1,500 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l462ce.rs b/embassy-stm32/src/pac/stm32l462ce.rs new file mode 100644 index 000000000..374f5bd5a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l462ce.rs @@ -0,0 +1,503 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l462re.rs b/embassy-stm32/src/pac/stm32l462re.rs new file mode 100644 index 000000000..374f5bd5a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l462re.rs @@ -0,0 +1,503 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l462ve.rs b/embassy-stm32/src/pac/stm32l462ve.rs new file mode 100644 index 000000000..374f5bd5a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l462ve.rs @@ -0,0 +1,503 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, + USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471qe.rs b/embassy-stm32/src/pac/stm32l471qe.rs new file mode 100644 index 000000000..1d4b4e8b5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471qe.rs @@ -0,0 +1,569 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471qg.rs b/embassy-stm32/src/pac/stm32l471qg.rs new file mode 100644 index 000000000..1d4b4e8b5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471qg.rs @@ -0,0 +1,569 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471re.rs b/embassy-stm32/src/pac/stm32l471re.rs new file mode 100644 index 000000000..1d4b4e8b5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471re.rs @@ -0,0 +1,569 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471rg.rs b/embassy-stm32/src/pac/stm32l471rg.rs new file mode 100644 index 000000000..1d4b4e8b5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471rg.rs @@ -0,0 +1,569 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471ve.rs b/embassy-stm32/src/pac/stm32l471ve.rs new file mode 100644 index 000000000..1d4b4e8b5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471ve.rs @@ -0,0 +1,569 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471vg.rs b/embassy-stm32/src/pac/stm32l471vg.rs new file mode 100644 index 000000000..1d4b4e8b5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471vg.rs @@ -0,0 +1,569 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471ze.rs b/embassy-stm32/src/pac/stm32l471ze.rs new file mode 100644 index 000000000..1d4b4e8b5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471ze.rs @@ -0,0 +1,569 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471zg.rs b/embassy-stm32/src/pac/stm32l471zg.rs new file mode 100644 index 000000000..1d4b4e8b5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471zg.rs @@ -0,0 +1,569 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475rc.rs b/embassy-stm32/src/pac/stm32l475rc.rs new file mode 100644 index 000000000..7d5fbfb85 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475rc.rs @@ -0,0 +1,572 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475re.rs b/embassy-stm32/src/pac/stm32l475re.rs new file mode 100644 index 000000000..7d5fbfb85 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475re.rs @@ -0,0 +1,572 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475rg.rs b/embassy-stm32/src/pac/stm32l475rg.rs new file mode 100644 index 000000000..7d5fbfb85 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475rg.rs @@ -0,0 +1,572 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475vc.rs b/embassy-stm32/src/pac/stm32l475vc.rs new file mode 100644 index 000000000..7d5fbfb85 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475vc.rs @@ -0,0 +1,572 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475ve.rs b/embassy-stm32/src/pac/stm32l475ve.rs new file mode 100644 index 000000000..7d5fbfb85 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475ve.rs @@ -0,0 +1,572 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475vg.rs b/embassy-stm32/src/pac/stm32l475vg.rs new file mode 100644 index 000000000..7d5fbfb85 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475vg.rs @@ -0,0 +1,572 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476je.rs b/embassy-stm32/src/pac/stm32l476je.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476je.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476jg.rs b/embassy-stm32/src/pac/stm32l476jg.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476jg.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476me.rs b/embassy-stm32/src/pac/stm32l476me.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476me.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476mg.rs b/embassy-stm32/src/pac/stm32l476mg.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476mg.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476qe.rs b/embassy-stm32/src/pac/stm32l476qe.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476qe.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476qg.rs b/embassy-stm32/src/pac/stm32l476qg.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476qg.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476rc.rs b/embassy-stm32/src/pac/stm32l476rc.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476rc.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476re.rs b/embassy-stm32/src/pac/stm32l476re.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476re.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476rg.rs b/embassy-stm32/src/pac/stm32l476rg.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476rg.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476vc.rs b/embassy-stm32/src/pac/stm32l476vc.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476vc.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476ve.rs b/embassy-stm32/src/pac/stm32l476ve.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476ve.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476vg.rs b/embassy-stm32/src/pac/stm32l476vg.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476vg.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476ze.rs b/embassy-stm32/src/pac/stm32l476ze.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476ze.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476zg.rs b/embassy-stm32/src/pac/stm32l476zg.rs new file mode 100644 index 000000000..2f2bb90b3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476zg.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l485jc.rs b/embassy-stm32/src/pac/stm32l485jc.rs new file mode 100644 index 000000000..cdd6b31d8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l485jc.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l485je.rs b/embassy-stm32/src/pac/stm32l485je.rs new file mode 100644 index 000000000..cdd6b31d8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l485je.rs @@ -0,0 +1,575 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l486jg.rs b/embassy-stm32/src/pac/stm32l486jg.rs new file mode 100644 index 000000000..aad81718f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l486jg.rs @@ -0,0 +1,578 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l486qg.rs b/embassy-stm32/src/pac/stm32l486qg.rs new file mode 100644 index 000000000..aad81718f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l486qg.rs @@ -0,0 +1,578 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l486rg.rs b/embassy-stm32/src/pac/stm32l486rg.rs new file mode 100644 index 000000000..aad81718f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l486rg.rs @@ -0,0 +1,578 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l486vg.rs b/embassy-stm32/src/pac/stm32l486vg.rs new file mode 100644 index 000000000..aad81718f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l486vg.rs @@ -0,0 +1,578 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l486zg.rs b/embassy-stm32/src/pac/stm32l486zg.rs new file mode 100644 index 000000000..aad81718f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l486zg.rs @@ -0,0 +1,578 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG, USART1, USART2, + USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496ae.rs b/embassy-stm32/src/pac/stm32l496ae.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496ae.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496ag.rs b/embassy-stm32/src/pac/stm32l496ag.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496ag.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496qe.rs b/embassy-stm32/src/pac/stm32l496qe.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496qe.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496qg.rs b/embassy-stm32/src/pac/stm32l496qg.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496qg.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496re.rs b/embassy-stm32/src/pac/stm32l496re.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496re.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496rg.rs b/embassy-stm32/src/pac/stm32l496rg.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496rg.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496ve.rs b/embassy-stm32/src/pac/stm32l496ve.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496ve.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496vg.rs b/embassy-stm32/src/pac/stm32l496vg.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496vg.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496wg.rs b/embassy-stm32/src/pac/stm32l496wg.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496wg.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496ze.rs b/embassy-stm32/src/pac/stm32l496ze.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496ze.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496zg.rs b/embassy-stm32/src/pac/stm32l496zg.rs new file mode 100644 index 000000000..b47a6359e --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496zg.rs @@ -0,0 +1,628 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4a6ag.rs b/embassy-stm32/src/pac/stm32l4a6ag.rs new file mode 100644 index 000000000..bb345cad9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4a6ag.rs @@ -0,0 +1,631 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4a6qg.rs b/embassy-stm32/src/pac/stm32l4a6qg.rs new file mode 100644 index 000000000..bb345cad9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4a6qg.rs @@ -0,0 +1,631 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4a6rg.rs b/embassy-stm32/src/pac/stm32l4a6rg.rs new file mode 100644 index 000000000..bb345cad9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4a6rg.rs @@ -0,0 +1,631 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4a6vg.rs b/embassy-stm32/src/pac/stm32l4a6vg.rs new file mode 100644 index 000000000..bb345cad9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4a6vg.rs @@ -0,0 +1,631 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4a6zg.rs b/embassy-stm32/src/pac/stm32l4a6zg.rs new file mode 100644 index 000000000..bb345cad9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4a6zg.rs @@ -0,0 +1,631 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5ae.rs b/embassy-stm32/src/pac/stm32l4p5ae.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5ae.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5ag.rs b/embassy-stm32/src/pac/stm32l4p5ag.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5ag.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5ce.rs b/embassy-stm32/src/pac/stm32l4p5ce.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5ce.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5cg.rs b/embassy-stm32/src/pac/stm32l4p5cg.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5cg.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5qe.rs b/embassy-stm32/src/pac/stm32l4p5qe.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5qe.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5qg.rs b/embassy-stm32/src/pac/stm32l4p5qg.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5qg.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5re.rs b/embassy-stm32/src/pac/stm32l4p5re.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5re.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5rg.rs b/embassy-stm32/src/pac/stm32l4p5rg.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5rg.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5ve.rs b/embassy-stm32/src/pac/stm32l4p5ve.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5ve.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5vg.rs b/embassy-stm32/src/pac/stm32l4p5vg.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5vg.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5ze.rs b/embassy-stm32/src/pac/stm32l4p5ze.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5ze.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5zg.rs b/embassy-stm32/src/pac/stm32l4p5zg.rs new file mode 100644 index 000000000..e057a6852 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5zg.rs @@ -0,0 +1,616 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5ag.rs b/embassy-stm32/src/pac/stm32l4q5ag.rs new file mode 100644 index 000000000..7dcc4d6c6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5ag.rs @@ -0,0 +1,622 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5cg.rs b/embassy-stm32/src/pac/stm32l4q5cg.rs new file mode 100644 index 000000000..7dcc4d6c6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5cg.rs @@ -0,0 +1,622 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5qg.rs b/embassy-stm32/src/pac/stm32l4q5qg.rs new file mode 100644 index 000000000..7dcc4d6c6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5qg.rs @@ -0,0 +1,622 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5rg.rs b/embassy-stm32/src/pac/stm32l4q5rg.rs new file mode 100644 index 000000000..7dcc4d6c6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5rg.rs @@ -0,0 +1,622 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5vg.rs b/embassy-stm32/src/pac/stm32l4q5vg.rs new file mode 100644 index 000000000..7dcc4d6c6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5vg.rs @@ -0,0 +1,622 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5zg.rs b/embassy-stm32/src/pac/stm32l4q5zg.rs new file mode 100644 index 000000000..7dcc4d6c6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5zg.rs @@ -0,0 +1,622 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5ag.rs b/embassy-stm32/src/pac/stm32l4r5ag.rs new file mode 100644 index 000000000..a9edcc96f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5ag.rs @@ -0,0 +1,615 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5ai.rs b/embassy-stm32/src/pac/stm32l4r5ai.rs new file mode 100644 index 000000000..a9edcc96f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5ai.rs @@ -0,0 +1,615 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5qg.rs b/embassy-stm32/src/pac/stm32l4r5qg.rs new file mode 100644 index 000000000..a9edcc96f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5qg.rs @@ -0,0 +1,615 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5qi.rs b/embassy-stm32/src/pac/stm32l4r5qi.rs new file mode 100644 index 000000000..a9edcc96f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5qi.rs @@ -0,0 +1,615 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5vg.rs b/embassy-stm32/src/pac/stm32l4r5vg.rs new file mode 100644 index 000000000..a9edcc96f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5vg.rs @@ -0,0 +1,615 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5vi.rs b/embassy-stm32/src/pac/stm32l4r5vi.rs new file mode 100644 index 000000000..a9edcc96f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5vi.rs @@ -0,0 +1,615 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5zg.rs b/embassy-stm32/src/pac/stm32l4r5zg.rs new file mode 100644 index 000000000..a9edcc96f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5zg.rs @@ -0,0 +1,615 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5zi.rs b/embassy-stm32/src/pac/stm32l4r5zi.rs new file mode 100644 index 000000000..a9edcc96f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5zi.rs @@ -0,0 +1,615 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r7ai.rs b/embassy-stm32/src/pac/stm32l4r7ai.rs new file mode 100644 index 000000000..7118408a7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r7ai.rs @@ -0,0 +1,624 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r7vi.rs b/embassy-stm32/src/pac/stm32l4r7vi.rs new file mode 100644 index 000000000..7118408a7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r7vi.rs @@ -0,0 +1,624 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r7zi.rs b/embassy-stm32/src/pac/stm32l4r7zi.rs new file mode 100644 index 000000000..7118408a7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r7zi.rs @@ -0,0 +1,624 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9ag.rs b/embassy-stm32/src/pac/stm32l4r9ag.rs new file mode 100644 index 000000000..f2636f3dc --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9ag.rs @@ -0,0 +1,627 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9ai.rs b/embassy-stm32/src/pac/stm32l4r9ai.rs new file mode 100644 index 000000000..f2636f3dc --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9ai.rs @@ -0,0 +1,627 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9vg.rs b/embassy-stm32/src/pac/stm32l4r9vg.rs new file mode 100644 index 000000000..f2636f3dc --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9vg.rs @@ -0,0 +1,627 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9vi.rs b/embassy-stm32/src/pac/stm32l4r9vi.rs new file mode 100644 index 000000000..f2636f3dc --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9vi.rs @@ -0,0 +1,627 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9zg.rs b/embassy-stm32/src/pac/stm32l4r9zg.rs new file mode 100644 index 000000000..f2636f3dc --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9zg.rs @@ -0,0 +1,627 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9zi.rs b/embassy-stm32/src/pac/stm32l4r9zi.rs new file mode 100644 index 000000000..f2636f3dc --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9zi.rs @@ -0,0 +1,627 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s5ai.rs b/embassy-stm32/src/pac/stm32l4s5ai.rs new file mode 100644 index 000000000..a86c017f6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s5ai.rs @@ -0,0 +1,618 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s5qi.rs b/embassy-stm32/src/pac/stm32l4s5qi.rs new file mode 100644 index 000000000..a86c017f6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s5qi.rs @@ -0,0 +1,618 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s5vi.rs b/embassy-stm32/src/pac/stm32l4s5vi.rs new file mode 100644 index 000000000..a86c017f6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s5vi.rs @@ -0,0 +1,618 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s5zi.rs b/embassy-stm32/src/pac/stm32l4s5zi.rs new file mode 100644 index 000000000..a86c017f6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s5zi.rs @@ -0,0 +1,618 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s7ai.rs b/embassy-stm32/src/pac/stm32l4s7ai.rs new file mode 100644 index 000000000..fbba75ae2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s7ai.rs @@ -0,0 +1,627 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s7vi.rs b/embassy-stm32/src/pac/stm32l4s7vi.rs new file mode 100644 index 000000000..fbba75ae2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s7vi.rs @@ -0,0 +1,627 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s7zi.rs b/embassy-stm32/src/pac/stm32l4s7zi.rs new file mode 100644 index 000000000..fbba75ae2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s7zi.rs @@ -0,0 +1,627 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s9ai.rs b/embassy-stm32/src/pac/stm32l4s9ai.rs new file mode 100644 index 000000000..c19cf10d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s9ai.rs @@ -0,0 +1,630 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s9vi.rs b/embassy-stm32/src/pac/stm32l4s9vi.rs new file mode 100644 index 000000000..c19cf10d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s9vi.rs @@ -0,0 +1,630 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s9zi.rs b/embassy-stm32/src/pac/stm32l4s9zi.rs new file mode 100644 index 000000000..c19cf10d7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s9zi.rs @@ -0,0 +1,630 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, EXTI, RNG, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs index a618bd093..f3f0ce1fa 100644 --- a/embassy-stm32/src/rng.rs +++ b/embassy-stm32/src/rng.rs @@ -1,4 +1,4 @@ -use crate::pac::rng_v1::{regs, Rng}; +use crate::pac::rng::{regs, Rng}; use crate::peripherals; use embassy::util::Unborrow; use embassy_extras::unborrow; @@ -8,26 +8,23 @@ pub struct Random { } impl Random { - pub fn new(inner: impl Unborrow) -> Self { + pub fn new(inner: impl Unborrow) -> Self { unborrow!(inner); - Self { - inner, - } + Self { inner } } } -use embassy::traits::rng::Rng as RngTrait; use core::future::Future; use core::marker::PhantomData; +use embassy::traits::rng::Rng as RngTrait; -impl RngTrait for Random { +impl RngTrait for Random { type Error = (); - type RngFuture<'a> where Self: 'a = impl Future>; + #[rustfmt::skip] + type RngFuture<'a> where Self: 'a = impl Future>; fn fill<'a>(&'a mut self, dest: &'a mut [u8]) -> Self::RngFuture<'a> { - async move { - Ok(()) - } + async move { Ok(()) } } } @@ -42,13 +39,13 @@ pub(crate) mod sealed { pub trait Instance: sealed::Instance {} macro_rules! impl_rng { - ($addr:expr) => { - impl crate::rng::sealed::Instance for peripherals::RNG { - fn regs(&self) -> crate::pac::rng_v1::Rng { - crate::pac::rng_v1::Rng($addr as _) + ($inst:ident) => { + impl crate::rng::sealed::Instance for peripherals::$inst { + fn regs(&self) -> crate::pac::rng::Rng { + crate::pac::$inst } } - impl crate::rng::Instance for peripherals::RNG {} - } -} \ No newline at end of file + impl crate::rng::Instance for peripherals::$inst {} + }; +} diff --git a/embassy-stm32/src/usart.rs b/embassy-stm32/src/usart.rs index 3d9e3f54c..2232ac57e 100644 --- a/embassy-stm32/src/usart.rs +++ b/embassy-stm32/src/usart.rs @@ -4,7 +4,7 @@ use embassy::util::Unborrow; use embassy_extras::unborrow; use crate::gpio::{NoPin, Pin}; -use crate::pac::usart_v1::{regs, vals, Usart}; +use crate::pac::usart::{regs, vals, Usart}; use crate::peripherals; #[non_exhaustive] @@ -99,10 +99,10 @@ impl sealed::CkPin for NoPin { impl CkPin for NoPin {} macro_rules! impl_usart { - ($inst:ident, $addr:expr) => { + ($inst:ident) => { impl crate::usart::sealed::Instance for peripherals::$inst { - fn regs(&self) -> crate::pac::usart_v1::Usart { - crate::pac::usart_v1::Usart($addr as _) + fn regs(&self) -> crate::pac::usart::Usart { + crate::pac::$inst } } impl crate::usart::Instance for peripherals::$inst {} diff --git a/embassy-stm32/stm32-data b/embassy-stm32/stm32-data index 0ffc2d500..062fa8117 160000 --- a/embassy-stm32/stm32-data +++ b/embassy-stm32/stm32-data @@ -1 +1 @@ -Subproject commit 0ffc2d50063823ceb77f03dece80f9708c7f60fe +Subproject commit 062fa81175065c6ca99f2b40214cce30d27b4c2f -- cgit