From 64e23b79cce5c2b551110a4b8d446dbcb42ac3bd Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 10 Dec 2025 15:58:28 +0100
Subject: nrf/cracen: fix bus fault on drop.

Accessing the RNGCONTROL reg bus faults when ENABLE.RNG=0.
Do all the enabling in start_rng/stop_rng, then do nothing on drop.

This is fine now that we only have blocking RNG, we'll have to do something fancier in the future.
---
 embassy-nrf/src/cracen.rs | 30 +++++++++++-------------------
 1 file changed, 11 insertions(+), 19 deletions(-)

diff --git a/embassy-nrf/src/cracen.rs b/embassy-nrf/src/cracen.rs
index 47ef1cd87..6381701c0 100644
--- a/embassy-nrf/src/cracen.rs
+++ b/embassy-nrf/src/cracen.rs
@@ -18,10 +18,7 @@ pub struct Cracen<'d, M: Mode> {
 impl<'d> Cracen<'d, Blocking> {
     /// Create a new CRACEN driver.
     pub fn new_blocking(_peri: Peri<'d, peripherals::CRACEN>) -> Self {
-        let me = Self { _peri, _p: PhantomData };
-
-        me.stop();
-        me
+        Self { _peri, _p: PhantomData }
     }
 }
 
@@ -48,7 +45,14 @@ impl<'d, M: Mode> Cracen<'d, M> {
         while r.rngcontrol().status().read().state() == pac::cracencore::vals::State::STARTUP {}
     }
 
-    fn stop(&self) {
+    fn stop_rng(&self) {
+        let r = Self::core();
+        r.rngcontrol().control().write(|w| {
+            w.set_enable(false);
+        });
+
+        while r.rngcontrol().status().read().state() != pac::cracencore::vals::State::RESET {}
+
         let r = Self::regs();
         r.enable().write(|w| {
             w.set_cryptomaster(false);
@@ -69,7 +73,7 @@ impl<'d, M: Mode> Cracen<'d, M> {
             chunk[..to_copy].copy_from_slice(&word[..to_copy]);
         }
 
-        self.stop();
+        self.stop_rng();
     }
 
     /// Generate a random u32
@@ -90,19 +94,7 @@ impl<'d, M: Mode> Cracen<'d, M> {
 
 impl<'d, M: Mode> Drop for Cracen<'d, M> {
     fn drop(&mut self) {
-        let r = Self::core();
-        r.rngcontrol().control().write(|w| {
-            w.set_enable(false);
-        });
-
-        while r.rngcontrol().status().read().state() != pac::cracencore::vals::State::RESET {}
-
-        let r = Self::regs();
-        r.enable().write(|w| {
-            w.set_cryptomaster(false);
-            w.set_rng(false);
-            w.set_pkeikg(false);
-        });
+        // nothing to do here, since we stop+disable rng for each operation.
     }
 }
 
-- 
cgit