From 7e3ca6067be7e2361ccd75f9712a0d08fa7d2d6a Mon Sep 17 00:00:00 2001 From: Brian Schwind Date: Sat, 4 Oct 2025 13:22:35 +0900 Subject: hspi: properly configure the transfer size --- embassy-stm32/src/hspi/mod.rs | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/embassy-stm32/src/hspi/mod.rs b/embassy-stm32/src/hspi/mod.rs index 277f69496..b64a6b62c 100644 --- a/embassy-stm32/src/hspi/mod.rs +++ b/embassy-stm32/src/hspi/mod.rs @@ -498,7 +498,8 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> { w.set_dmaen(false); }); - self.configure_command(&transaction, Some(buf.len()))?; + let transfer_size_bytes = buf.len() * W::size().bytes(); + self.configure_command(&transaction, Some(transfer_size_bytes))?; let current_address = T::REGS.ar().read().address(); let current_instruction = T::REGS.ir().read().instruction(); @@ -537,7 +538,8 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> { w.set_dmaen(false); }); - self.configure_command(&transaction, Some(buf.len()))?; + let transfer_size_bytes = buf.len() * W::size().bytes(); + self.configure_command(&transaction, Some(transfer_size_bytes))?; T::REGS .cr() @@ -767,7 +769,8 @@ impl<'d, T: Instance> Hspi<'d, T, Async> { // Wait for peripheral to be free while T::REGS.sr().read().busy() {} - self.configure_command(&transaction, Some(buf.len()))?; + let transfer_size_bytes = buf.len() * W::size().bytes(); + self.configure_command(&transaction, Some(transfer_size_bytes))?; let current_address = T::REGS.ar().read().address(); let current_instruction = T::REGS.ir().read().instruction(); @@ -807,7 +810,8 @@ impl<'d, T: Instance> Hspi<'d, T, Async> { // Wait for peripheral to be free while T::REGS.sr().read().busy() {} - self.configure_command(&transaction, Some(buf.len()))?; + let transfer_size_bytes = buf.len() * W::size().bytes(); + self.configure_command(&transaction, Some(transfer_size_bytes))?; T::REGS .cr() .modify(|v| v.set_fmode(FunctionalMode::IndirectWrite.into())); @@ -837,7 +841,8 @@ impl<'d, T: Instance> Hspi<'d, T, Async> { // Wait for peripheral to be free while T::REGS.sr().read().busy() {} - self.configure_command(&transaction, Some(buf.len()))?; + let transfer_size_bytes = buf.len() * W::size().bytes(); + self.configure_command(&transaction, Some(transfer_size_bytes))?; let current_address = T::REGS.ar().read().address(); let current_instruction = T::REGS.ir().read().instruction(); @@ -877,7 +882,8 @@ impl<'d, T: Instance> Hspi<'d, T, Async> { // Wait for peripheral to be free while T::REGS.sr().read().busy() {} - self.configure_command(&transaction, Some(buf.len()))?; + let transfer_size_bytes = buf.len() * W::size().bytes(); + self.configure_command(&transaction, Some(transfer_size_bytes))?; T::REGS .cr() .modify(|v| v.set_fmode(FunctionalMode::IndirectWrite.into())); -- cgit