From 94080b38a5b8dec05210b5b1377d595b2640488c Mon Sep 17 00:00:00 2001 From: Benjamin Date: Tue, 3 Jun 2025 20:29:06 +0200 Subject: Added Option to enable HW Oversampling in STM32 V3 ADCs. Copied from adc/v4.rs and adjusted to reflect 2 to 256x oversampling + adjusted bit shifting operations --- embassy-stm32/src/adc/v3.rs | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index 313244e19..f561f817c 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -93,6 +93,18 @@ cfg_if! { } } +/// Number of samples used for averaging. +pub enum Averaging { + Disabled, + Samples2, + Samples4, + Samples8, + Samples16, + Samples32, + Samples64, + Samples128, + Samples256, +} impl<'d, T: Instance> Adc<'d, T> { pub fn new(adc: Peri<'d, T>) -> Self { rcc::enable_and_reset::(); @@ -223,6 +235,25 @@ impl<'d, T: Instance> Adc<'d, T> { T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into())); } + pub fn set_averaging(&mut self, averaging: Averaging) { + let (enable, samples, right_shift) = match averaging { + Averaging::Disabled => (false, 0, 0), + Averaging::Samples2 => (true, 0, 1), + Averaging::Samples4 => (true, 1, 2), + Averaging::Samples8 => (true, 2, 3), + Averaging::Samples16 => (true, 3, 4), + Averaging::Samples32 => (true, 4, 5), + Averaging::Samples64 => (true, 5, 6), + Averaging::Samples128 => (true, 6, 7), + Averaging::Samples256 => (true, 7, 8), + }; + + T::regs().cfgr2().modify(|reg| { + reg.set_rovse(enable); + reg.set_ovsr(samples); + reg.set_ovss(right_shift); + }) + } /* /// Convert a raw sample from the `Temperature` to deg C pub fn to_degrees_centigrade(sample: u16) -> f32 { -- cgit From a912a3798d5321d099765df4e1af16158699c8d5 Mon Sep 17 00:00:00 2001 From: Benjamin Date: Tue, 3 Jun 2025 21:04:41 +0200 Subject: Fixed variations in register access for different families --- embassy-stm32/src/adc/v3.rs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index f561f817c..c032113d5 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -247,9 +247,14 @@ impl<'d, T: Instance> Adc<'d, T> { Averaging::Samples128 => (true, 6, 7), Averaging::Samples256 => (true, 7, 8), }; - T::regs().cfgr2().modify(|reg| { + #[cfg(not(adc_g0))] reg.set_rovse(enable); + #[cfg(adc_g0)] + reg.set_ovse(enable); + #[cfg(any(adc_h5, adc_h7rs))] + reg.set_ovsr(samples.into()); + #[cfg(not(any(adc_h5, adc_h7rs)))] reg.set_ovsr(samples); reg.set_ovss(right_shift); }) -- cgit From adb728009ceba095d2190038ff698aaee08907a9 Mon Sep 17 00:00:00 2001 From: Benjamin Date: Tue, 3 Jun 2025 21:10:19 +0200 Subject: adjusted for u0 as well --- embassy-stm32/src/adc/v3.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index c032113d5..7b5df80b8 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -248,9 +248,9 @@ impl<'d, T: Instance> Adc<'d, T> { Averaging::Samples256 => (true, 7, 8), }; T::regs().cfgr2().modify(|reg| { - #[cfg(not(adc_g0))] + #[cfg(not(any(adc_g0, adc_u0)))] reg.set_rovse(enable); - #[cfg(adc_g0)] + #[cfg(any(adc_g0, adc_u0))] reg.set_ovse(enable); #[cfg(any(adc_h5, adc_h7rs))] reg.set_ovsr(samples.into()); -- cgit From 777e0c71c99fde779cf91c364849ac6906cb3d97 Mon Sep 17 00:00:00 2001 From: emkanea-dev Date: Fri, 25 Jul 2025 20:53:04 +0200 Subject: fixed build after rebase --- embassy-stm32/src/adc/v3.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index 805dae564..a2e42fe52 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -257,8 +257,8 @@ impl<'d, T: Instance> Adc<'d, T> { #[cfg(any(adc_h5, adc_h7rs))] reg.set_ovsr(samples.into()); #[cfg(not(any(adc_h5, adc_h7rs)))] - reg.set_ovsr(samples); - reg.set_ovss(right_shift); + reg.set_ovsr(samples.into()); + reg.set_ovss(right_shift.into()); }) } /* -- cgit