From 219de4be85f6e63e73693c934be54687c9ad860c Mon Sep 17 00:00:00 2001
From: Gerzain Mata <leftger@gmail.com>
Date: Wed, 19 Nov 2025 20:45:36 -0700
Subject: stm32: Fixed ADC4 enable() for WBA

---
 embassy-stm32/CHANGELOG.md        |  1 +
 embassy-stm32/src/adc/adc4.rs     | 18 +++++++++++++++++-
 examples/stm32wba6/src/bin/adc.rs | 28 +++++++++++++++++++++++++++-
 3 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index d2f675dbc..8dc34ff72 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## Unreleased - ReleaseDate
 
+- fix: Fixed ADC4 enable() for WBA
 - feat: add poll_for methods to exti
 - feat: implement stop for stm32wb.
 - change: rework hsem and add HIL test for some chips.
diff --git a/embassy-stm32/src/adc/adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 499fc2093..472eb46fd 100644
--- a/embassy-stm32/src/adc/adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -113,10 +113,26 @@ foreach_adc!(
             }
 
             fn enable() {
+                let cr_initial = ADC4::regs().cr().read();
+                let isr_initial = ADC4::regs().isr().read();
+
+                if cr_initial.aden() && isr_initial.adrdy() {
+                    return;
+                }
+
+                if cr_initial.aden() || cr_initial.adstart() {
+                    if cr_initial.adstart() {
+                        ADC4::regs().cr().modify(|w| w.set_adstp(true));
+                        while ADC4::regs().cr().read().adstart() {}
+                    }
+
+                    ADC4::regs().cr().modify(|w| w.set_addis(true));
+                    while ADC4::regs().cr().read().aden() {}
+                }
+
                 ADC4::regs().isr().write(|w| w.set_adrdy(true));
                 ADC4::regs().cr().modify(|w| w.set_aden(true));
                 while !ADC4::regs().isr().read().adrdy() {}
-                ADC4::regs().isr().write(|w| w.set_adrdy(true));
             }
 
             fn start() {
diff --git a/examples/stm32wba6/src/bin/adc.rs b/examples/stm32wba6/src/bin/adc.rs
index 9d1f39419..14f4a0636 100644
--- a/examples/stm32wba6/src/bin/adc.rs
+++ b/examples/stm32wba6/src/bin/adc.rs
@@ -3,11 +3,37 @@
 
 use defmt::*;
 use embassy_stm32::adc::{Adc, AdcChannel, SampleTime, adc4};
+use embassy_stm32::Config;
+use embassy_stm32::rcc::{
+    AHB5Prescaler, AHBPrescaler, APBPrescaler, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk, VoltageScale,
+};
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
 async fn main(_spawner: embassy_executor::Spawner) {
-    let config = embassy_stm32::Config::default();
+    let mut config = Config::default();
+    // Fine-tune PLL1 dividers/multipliers
+    config.rcc.pll1 = Some(embassy_stm32::rcc::Pll {
+        source: PllSource::HSI,
+        prediv: PllPreDiv::DIV1,  // PLLM = 1 → HSI / 1 = 16 MHz
+        mul: PllMul::MUL30,       // PLLN = 30 → 16 MHz * 30 = 480 MHz VCO
+        divr: Some(PllDiv::DIV5), // PLLR = 5 → 96 MHz (Sysclk)
+        // divq: Some(PllDiv::DIV10), // PLLQ = 10 → 48 MHz (NOT USED)
+        divq: None,
+        divp: Some(PllDiv::DIV30), // PLLP = 30 → 16 MHz (USBOTG)
+        frac: Some(0),             // Fractional part (enabled)
+    });
+
+    config.rcc.ahb_pre = AHBPrescaler::DIV1;
+    config.rcc.apb1_pre = APBPrescaler::DIV1;
+    config.rcc.apb2_pre = APBPrescaler::DIV1;
+    config.rcc.apb7_pre = APBPrescaler::DIV1;
+    config.rcc.ahb5_pre = AHB5Prescaler::DIV4;
+
+    // voltage scale for max performance
+    config.rcc.voltage_scale = VoltageScale::RANGE1;
+    // route PLL1_P into the USB‐OTG‐HS block
+    config.rcc.sys = Sysclk::PLL1_R;
 
     let mut p = embassy_stm32::init(config);
 
-- 
cgit