From a021b4940c852f01322a20a7358bc1a549b3d3c4 Mon Sep 17 00:00:00 2001 From: datdenkikniet Date: Wed, 12 Nov 2025 21:51:55 +0100 Subject: Move SMA responsibility to SMA peripheral --- embassy-stm32/build.rs | 5 ++ embassy-stm32/src/eth/mod.rs | 13 ++--- embassy-stm32/src/eth/sma/mod.rs | 32 ++++++++++-- embassy-stm32/src/eth/sma/v1.rs | 102 +++++++++++++++++++++++++++++++++++++++ embassy-stm32/src/eth/sma/v2.rs | 94 ++++++++++++++++++++++++++++++++++++ embassy-stm32/src/eth/v1/mod.rs | 89 +++++----------------------------- embassy-stm32/src/eth/v2/mod.rs | 81 +++---------------------------- 7 files changed, 249 insertions(+), 167 deletions(-) create mode 100644 embassy-stm32/src/eth/sma/v1.rs create mode 100644 embassy-stm32/src/eth/sma/v2.rs diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs index 9dd94941c..8cbd38e10 100644 --- a/embassy-stm32/build.rs +++ b/embassy-stm32/build.rs @@ -1404,6 +1404,11 @@ fn main() { } } + // MDIO and MDC are special + if pin.signal == "MDIO" || pin.signal == "MDC" { + peri = format_ident!("{}", "ETH_SMA"); + } + // XSPI NCS pin to CSSEL mapping if pin.signal.ends_with("NCS1") { g.extend(quote! { diff --git a/embassy-stm32/src/eth/mod.rs b/embassy-stm32/src/eth/mod.rs index bef6a02b2..448d21f3f 100644 --- a/embassy-stm32/src/eth/mod.rs +++ b/embassy-stm32/src/eth/mod.rs @@ -16,6 +16,7 @@ use embassy_sync::waitqueue::AtomicWaker; pub use self::_version::{InterruptHandler, *}; pub use self::generic_phy::*; +pub use self::sma::{Sma, StationManagement}; use crate::rcc::RccPeripheral; #[allow(unused)] @@ -158,14 +159,6 @@ impl<'a, 'd> embassy_net_driver::TxToken for TxToken<'a, 'd> { } } -/// Station Management Interface (SMI) on an ethernet PHY -pub trait StationManagement { - /// Read a register over SMI. - fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16; - /// Write a register over SMI. - fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16); -} - /// Trait for an Ethernet PHY pub trait Phy { /// Reset PHY and wait for it to come out of reset. @@ -213,8 +206,8 @@ impl Instance for crate::peripherals::ETH {} pin_trait!(RXClkPin, Instance, @A); pin_trait!(TXClkPin, Instance, @A); pin_trait!(RefClkPin, Instance, @A); -pin_trait!(MDIOPin, Instance, @A); -pin_trait!(MDCPin, Instance, @A); +pin_trait!(MDIOPin, sma::Instance, @A); +pin_trait!(MDCPin, sma::Instance, @A); pin_trait!(RXDVPin, Instance, @A); pin_trait!(CRSPin, Instance, @A); pin_trait!(RXD0Pin, Instance, @A); diff --git a/embassy-stm32/src/eth/sma/mod.rs b/embassy-stm32/src/eth/sma/mod.rs index 106a6b2bd..558107abc 100644 --- a/embassy-stm32/src/eth/sma/mod.rs +++ b/embassy-stm32/src/eth/sma/mod.rs @@ -2,13 +2,22 @@ #![macro_use] +#[cfg_attr(eth_v2, path = "v2.rs")] +#[cfg_attr(any(eth_v1a, eth_v1b, eth_v1c), path = "v1.rs")] +mod _version; + use embassy_hal_internal::PeripheralType; -#[cfg(eth_v2)] -pub(crate) use regs::{Macmdioar as AddressRegister, Macmdiodr as DataRegister}; -#[cfg(any(eth_v1a, eth_v1b, eth_v1c))] -pub(crate) use regs::{Macmiiar as AddressRegister, Macmiidr as DataRegister}; use stm32_metapac::common::{RW, Reg}; -use stm32_metapac::eth::regs; + +pub use self::_version::*; + +/// Station Management Interface (SMI). +pub trait StationManagement { + /// Read a register over SMI. + fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16; + /// Write a register over SMI. + fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16); +} trait SealedInstance { fn regs() -> (Reg, Reg); @@ -30,4 +39,17 @@ impl SealedInstance for crate::peripherals::ETH_SMA { } } +impl SealedInstance for T { + fn regs() -> (Reg, Reg) { + let mac = ::regs().ethernet_mac(); + + #[cfg(any(eth_v1a, eth_v1b, eth_v1c))] + return (mac.macmiiar(), mac.macmiidr()); + + #[cfg(eth_v2)] + return (mac.macmdioar(), mac.macmdiodr()); + } +} + impl Instance for crate::peripherals::ETH_SMA {} +impl Instance for T {} diff --git a/embassy-stm32/src/eth/sma/v1.rs b/embassy-stm32/src/eth/sma/v1.rs new file mode 100644 index 000000000..db64a6c78 --- /dev/null +++ b/embassy-stm32/src/eth/sma/v1.rs @@ -0,0 +1,102 @@ +use embassy_hal_internal::Peri; +pub(crate) use regs::{Macmiiar as AddressRegister, Macmiidr as DataRegister}; +use stm32_metapac::eth::regs; +use stm32_metapac::eth::vals::{Cr, MbProgress, Mw}; + +use super::{Instance, StationManagement}; +use crate::eth::{MDCPin, MDIOPin}; +use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed}; + +/// Station Management Agent. +/// +/// This peripheral is used for SMI reads and writes to the connected +/// ethernet PHY/device(s). +pub struct Sma<'d, T: Instance> { + _peri: Peri<'d, T>, + clock_range: Cr, + pins: [Peri<'d, AnyPin>; 2], +} + +impl<'d, T: Instance> Sma<'d, T> { + /// Create a new instance of this peripheral. + pub fn new<#[cfg(afio)] A>( + peri: Peri<'d, T>, + mdio: Peri<'d, if_afio!(impl MDIOPin)>, + mdc: Peri<'d, if_afio!(impl MDCPin)>, + ) -> Self { + set_as_af!(mdio, AfType::output(OutputType::PushPull, Speed::VeryHigh)); + set_as_af!(mdc, AfType::output(OutputType::PushPull, Speed::VeryHigh)); + + // Enable necessary clocks. + critical_section::with(|_| { + #[cfg(eth_v1a)] + let reg = crate::pac::RCC.ahbenr(); + + #[cfg(any(eth_v1b, eth_v1c))] + let reg = crate::pac::RCC.ahb1enr(); + + reg.modify(|w| { + w.set_ethen(true); + }) + }); + + let hclk = unsafe { crate::rcc::get_freqs().hclk1.to_hertz() }; + let hclk = unwrap!(hclk, "SMA requires HCLK to be enabled, but it was not."); + let hclk_mhz = hclk.0 / 1_000_000; + + // Set the MDC clock frequency in the range 1MHz - 2.5MHz + let clock_range = match hclk_mhz { + 0..=24 => panic!("Invalid HCLK frequency - should be at least 25 MHz."), + 25..=34 => Cr::CR_20_35, // Divide by 16 + 35..=59 => Cr::CR_35_60, // Divide by 26 + 60..=99 => Cr::CR_60_100, // Divide by 42 + 100..=149 => Cr::CR_100_150, // Divide by 62 + 150..=216 => Cr::CR_150_168, // Divide by 102 + _ => { + panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider") + } + }; + + Self { + _peri: peri, + clock_range, + pins: [mdio.into(), mdc.into()], + } + } +} + +impl StationManagement for Sma<'_, T> { + fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 { + let (macmiiar, macmiidr) = T::regs(); + + macmiiar.modify(|w| { + w.set_pa(phy_addr); + w.set_mr(reg); + w.set_mw(Mw::READ); // read operation + w.set_cr(self.clock_range); + w.set_mb(MbProgress::BUSY); // indicate that operation is in progress + }); + while macmiiar.read().mb() == MbProgress::BUSY {} + macmiidr.read().md() + } + + fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) { + let (macmiiar, macmiidr) = T::regs(); + + macmiidr.write(|w| w.set_md(val)); + macmiiar.modify(|w| { + w.set_pa(phy_addr); + w.set_mr(reg); + w.set_mw(Mw::WRITE); // write + w.set_cr(self.clock_range); + w.set_mb(MbProgress::BUSY); + }); + while macmiiar.read().mb() == MbProgress::BUSY {} + } +} + +impl Drop for Sma<'_, T> { + fn drop(&mut self) { + self.pins.iter_mut().for_each(|p| p.set_as_disconnected()); + } +} diff --git a/embassy-stm32/src/eth/sma/v2.rs b/embassy-stm32/src/eth/sma/v2.rs new file mode 100644 index 000000000..6bc5230b5 --- /dev/null +++ b/embassy-stm32/src/eth/sma/v2.rs @@ -0,0 +1,94 @@ +use embassy_hal_internal::Peri; +pub(crate) use regs::{Macmdioar as AddressRegister, Macmdiodr as DataRegister}; +use stm32_metapac::eth::regs; + +use super::{Instance, StationManagement}; +use crate::eth::{MDCPin, MDIOPin}; +use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed}; + +/// Station Management Agent. +/// +/// This peripheral is used for SMI reads and writes to the connected +/// ethernet PHY/device(s). +pub struct Sma<'d, T: Instance> { + _peri: Peri<'d, T>, + pins: [Peri<'d, AnyPin>; 2], + clock_range: u8, +} + +impl<'d, T: Instance> Sma<'d, T> { + /// Create a new instance of this peripheral. + pub fn new(peri: Peri<'d, T>, mdio: Peri<'d, impl MDIOPin>, mdc: Peri<'d, impl MDCPin>) -> Self { + set_as_af!(mdio, AfType::output(OutputType::PushPull, Speed::VeryHigh)); + set_as_af!(mdc, AfType::output(OutputType::PushPull, Speed::VeryHigh)); + + // Enable necessary clocks. + critical_section::with(|_| { + crate::pac::RCC.ahb1enr().modify(|w| { + w.set_ethen(true); + }) + }); + + let hclk = unsafe { crate::rcc::get_freqs().hclk1.to_hertz() }; + let hclk = unwrap!(hclk, "SMA requires HCLK to be enabled, but it was not."); + let hclk_mhz = hclk.0 / 1_000_000; + + // Set the MDC clock frequency in the range 1MHz - 2.5MHz + let clock_range = match hclk_mhz { + 0..=34 => 2, // Divide by 16 + 35..=59 => 3, // Divide by 26 + 60..=99 => 0, // Divide by 42 + 100..=149 => 1, // Divide by 62 + 150..=249 => 4, // Divide by 102 + 250..=310 => 5, // Divide by 124 + _ => { + panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider") + } + }; + + Self { + _peri: peri, + clock_range, + pins: [mdio.into(), mdc.into()], + } + } +} + +impl StationManagement for Sma<'_, T> { + fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 { + let (macmdioar, macmdiodr) = T::regs(); + + macmdioar.modify(|w| { + w.set_pa(phy_addr); + w.set_rda(reg); + w.set_goc(0b11); // read + w.set_cr(self.clock_range); + w.set_mb(true); + }); + + while macmdioar.read().mb() {} + + macmdiodr.read().md() + } + + fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) { + let (macmdioar, macmdiodr) = T::regs(); + + macmdiodr.write(|w| w.set_md(val)); + macmdioar.modify(|w| { + w.set_pa(phy_addr); + w.set_rda(reg); + w.set_goc(0b01); // write + w.set_cr(self.clock_range); + w.set_mb(true); + }); + + while macmdioar.read().mb() {} + } +} + +impl Drop for Sma<'_, T> { + fn drop(&mut self) { + self.pins.iter_mut().for_each(|p| p.set_as_disconnected()); + } +} diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs index 91daa9d0b..d448537c8 100644 --- a/embassy-stm32/src/eth/v1/mod.rs +++ b/embassy-stm32/src/eth/v1/mod.rs @@ -3,15 +3,16 @@ mod rx_desc; mod tx_desc; -use core::marker::PhantomData; use core::sync::atomic::{Ordering, fence}; use embassy_hal_internal::Peri; -use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf}; +use stm32_metapac::eth::vals::{Apcs, Dm, DmaomrSr, Fes, Ftf, Ifg, Pbl, Rsf, St, Tsf}; pub(crate) use self::rx_desc::{RDes, RDesRing}; pub(crate) use self::tx_desc::{TDes, TDesRing}; +use super::sma::Sma; use super::*; +use crate::eth::{MDCPin, MDIOPin}; #[cfg(eth_v1a)] use crate::gpio::Pull; use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed}; @@ -22,7 +23,6 @@ use crate::pac::AFIO; #[cfg(any(eth_v1b, eth_v1c))] use crate::pac::SYSCFG; use crate::pac::{ETH, RCC}; -use crate::rcc::SealedRccPeripheral; /// Interrupt handler. pub struct InterruptHandler {} @@ -53,7 +53,7 @@ pub struct Ethernet<'d, T: Instance, P: Phy> { pins: Pins<'d>, pub(crate) phy: P, - pub(crate) station_management: EthernetStationManagement<'d, T>, + pub(crate) station_management: Sma<'d, T>, pub(crate) mac_addr: [u8; 6], } @@ -149,11 +149,11 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> { #[cfg(eth_v1a)] { config_in_pins!(ref_clk, rx_d0, rx_d1); - config_af_pins!(mdio, mdc, tx_d0, tx_d1, tx_en); + config_af_pins!(tx_d0, tx_d1, tx_en); } #[cfg(any(eth_v1b, eth_v1c))] - config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en); + config_pins!(ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en); let pins = Pins::Rmii([ ref_clk.into(), @@ -168,7 +168,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> { Self::new_inner(queue, peri, irq, pins, mdio, mdc, phy, mac_addr) } - fn new_inner( + fn new_inner( queue: &'d mut PacketQueue, peri: Peri<'d, T>, _irq: impl interrupt::typelevel::Binding + 'd, @@ -226,31 +226,13 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> { // TODO MTU size setting not found for v1 ethernet, check if correct - let hclk = ::frequency(); - let hclk_mhz = hclk.0 / 1_000_000; - - // Set the MDC clock frequency in the range 1MHz - 2.5MHz - let clock_range = match hclk_mhz { - 0..=24 => panic!("Invalid HCLK frequency - should be at least 25 MHz."), - 25..=34 => Cr::CR_20_35, // Divide by 16 - 35..=59 => Cr::CR_35_60, // Divide by 26 - 60..=99 => Cr::CR_60_100, // Divide by 42 - 100..=149 => Cr::CR_100_150, // Divide by 62 - 150..=216 => Cr::CR_150_168, // Divide by 102 - _ => { - panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider") - } - }; + let sma_peri = unsafe { peri.clone_unchecked() }; let mut this = Self { _peri: peri, pins, phy: phy, - station_management: EthernetStationManagement { - peri: PhantomData, - clock_range: clock_range, - pins: [mdio.into(), mdc.into()], - }, + station_management: Sma::new(sma_peri, mdio, mdc), mac_addr, tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf), rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf), @@ -347,12 +329,12 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> { #[cfg(eth_v1a)] { config_in_pins!(rx_clk, tx_clk, rx_d0, rx_d1, rx_d2, rx_d3, rxdv); - config_af_pins!(mdio, mdc, tx_d0, tx_d1, tx_d2, tx_d3, tx_en); + config_af_pins!(tx_d0, tx_d1, tx_d2, tx_d3, tx_en); } #[cfg(any(eth_v1b, eth_v1c))] config_pins!( - rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en + rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en ); let pins = Pins::Mii([ @@ -374,49 +356,6 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> { } } -/// Ethernet station management interface. -pub(crate) struct EthernetStationManagement<'d, T: Instance> { - peri: PhantomData, - clock_range: Cr, - pins: [Peri<'d, AnyPin>; 2], -} - -impl StationManagement for EthernetStationManagement<'_, T> { - fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 { - let (macmiiar, macmiidr) = { - let regs = T::regs().ethernet_mac(); - (regs.macmiiar(), regs.macmiidr()) - }; - - macmiiar.modify(|w| { - w.set_pa(phy_addr); - w.set_mr(reg); - w.set_mw(Mw::READ); // read operation - w.set_cr(self.clock_range); - w.set_mb(MbProgress::BUSY); // indicate that operation is in progress - }); - while macmiiar.read().mb() == MbProgress::BUSY {} - macmiidr.read().md() - } - - fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) { - let (macmiiar, macmiidr) = { - let regs = T::regs().ethernet_mac(); - (regs.macmiiar(), regs.macmiidr()) - }; - - macmiidr.write(|w| w.set_md(val)); - macmiiar.modify(|w| { - w.set_pa(phy_addr); - w.set_mr(reg); - w.set_mw(Mw::WRITE); // write - w.set_cr(self.clock_range); - w.set_mb(MbProgress::BUSY); - }); - while macmiiar.read().mb() == MbProgress::BUSY {} - } -} - impl<'d, T: Instance, P: Phy> Drop for Ethernet<'d, T, P> { fn drop(&mut self) { let dma = T::regs().ethernet_dma(); @@ -443,9 +382,3 @@ impl<'d, T: Instance, P: Phy> Drop for Ethernet<'d, T, P> { }) } } - -impl Drop for EthernetStationManagement<'_, T> { - fn drop(&mut self) { - self.pins.iter_mut().for_each(|p| p.set_as_disconnected()); - } -} diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs index 61dea6f3f..0db335a7c 100644 --- a/embassy-stm32/src/eth/v2/mod.rs +++ b/embassy-stm32/src/eth/v2/mod.rs @@ -1,18 +1,18 @@ mod descriptors; -use core::marker::PhantomData; use core::sync::atomic::{Ordering, fence}; use embassy_hal_internal::Peri; use stm32_metapac::syscfg::vals::EthSelPhy; pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing}; +use super::sma::Sma; use super::*; +use crate::eth::{MDCPin, MDIOPin}; use crate::gpio::{AfType, AnyPin, OutputType, SealedPin as _, Speed}; use crate::interrupt; use crate::interrupt::InterruptExt; use crate::pac::ETH; -use crate::rcc::SealedRccPeripheral; /// Interrupt handler. pub struct InterruptHandler {} @@ -42,7 +42,7 @@ pub struct Ethernet<'d, T: Instance, P: Phy> { pub(crate) rx: RDesRing<'d>, pins: Pins<'d>, pub(crate) phy: P, - pub(crate) station_management: EthernetStationManagement<'d, T>, + pub(crate) station_management: Sma<'d, T>, pub(crate) mac_addr: [u8; 6], } @@ -92,7 +92,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> { crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(EthSelPhy::RMII)); }); - config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en); + config_pins!(ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en); let pins = Pins::Rmii([ ref_clk.into(), @@ -143,7 +143,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> { }); config_pins!( - rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en + rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en ); let pins = Pins::Mii([ @@ -235,21 +235,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> { w.set_rbsz(RX_BUFFER_SIZE as u16); }); - let hclk = ::frequency(); - let hclk_mhz = hclk.0 / 1_000_000; - - // Set the MDC clock frequency in the range 1MHz - 2.5MHz - let clock_range = match hclk_mhz { - 0..=34 => 2, // Divide by 16 - 35..=59 => 3, // Divide by 26 - 60..=99 => 0, // Divide by 42 - 100..=149 => 1, // Divide by 62 - 150..=249 => 4, // Divide by 102 - 250..=310 => 5, // Divide by 124 - _ => { - panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider") - } - }; + let sma_peri = unsafe { peri.clone_unchecked() }; let mut this = Self { _peri: peri, @@ -257,11 +243,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> { rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf), pins, phy, - station_management: EthernetStationManagement { - peri: PhantomData, - clock_range: clock_range, - pins: [mdio.into(), mdc.into()], - }, + station_management: Sma::new(sma_peri, mdio, mdc), mac_addr, }; @@ -297,49 +279,6 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> { } } -/// Ethernet SMI driver. -pub struct EthernetStationManagement<'d, T: Instance> { - peri: PhantomData, - clock_range: u8, - pins: [Peri<'d, AnyPin>; 2], -} - -impl StationManagement for EthernetStationManagement<'_, T> { - fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 { - let (macmdioar, macmdiodr) = { - let regs = T::regs().ethernet_mac(); - (regs.macmdioar(), regs.macmdiodr()) - }; - - macmdioar.modify(|w| { - w.set_pa(phy_addr); - w.set_rda(reg); - w.set_goc(0b11); // read - w.set_cr(self.clock_range); - w.set_mb(true); - }); - while macmdioar.read().mb() {} - macmdiodr.read().md() - } - - fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) { - let (macmdioar, macmdiodr) = { - let regs = T::regs().ethernet_mac(); - (regs.macmdioar(), regs.macmdiodr()) - }; - - macmdiodr.write(|w| w.set_md(val)); - macmdioar.modify(|w| { - w.set_pa(phy_addr); - w.set_rda(reg); - w.set_goc(0b01); // write - w.set_cr(self.clock_range); - w.set_mb(true); - }); - while macmdioar.read().mb() {} - } -} - impl<'d, T: Instance, P: Phy> Drop for Ethernet<'d, T, P> { fn drop(&mut self) { let dma = T::regs().ethernet_dma(); @@ -376,9 +315,3 @@ impl<'d, T: Instance, P: Phy> Drop for Ethernet<'d, T, P> { }) } } - -impl Drop for EthernetStationManagement<'_, T> { - fn drop(&mut self) { - self.pins.iter_mut().for_each(|p| p.set_as_disconnected()); - } -} -- cgit