From a912a3798d5321d099765df4e1af16158699c8d5 Mon Sep 17 00:00:00 2001
From: Benjamin <benny_schlegel@hotmail.com>
Date: Tue, 3 Jun 2025 21:04:41 +0200
Subject: Fixed variations in register access for different families

---
 embassy-stm32/src/adc/v3.rs | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index f561f817c..c032113d5 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -247,9 +247,14 @@ impl<'d, T: Instance> Adc<'d, T> {
             Averaging::Samples128 => (true, 6, 7),
             Averaging::Samples256 => (true, 7, 8),
         };
-
         T::regs().cfgr2().modify(|reg| {
+            #[cfg(not(adc_g0))]
             reg.set_rovse(enable);
+            #[cfg(adc_g0)]
+            reg.set_ovse(enable);
+            #[cfg(any(adc_h5, adc_h7rs))]
+            reg.set_ovsr(samples.into());
+            #[cfg(not(any(adc_h5, adc_h7rs)))]
             reg.set_ovsr(samples);
             reg.set_ovss(right_shift);
         })
-- 
cgit