From a7e1bf2aff94ed0dd3d56848ccb9afe7a127054e Mon Sep 17 00:00:00 2001 From: Brian Schwind Date: Fri, 12 Sep 2025 20:02:08 +0900 Subject: Typo fixes --- embassy-stm32/src/ospi/mod.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/embassy-stm32/src/ospi/mod.rs b/embassy-stm32/src/ospi/mod.rs index 8384f4fc4..4df3b0042 100644 --- a/embassy-stm32/src/ospi/mod.rs +++ b/embassy-stm32/src/ospi/mod.rs @@ -113,7 +113,7 @@ pub struct TransferConfig { /// Data width (DMODE) pub dwidth: OspiWidth, - /// Data buffer + /// Data Double Transfer rate enable pub ddtr: bool, /// Number of dummy cycles (DCYC) @@ -467,11 +467,11 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> { if let Some(data_length) = data_len { T::REGS.dlr().write(|v| { v.set_dl((data_length - 1) as u32); - }) + }); } else { T::REGS.dlr().write(|v| { v.set_dl((0) as u32); - }) + }); } // Configure instruction/address/data/communication modes @@ -491,7 +491,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> { w.set_sioo(command.sioo); }); - // Set informationrequired to initiate transaction + // Set information required to initiate transaction if let Some(instruction) = command.instruction { if let Some(address) = command.address { T::REGS.ir().write(|v| { -- cgit From 9c4df75940023456e92623700a9bb25fe6600196 Mon Sep 17 00:00:00 2001 From: Brian Schwind Date: Fri, 12 Sep 2025 20:02:33 +0900 Subject: Set the alternate bytes register to the correct value when configuring an Ospi command --- embassy-stm32/src/ospi/mod.rs | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/embassy-stm32/src/ospi/mod.rs b/embassy-stm32/src/ospi/mod.rs index 4df3b0042..cbd6c8d35 100644 --- a/embassy-stm32/src/ospi/mod.rs +++ b/embassy-stm32/src/ospi/mod.rs @@ -451,11 +451,6 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> { // Configure alternate bytes if let Some(ab) = command.alternate_bytes { T::REGS.abr().write(|v| v.set_alternate(ab)); - T::REGS.ccr().modify(|w| { - w.set_abmode(PhaseMode::from_bits(command.abwidth.into())); - w.set_abdtr(command.abdtr); - w.set_absize(SizeInBits::from_bits(command.absize.into())); - }) } // Configure dummy cycles @@ -474,7 +469,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> { }); } - // Configure instruction/address/data/communication modes + // Configure instruction/address/alternate bytes/data/communication modes T::REGS.ccr().modify(|w| { w.set_imode(PhaseMode::from_bits(command.iwidth.into())); w.set_idtr(command.idtr); @@ -484,6 +479,10 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> { w.set_addtr(command.addtr); w.set_adsize(SizeInBits::from_bits(command.adsize.into())); + w.set_abmode(PhaseMode::from_bits(command.abwidth.into())); + w.set_abdtr(command.abdtr); + w.set_absize(SizeInBits::from_bits(command.absize.into())); + w.set_dmode(PhaseMode::from_bits(command.dwidth.into())); w.set_ddtr(command.ddtr); -- cgit From 4a3e9e38e5fd0f5f2f576691154ecbbdc22eabab Mon Sep 17 00:00:00 2001 From: Brian Schwind Date: Sat, 13 Sep 2025 00:12:14 +0900 Subject: Apply fixes to HSPI as well --- embassy-stm32/src/hspi/mod.rs | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/embassy-stm32/src/hspi/mod.rs b/embassy-stm32/src/hspi/mod.rs index 62bc0e979..3b73062a2 100644 --- a/embassy-stm32/src/hspi/mod.rs +++ b/embassy-stm32/src/hspi/mod.rs @@ -116,7 +116,7 @@ pub struct TransferConfig { /// Data width (DMODE) pub dwidth: HspiWidth, - /// Data buffer + /// Data Double Transfer rate enable pub ddtr: bool, /// Number of dummy cycles (DCYC) @@ -395,11 +395,6 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> { // Configure alternate bytes if let Some(ab) = command.alternate_bytes { T::REGS.abr().write(|v| v.set_alternate(ab)); - T::REGS.ccr().modify(|w| { - w.set_abmode(command.abwidth.into()); - w.set_abdtr(command.abdtr); - w.set_absize(command.absize.into()); - }) } // Configure dummy cycles @@ -411,14 +406,14 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> { if let Some(data_length) = data_len { T::REGS.dlr().write(|v| { v.set_dl((data_length - 1) as u32); - }) + }); } else { T::REGS.dlr().write(|v| { v.set_dl((0) as u32); - }) + }); } - // Configure instruction/address/data modes + // Configure instruction/address/alternate bytes/data modes T::REGS.ccr().modify(|w| { w.set_imode(command.iwidth.into()); w.set_idtr(command.idtr); @@ -428,6 +423,10 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> { w.set_addtr(command.addtr); w.set_adsize(command.adsize.into()); + w.set_abmode(command.abwidth.into()); + w.set_abdtr(command.abdtr); + w.set_absize(command.absize.into()); + w.set_dmode(command.dwidth.into()); w.set_ddtr(command.ddtr); }); -- cgit From 881fee982005b36a73c3b09b69bda48f81603084 Mon Sep 17 00:00:00 2001 From: Brian Schwind Date: Sat, 13 Sep 2025 00:12:36 +0900 Subject: Apply fixes to XSPI as well --- embassy-stm32/src/xspi/mod.rs | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/embassy-stm32/src/xspi/mod.rs b/embassy-stm32/src/xspi/mod.rs index 60ccf3c97..5ae074a90 100644 --- a/embassy-stm32/src/xspi/mod.rs +++ b/embassy-stm32/src/xspi/mod.rs @@ -110,7 +110,7 @@ pub struct TransferConfig { /// Data width (DMODE) pub dwidth: XspiWidth, - /// Data buffer + /// Data Double Transfer rate enable pub ddtr: bool, /// Number of dummy cycles (DCYC) @@ -424,11 +424,6 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> { // Configure alternate bytes if let Some(ab) = command.alternate_bytes { T::REGS.abr().write(|v| v.set_alternate(ab)); - T::REGS.ccr().modify(|w| { - w.set_abmode(CcrAbmode::from_bits(command.abwidth.into())); - w.set_abdtr(command.abdtr); - w.set_absize(CcrAbsize::from_bits(command.absize.into())); - }) } else { T::REGS.ccr().modify(|w| { // disable alternate bytes @@ -445,14 +440,14 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> { if let Some(data_length) = data_len { T::REGS.dlr().write(|v| { v.set_dl((data_length - 1) as u32); - }) + }); } else { T::REGS.dlr().write(|v| { v.set_dl((0) as u32); - }) + }); } - // Configure instruction/address/data modes + // Configure instruction/address/alternate bytes/data modes T::REGS.ccr().modify(|w| { w.set_imode(CcrImode::from_bits(command.iwidth.into())); w.set_idtr(command.idtr); @@ -462,6 +457,10 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> { w.set_addtr(command.addtr); w.set_adsize(CcrAdsize::from_bits(command.adsize.into())); + w.set_abmode(CcrAbmode::from_bits(command.abwidth.into())); + w.set_abdtr(command.abdtr); + w.set_absize(CcrAbsize::from_bits(command.absize.into())); + w.set_dmode(CcrDmode::from_bits(command.dwidth.into())); w.set_ddtr(command.ddtr); }); -- cgit From ffe7f6b0a06bda06ab7bde395f6f74a56be8dbf4 Mon Sep 17 00:00:00 2001 From: Brian Schwind Date: Sat, 13 Sep 2025 00:27:30 +0900 Subject: Update embassy-stm32/CHANGELOG.md --- embassy-stm32/CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md index 4ea11b664..93a1f4f64 100644 --- a/embassy-stm32/CHANGELOG.md +++ b/embassy-stm32/CHANGELOG.md @@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - fix: STM32: Prevent dropped DacChannel from disabling Dac peripheral if another DacChannel is still in scope ([#4577](https://github.com/embassy-rs/embassy/pull/4577)) - feat: Added support for more OctoSPI configurations (e.g. APS6408 RAM) ([#4581](https://github.com/embassy-rs/embassy/pull/4581)) - fix: stm32/usart: fix bug with blocking flush in buffered uart ([#4648](https://github.com/embassy-rs/embassy/pull/4648)) +- fix: stm32/(ospi/hspi/xspi): Fix the alternate bytes register config sticking around for subsequent writes ## 0.4.0 - 2025-08-26 -- cgit