From dccf185e1489c0055fcacdea59ce7837cc4d076d Mon Sep 17 00:00:00 2001
From: "Andreas Lindahl Flåten (ALF)" <andreas.flaten@rvmsystems.com>
Date: Wed, 5 Nov 2025 16:47:09 +0100
Subject: Add c.rs flash for the stm32c0 family

This is basically a copy of the `g.rs` file, with multi bank support
removed (c0 is single bank only).
---
 embassy-stm32/src/flash/c.rs      | 122 ++++++++++++++++++++++++++++++++++++++
 embassy-stm32/src/flash/common.rs |   2 +-
 embassy-stm32/src/flash/mod.rs    |   3 +-
 3 files changed, 125 insertions(+), 2 deletions(-)
 create mode 100644 embassy-stm32/src/flash/c.rs

diff --git a/embassy-stm32/src/flash/c.rs b/embassy-stm32/src/flash/c.rs
new file mode 100644
index 000000000..af3d07ac6
--- /dev/null
+++ b/embassy-stm32/src/flash/c.rs
@@ -0,0 +1,122 @@
+use core::ptr::write_volatile;
+use core::sync::atomic::{Ordering, fence};
+
+use cortex_m::interrupt;
+
+use super::{FlashSector, WRITE_SIZE};
+use crate::flash::Error;
+use crate::pac;
+
+pub(crate) unsafe fn lock() {
+    pac::FLASH.cr().modify(|w| w.set_lock(true));
+}
+pub(crate) unsafe fn unlock() {
+    // Wait, while the memory interface is busy.
+    wait_busy();
+
+    // Unlock flash
+    if pac::FLASH.cr().read().lock() {
+        pac::FLASH.keyr().write_value(0x4567_0123);
+        pac::FLASH.keyr().write_value(0xCDEF_89AB);
+    }
+}
+
+pub(crate) unsafe fn enable_blocking_write() {
+    assert_eq!(0, WRITE_SIZE % 4);
+    pac::FLASH.cr().write(|w| w.set_pg(true));
+}
+
+pub(crate) unsafe fn disable_blocking_write() {
+    pac::FLASH.cr().write(|w| w.set_pg(false));
+}
+
+pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+    let mut address = start_address;
+    for val in buf.chunks(4) {
+        write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
+        address += val.len() as u32;
+
+        // prevents parallelism errors
+        fence(Ordering::SeqCst);
+    }
+
+    wait_ready_blocking()
+}
+
+pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
+    let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
+
+    #[cfg(feature = "defmt")]
+    defmt::trace!("STM32C0 Erase: addr=0x{:08x}, idx={}, erase_size={}", sector.start, idx, super::BANK1_REGION.erase_size);
+
+
+    wait_busy();
+    clear_all_err();
+
+    // Explicitly unlock before erase
+    unlock();
+
+    interrupt::free(|_| {
+        #[cfg(feature = "defmt")]
+        {
+            let cr_before = pac::FLASH.cr().read();
+            defmt::trace!("FLASH_CR before: 0x{:08x}", cr_before.0);
+        }
+
+        pac::FLASH.cr().modify(|w| {
+            w.set_per(true);
+            w.set_pnb(idx as u8);
+            w.set_strt(true);
+        });
+
+        #[cfg(feature = "defmt")]
+        {
+            let cr_after = pac::FLASH.cr().read();
+            defmt::trace!("FLASH_CR after: 0x{:08x}, PER={}, PNB={}, STRT={}",
+                         cr_after.0, cr_after.per(), cr_after.pnb(), cr_after.strt());
+        }
+    });
+
+    let ret: Result<(), Error> = wait_ready_blocking();
+
+    // Clear erase bit
+    pac::FLASH.cr().modify(|w| w.set_per(false));
+
+    // Explicitly lock after erase
+    lock();
+
+    // Extra wait to ensure operation completes
+    wait_busy();
+
+    ret
+}
+
+pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
+    while pac::FLASH.sr().read().bsy() {}
+
+    let sr = pac::FLASH.sr().read();
+
+    if sr.progerr() {
+        return Err(Error::Prog);
+    }
+
+    if sr.wrperr() {
+        return Err(Error::Protected);
+    }
+
+    if sr.pgaerr() {
+        return Err(Error::Unaligned);
+    }
+
+    Ok(())
+}
+
+pub(crate) unsafe fn clear_all_err() {
+    // read and write back the same value.
+    // This clears all "write 1 to clear" bits.
+    pac::FLASH.sr().modify(|_| {});
+}
+
+fn wait_busy() {
+    while pac::FLASH.sr().read().bsy() {}
+}
diff --git a/embassy-stm32/src/flash/common.rs b/embassy-stm32/src/flash/common.rs
index b595938a6..508bb2548 100644
--- a/embassy-stm32/src/flash/common.rs
+++ b/embassy-stm32/src/flash/common.rs
@@ -102,7 +102,7 @@ pub(super) unsafe fn blocking_write(
     }
 
     let mut address = base + offset;
-    trace!("Writing {} bytes at 0x{:x}", bytes.len(), address);
+    trace!("Writing {} bytes at 0x{:x} (base=0x{:x}, offset=0x{:x})", bytes.len(), address, base, offset);
 
     for chunk in bytes.chunks(WRITE_SIZE) {
         write_chunk(address, chunk)?;
diff --git a/embassy-stm32/src/flash/mod.rs b/embassy-stm32/src/flash/mod.rs
index 3e74d857a..39cd9b3a9 100644
--- a/embassy-stm32/src/flash/mod.rs
+++ b/embassy-stm32/src/flash/mod.rs
@@ -99,6 +99,7 @@ compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is
 #[cfg_attr(flash_f4, path = "f4.rs")]
 #[cfg_attr(flash_f7, path = "f7.rs")]
 #[cfg_attr(any(flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4), path = "g.rs")]
+#[cfg_attr(flash_c0, path = "c.rs")]
 #[cfg_attr(flash_h7, path = "h7.rs")]
 #[cfg_attr(flash_h7ab, path = "h7.rs")]
 #[cfg_attr(any(flash_u5, flash_wba), path = "u5.rs")]
@@ -108,7 +109,7 @@ compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is
 #[cfg_attr(
     not(any(
         flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb, flash_f0, flash_f1, flash_f2, flash_f3, flash_f4,
-        flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5,
+        flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_c0, flash_h7, flash_h7ab, flash_u5,
         flash_wba, flash_h50, flash_u0, flash_h5,
     )),
     path = "other.rs"
-- 
cgit