From e4cb80be7cc74203259dbb82092f83a154bcd8a2 Mon Sep 17 00:00:00 2001 From: Rick Rogers Date: Thu, 24 Jul 2025 15:12:12 -0400 Subject: add pll divs/t for h7rs --- embassy-stm32/src/rcc/h.rs | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs index 383f48874..354824e26 100644 --- a/embassy-stm32/src/rcc/h.rs +++ b/embassy-stm32/src/rcc/h.rs @@ -8,6 +8,9 @@ use crate::pac::rcc::vals::{Pllrge, Pllvcosel, Timpre}; use crate::pac::{FLASH, PWR, RCC}; use crate::time::Hertz; +#[cfg(stm32h7rs)] +use stm32_metapac::rcc::vals::Plldivst; + /// HSI speed pub const HSI_FREQ: Hertz = Hertz(64_000_000); @@ -78,6 +81,12 @@ pub struct Pll { pub divq: Option, /// PLL R division factor. If None, PLL R output is disabled. pub divr: Option, + #[cfg(stm32h7rs)] + /// PLL S division factor. If None, PLL S output is disabled. + pub divs: Option, + #[cfg(stm32h7rs)] + /// PLL T division factor. If None, PLL T output is disabled. + pub divt: Option, } fn apb_div_tim(apb: &APBPrescaler, clk: Hertz, tim: TimerPrescaler) -> Hertz { -- cgit From 24b2794931e73325ad969d83453d0cf872ac4775 Mon Sep 17 00:00:00 2001 From: Rick Rogers Date: Thu, 24 Jul 2025 21:09:24 -0400 Subject: add plls/t to stm32h7rs examples --- examples/stm32h7rs/src/bin/blinky.rs | 2 ++ examples/stm32h7rs/src/bin/eth.rs | 2 ++ examples/stm32h7rs/src/bin/usb_serial.rs | 2 ++ examples/stm32h7rs/src/bin/xspi_memory_mapped.rs | 2 ++ 4 files changed, 8 insertions(+) diff --git a/examples/stm32h7rs/src/bin/blinky.rs b/examples/stm32h7rs/src/bin/blinky.rs index 137c585b7..5fd50fb15 100644 --- a/examples/stm32h7rs/src/bin/blinky.rs +++ b/examples/stm32h7rs/src/bin/blinky.rs @@ -25,6 +25,8 @@ async fn main(_spawner: Spawner) { divp: Some(PllDiv::DIV2), divq: None, divr: None, + divs: None, + divt: None, }); config.rcc.sys = Sysclk::PLL1_P; // 600 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 Mhz diff --git a/examples/stm32h7rs/src/bin/eth.rs b/examples/stm32h7rs/src/bin/eth.rs index 6d246bb09..d8002e9ba 100644 --- a/examples/stm32h7rs/src/bin/eth.rs +++ b/examples/stm32h7rs/src/bin/eth.rs @@ -41,6 +41,8 @@ async fn main(spawner: Spawner) -> ! { divp: Some(PllDiv::DIV2), divq: None, divr: None, + divs: None, + divt: None, }); config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz diff --git a/examples/stm32h7rs/src/bin/usb_serial.rs b/examples/stm32h7rs/src/bin/usb_serial.rs index 56a9884af..23abc3e2f 100644 --- a/examples/stm32h7rs/src/bin/usb_serial.rs +++ b/examples/stm32h7rs/src/bin/usb_serial.rs @@ -40,6 +40,8 @@ async fn main(_spawner: Spawner) { divp: Some(PllDiv::DIV1), //600 MHz divq: Some(PllDiv::DIV2), // 300 MHz divr: Some(PllDiv::DIV2), // 300 MHz + divs: None, + divt: None, }); config.rcc.sys = Sysclk::PLL1_P; // 600 MHz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 MHz diff --git a/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs b/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs index 59045ca2e..4c1b450b4 100644 --- a/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs +++ b/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs @@ -36,6 +36,8 @@ async fn main(_spawner: Spawner) { divp: Some(PllDiv::DIV2), divq: None, divr: None, + divs: None, + divt: None, }); config.rcc.sys = Sysclk::PLL1_P; // 600 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 Mhz -- cgit From 3a30458b253083087b43b85c43cc8eaf10870414 Mon Sep 17 00:00:00 2001 From: Rick Rogers Date: Fri, 25 Jul 2025 12:10:17 -0400 Subject: address rustfmt ci check --- embassy-stm32/src/rcc/h.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs index 354824e26..c31b1bbd1 100644 --- a/embassy-stm32/src/rcc/h.rs +++ b/embassy-stm32/src/rcc/h.rs @@ -1,5 +1,8 @@ use core::ops::RangeInclusive; +#[cfg(stm32h7rs)] +use stm32_metapac::rcc::vals::Plldivst; + use crate::pac; pub use crate::pac::rcc::vals::{ Hsidiv as HSIPrescaler, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul, Pllsrc as PllSource, Sw as Sysclk, @@ -8,9 +11,6 @@ use crate::pac::rcc::vals::{Pllrge, Pllvcosel, Timpre}; use crate::pac::{FLASH, PWR, RCC}; use crate::time::Hertz; -#[cfg(stm32h7rs)] -use stm32_metapac::rcc::vals::Plldivst; - /// HSI speed pub const HSI_FREQ: Hertz = Hertz(64_000_000); -- cgit From c37fb51cfe25511b2222e92e37b80933079ed3fc Mon Sep 17 00:00:00 2001 From: Rick Rogers Date: Fri, 25 Jul 2025 12:24:54 -0400 Subject: address ci test failure --- tests/stm32/src/common.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs index a4d8048ce..cb63b3374 100644 --- a/tests/stm32/src/common.rs +++ b/tests/stm32/src/common.rs @@ -681,6 +681,8 @@ pub fn config() -> Config { divp: Some(PllDiv::DIV2), // 600Mhz divq: Some(PllDiv::DIV25), // 48Mhz divr: None, + divs: None, + divt: None, }); config.rcc.sys = Sysclk::PLL1_P; // 600 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 Mhz -- cgit From a5a9c02543fbe978c68a707654029552f6b7b00a Mon Sep 17 00:00:00 2001 From: Rick Rogers Date: Fri, 25 Jul 2025 15:03:37 -0400 Subject: include proper pll divs/divt initialization --- embassy-stm32/build.rs | 2 +- embassy-stm32/src/rcc/h.rs | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs index 73860c64a..753f94fa6 100644 --- a/embassy-stm32/build.rs +++ b/embassy-stm32/build.rs @@ -1599,7 +1599,7 @@ fn main() { for e in rcc_registers.ir.enums { fn is_rcc_name(e: &str) -> bool { match e { - "Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" => true, + "Pllp" | "Pllq" | "Pllr" | "Plldivst" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" => true, "Timpre" | "Pllrclkpre" => false, e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true, _ => false, diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs index c31b1bbd1..837210b6a 100644 --- a/embassy-stm32/src/rcc/h.rs +++ b/embassy-stm32/src/rcc/h.rs @@ -758,6 +758,12 @@ struct PllOutput { q: Option, #[allow(dead_code)] r: Option, + #[cfg(stm32h7rs)] + #[allow(dead_code)] + s: Option, + #[cfg(stm32h7rs)] + #[allow(dead_code)] + t: Option, } fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { @@ -776,6 +782,10 @@ fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { p: None, q: None, r: None, + #[cfg(stm32h7rs)] + s: None, + #[cfg(stm32h7rs)] + t: None, }; }; @@ -823,6 +833,10 @@ fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { }); let q = config.divq.map(|div| vco_clk / div); let r = config.divr.map(|div| vco_clk / div); + #[cfg(stm32h7rs)] + let s = config.divs.map(|div| vco_clk / div); + #[cfg(stm32h7rs)] + let t = config.divt.map(|div| vco_clk / div); #[cfg(stm32h5)] RCC.pllcfgr(num).write(|w| { @@ -849,6 +863,10 @@ fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { w.set_divpen(num, p.is_some()); w.set_divqen(num, q.is_some()); w.set_divren(num, r.is_some()); + #[cfg(stm32h7rs)] + w.set_divsen(num, s.is_some()); + #[cfg(stm32h7rs)] + w.set_divten(num, t.is_some()); }); } @@ -859,10 +877,24 @@ fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { w.set_pllr(config.divr.unwrap_or(PllDiv::DIV2)); }); + #[cfg(stm32h7rs)] + RCC.plldivr2(num).write(|w| { + w.set_plls(config.divs.unwrap_or(Plldivst::DIV2)); + w.set_pllt(config.divt.unwrap_or(Plldivst::DIV2)); + }); + RCC.cr().modify(|w| w.set_pllon(num, true)); while !RCC.cr().read().pllrdy(num) {} - PllOutput { p, q, r } + PllOutput { + p, + q, + r, + #[cfg(stm32h7rs)] + s, + #[cfg(stm32h7rs)] + t, + } } fn flash_setup(clk: Hertz, vos: VoltageScale) { -- cgit