From a101d9078deb3ad576a40b6d5f4d6e81dcfd528e Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Tue, 4 Jul 2023 19:53:06 +0200 Subject: update embedded-hal crates. --- embassy-embedded-hal/src/adapter/blocking_async.rs | 43 +++---- embassy-embedded-hal/src/adapter/yielding_async.rs | 39 ++----- embassy-embedded-hal/src/shared_bus/asynch/spi.rs | 126 ++------------------- .../src/shared_bus/blocking/spi.rs | 120 +++----------------- embassy-embedded-hal/src/shared_bus/mod.rs | 4 + 5 files changed, 56 insertions(+), 276 deletions(-) (limited to 'embassy-embedded-hal/src') diff --git a/embassy-embedded-hal/src/adapter/blocking_async.rs b/embassy-embedded-hal/src/adapter/blocking_async.rs index b996d6a75..98ae2b02c 100644 --- a/embassy-embedded-hal/src/adapter/blocking_async.rs +++ b/embassy-embedded-hal/src/adapter/blocking_async.rs @@ -74,47 +74,30 @@ where E: embedded_hal_1::spi::Error + 'static, T: blocking::spi::Transfer + blocking::spi::Write, { - async fn transfer<'a>(&'a mut self, read: &'a mut [u8], write: &'a [u8]) -> Result<(), Self::Error> { - // Ensure we write the expected bytes - for i in 0..core::cmp::min(read.len(), write.len()) { - read[i] = write[i].clone(); - } - self.wrapped.transfer(read)?; + async fn flush(&mut self) -> Result<(), Self::Error> { Ok(()) } - async fn transfer_in_place<'a>(&'a mut self, _: &'a mut [u8]) -> Result<(), Self::Error> { - todo!() + async fn write(&mut self, data: &[u8]) -> Result<(), Self::Error> { + self.wrapped.write(data)?; + Ok(()) } -} -impl embedded_hal_async::spi::SpiBusFlush for BlockingAsync -where - E: embedded_hal_1::spi::Error + 'static, - T: blocking::spi::Transfer + blocking::spi::Write, -{ - async fn flush(&mut self) -> Result<(), Self::Error> { + async fn read(&mut self, data: &mut [u8]) -> Result<(), Self::Error> { + self.wrapped.transfer(data)?; Ok(()) } -} -impl embedded_hal_async::spi::SpiBusWrite for BlockingAsync -where - E: embedded_hal_1::spi::Error + 'static, - T: blocking::spi::Transfer + blocking::spi::Write, -{ - async fn write(&mut self, data: &[u8]) -> Result<(), Self::Error> { - self.wrapped.write(data)?; + async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> { + // Ensure we write the expected bytes + for i in 0..core::cmp::min(read.len(), write.len()) { + read[i] = write[i].clone(); + } + self.wrapped.transfer(read)?; Ok(()) } -} -impl embedded_hal_async::spi::SpiBusRead for BlockingAsync -where - E: embedded_hal_1::spi::Error + 'static, - T: blocking::spi::Transfer + blocking::spi::Write, -{ - async fn read(&mut self, data: &mut [u8]) -> Result<(), Self::Error> { + async fn transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Self::Error> { self.wrapped.transfer(data)?; Ok(()) } diff --git a/embassy-embedded-hal/src/adapter/yielding_async.rs b/embassy-embedded-hal/src/adapter/yielding_async.rs index f51e4076f..fe9c9c341 100644 --- a/embassy-embedded-hal/src/adapter/yielding_async.rs +++ b/embassy-embedded-hal/src/adapter/yielding_async.rs @@ -69,51 +69,36 @@ where type Error = T::Error; } -impl embedded_hal_async::spi::SpiBus for YieldingAsync +impl embedded_hal_async::spi::SpiBus for YieldingAsync where - T: embedded_hal_async::spi::SpiBus, + T: embedded_hal_async::spi::SpiBus, { - async fn transfer<'a>(&'a mut self, read: &'a mut [u8], write: &'a [u8]) -> Result<(), Self::Error> { - self.wrapped.transfer(read, write).await?; + async fn flush(&mut self) -> Result<(), Self::Error> { + self.wrapped.flush().await?; yield_now().await; Ok(()) } - async fn transfer_in_place<'a>(&'a mut self, words: &'a mut [u8]) -> Result<(), Self::Error> { - self.wrapped.transfer_in_place(words).await?; + async fn write(&mut self, data: &[Word]) -> Result<(), Self::Error> { + self.wrapped.write(data).await?; yield_now().await; Ok(()) } -} -impl embedded_hal_async::spi::SpiBusFlush for YieldingAsync -where - T: embedded_hal_async::spi::SpiBusFlush, -{ - async fn flush(&mut self) -> Result<(), Self::Error> { - self.wrapped.flush().await?; + async fn read(&mut self, data: &mut [Word]) -> Result<(), Self::Error> { + self.wrapped.read(data).await?; yield_now().await; Ok(()) } -} -impl embedded_hal_async::spi::SpiBusWrite for YieldingAsync -where - T: embedded_hal_async::spi::SpiBusWrite, -{ - async fn write(&mut self, data: &[u8]) -> Result<(), Self::Error> { - self.wrapped.write(data).await?; + async fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> { + self.wrapped.transfer(read, write).await?; yield_now().await; Ok(()) } -} -impl embedded_hal_async::spi::SpiBusRead for YieldingAsync -where - T: embedded_hal_async::spi::SpiBusRead, -{ - async fn read(&mut self, data: &mut [u8]) -> Result<(), Self::Error> { - self.wrapped.read(data).await?; + async fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> { + self.wrapped.transfer_in_place(words).await?; yield_now().await; Ok(()) } diff --git a/embassy-embedded-hal/src/shared_bus/asynch/spi.rs b/embassy-embedded-hal/src/shared_bus/asynch/spi.rs index b5549a6cd..030392183 100644 --- a/embassy-embedded-hal/src/shared_bus/asynch/spi.rs +++ b/embassy-embedded-hal/src/shared_bus/asynch/spi.rs @@ -56,62 +56,6 @@ where type Error = SpiDeviceError; } -impl spi::SpiDeviceRead for SpiDevice<'_, M, BUS, CS> -where - M: RawMutex, - BUS: spi::SpiBusRead, - CS: OutputPin, -{ - async fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> { - let mut bus = self.bus.lock().await; - self.cs.set_low().map_err(SpiDeviceError::Cs)?; - - let op_res: Result<(), BUS::Error> = try { - for buf in operations { - bus.read(buf).await?; - } - }; - - // On failure, it's important to still flush and deassert CS. - let flush_res = bus.flush().await; - let cs_res = self.cs.set_high(); - - let op_res = op_res.map_err(SpiDeviceError::Spi)?; - flush_res.map_err(SpiDeviceError::Spi)?; - cs_res.map_err(SpiDeviceError::Cs)?; - - Ok(op_res) - } -} - -impl spi::SpiDeviceWrite for SpiDevice<'_, M, BUS, CS> -where - M: RawMutex, - BUS: spi::SpiBusWrite, - CS: OutputPin, -{ - async fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> { - let mut bus = self.bus.lock().await; - self.cs.set_low().map_err(SpiDeviceError::Cs)?; - - let op_res: Result<(), BUS::Error> = try { - for buf in operations { - bus.write(buf).await?; - } - }; - - // On failure, it's important to still flush and deassert CS. - let flush_res = bus.flush().await; - let cs_res = self.cs.set_high(); - - let op_res = op_res.map_err(SpiDeviceError::Spi)?; - flush_res.map_err(SpiDeviceError::Spi)?; - cs_res.map_err(SpiDeviceError::Cs)?; - - Ok(op_res) - } -} - impl spi::SpiDevice for SpiDevice<'_, M, BUS, CS> where M: RawMutex, @@ -129,6 +73,12 @@ where Operation::Write(buf) => bus.write(buf).await?, Operation::Transfer(read, write) => bus.transfer(read, write).await?, Operation::TransferInPlace(buf) => bus.transfer_in_place(buf).await?, + #[cfg(not(feature = "time"))] + Operation::DelayUs(_) => return Err(SpiDeviceError::DelayUsNotSupported), + #[cfg(feature = "time")] + Operation::DelayUs(us) => { + embassy_time::Timer::after(embassy_time::Duration::from_micros(*us as _)).await + } } } }; @@ -172,64 +122,6 @@ where type Error = SpiDeviceError; } -impl spi::SpiDeviceWrite for SpiDeviceWithConfig<'_, M, BUS, CS> -where - M: RawMutex, - BUS: spi::SpiBusWrite + SetConfig, - CS: OutputPin, -{ - async fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> { - let mut bus = self.bus.lock().await; - bus.set_config(&self.config); - self.cs.set_low().map_err(SpiDeviceError::Cs)?; - - let op_res: Result<(), BUS::Error> = try { - for buf in operations { - bus.write(buf).await?; - } - }; - - // On failure, it's important to still flush and deassert CS. - let flush_res = bus.flush().await; - let cs_res = self.cs.set_high(); - - let op_res = op_res.map_err(SpiDeviceError::Spi)?; - flush_res.map_err(SpiDeviceError::Spi)?; - cs_res.map_err(SpiDeviceError::Cs)?; - - Ok(op_res) - } -} - -impl spi::SpiDeviceRead for SpiDeviceWithConfig<'_, M, BUS, CS> -where - M: RawMutex, - BUS: spi::SpiBusRead + SetConfig, - CS: OutputPin, -{ - async fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> { - let mut bus = self.bus.lock().await; - bus.set_config(&self.config); - self.cs.set_low().map_err(SpiDeviceError::Cs)?; - - let op_res: Result<(), BUS::Error> = try { - for buf in operations { - bus.read(buf).await?; - } - }; - - // On failure, it's important to still flush and deassert CS. - let flush_res = bus.flush().await; - let cs_res = self.cs.set_high(); - - let op_res = op_res.map_err(SpiDeviceError::Spi)?; - flush_res.map_err(SpiDeviceError::Spi)?; - cs_res.map_err(SpiDeviceError::Cs)?; - - Ok(op_res) - } -} - impl spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS> where M: RawMutex, @@ -248,6 +140,12 @@ where Operation::Write(buf) => bus.write(buf).await?, Operation::Transfer(read, write) => bus.transfer(read, write).await?, Operation::TransferInPlace(buf) => bus.transfer_in_place(buf).await?, + #[cfg(not(feature = "time"))] + Operation::DelayUs(_) => return Err(SpiDeviceError::DelayUsNotSupported), + #[cfg(feature = "time")] + Operation::DelayUs(us) => { + embassy_time::Timer::after(embassy_time::Duration::from_micros(*us as _)).await + } } } }; diff --git a/embassy-embedded-hal/src/shared_bus/blocking/spi.rs b/embassy-embedded-hal/src/shared_bus/blocking/spi.rs index 22e013be9..6d03d6263 100644 --- a/embassy-embedded-hal/src/shared_bus/blocking/spi.rs +++ b/embassy-embedded-hal/src/shared_bus/blocking/spi.rs @@ -22,7 +22,7 @@ use core::cell::RefCell; use embassy_sync::blocking_mutex::raw::RawMutex; use embassy_sync::blocking_mutex::Mutex; use embedded_hal_1::digital::OutputPin; -use embedded_hal_1::spi::{self, Operation, SpiBus, SpiBusRead, SpiBusWrite}; +use embedded_hal_1::spi::{self, Operation, SpiBus}; use crate::shared_bus::SpiDeviceError; use crate::SetConfig; @@ -48,58 +48,6 @@ where type Error = SpiDeviceError; } -impl embedded_hal_1::spi::SpiDeviceRead for SpiDevice<'_, M, BUS, CS> -where - M: RawMutex, - BUS: SpiBusRead, - CS: OutputPin, -{ - fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> { - self.bus.lock(|bus| { - let mut bus = bus.borrow_mut(); - self.cs.set_low().map_err(SpiDeviceError::Cs)?; - - let op_res = operations.iter_mut().try_for_each(|buf| bus.read(buf)); - - // On failure, it's important to still flush and deassert CS. - let flush_res = bus.flush(); - let cs_res = self.cs.set_high(); - - let op_res = op_res.map_err(SpiDeviceError::Spi)?; - flush_res.map_err(SpiDeviceError::Spi)?; - cs_res.map_err(SpiDeviceError::Cs)?; - - Ok(op_res) - }) - } -} - -impl embedded_hal_1::spi::SpiDeviceWrite for SpiDevice<'_, M, BUS, CS> -where - M: RawMutex, - BUS: SpiBusWrite, - CS: OutputPin, -{ - fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> { - self.bus.lock(|bus| { - let mut bus = bus.borrow_mut(); - self.cs.set_low().map_err(SpiDeviceError::Cs)?; - - let op_res = operations.iter().try_for_each(|buf| bus.write(buf)); - - // On failure, it's important to still flush and deassert CS. - let flush_res = bus.flush(); - let cs_res = self.cs.set_high(); - - let op_res = op_res.map_err(SpiDeviceError::Spi)?; - flush_res.map_err(SpiDeviceError::Spi)?; - cs_res.map_err(SpiDeviceError::Cs)?; - - Ok(op_res) - }) - } -} - impl embedded_hal_1::spi::SpiDevice for SpiDevice<'_, M, BUS, CS> where M: RawMutex, @@ -116,6 +64,13 @@ where Operation::Write(buf) => bus.write(buf), Operation::Transfer(read, write) => bus.transfer(read, write), Operation::TransferInPlace(buf) => bus.transfer_in_place(buf), + #[cfg(not(feature = "time"))] + Operation::DelayUs(_) => Err(SpiDeviceError::DelayUsNotSupported), + #[cfg(feature = "time")] + Operation::DelayUs(us) => { + embassy_time::block_for(embassy_time::Duration::from_micros(*us as _)); + Ok(()) + } }); // On failure, it's important to still flush and deassert CS. @@ -199,58 +154,6 @@ where type Error = SpiDeviceError; } -impl embedded_hal_1::spi::SpiDeviceRead for SpiDeviceWithConfig<'_, M, BUS, CS> -where - M: RawMutex, - BUS: SpiBusRead + SetConfig, - CS: OutputPin, -{ - fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> { - self.bus.lock(|bus| { - let mut bus = bus.borrow_mut(); - bus.set_config(&self.config); - self.cs.set_low().map_err(SpiDeviceError::Cs)?; - - let op_res = operations.iter_mut().try_for_each(|buf| bus.read(buf)); - - // On failure, it's important to still flush and deassert CS. - let flush_res = bus.flush(); - let cs_res = self.cs.set_high(); - - let op_res = op_res.map_err(SpiDeviceError::Spi)?; - flush_res.map_err(SpiDeviceError::Spi)?; - cs_res.map_err(SpiDeviceError::Cs)?; - Ok(op_res) - }) - } -} - -impl embedded_hal_1::spi::SpiDeviceWrite for SpiDeviceWithConfig<'_, M, BUS, CS> -where - M: RawMutex, - BUS: SpiBusWrite + SetConfig, - CS: OutputPin, -{ - fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> { - self.bus.lock(|bus| { - let mut bus = bus.borrow_mut(); - bus.set_config(&self.config); - self.cs.set_low().map_err(SpiDeviceError::Cs)?; - - let op_res = operations.iter().try_for_each(|buf| bus.write(buf)); - - // On failure, it's important to still flush and deassert CS. - let flush_res = bus.flush(); - let cs_res = self.cs.set_high(); - - let op_res = op_res.map_err(SpiDeviceError::Spi)?; - flush_res.map_err(SpiDeviceError::Spi)?; - cs_res.map_err(SpiDeviceError::Cs)?; - Ok(op_res) - }) - } -} - impl embedded_hal_1::spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS> where M: RawMutex, @@ -268,6 +171,13 @@ where Operation::Write(buf) => bus.write(buf), Operation::Transfer(read, write) => bus.transfer(read, write), Operation::TransferInPlace(buf) => bus.transfer_in_place(buf), + #[cfg(not(feature = "time"))] + Operation::DelayUs(_) => Err(SpiDeviceError::DelayUsNotSupported), + #[cfg(feature = "time")] + Operation::DelayUs(us) => { + embassy_time::block_for(embassy_time::Duration::from_micros(*us as _)); + Ok(()) + } }); // On failure, it's important to still flush and deassert CS. diff --git a/embassy-embedded-hal/src/shared_bus/mod.rs b/embassy-embedded-hal/src/shared_bus/mod.rs index 617d921e9..79a90bd52 100644 --- a/embassy-embedded-hal/src/shared_bus/mod.rs +++ b/embassy-embedded-hal/src/shared_bus/mod.rs @@ -30,11 +30,14 @@ where /// Error returned by SPI device implementations in this crate. #[derive(Copy, Clone, Eq, PartialEq, Debug)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[non_exhaustive] pub enum SpiDeviceError { /// An operation on the inner SPI bus failed. Spi(BUS), /// Setting the value of the Chip Select (CS) pin failed. Cs(CS), + /// DelayUs operations are not supported when the `time` Cargo feature is not enabled. + DelayUsNotSupported, } impl spi::Error for SpiDeviceError @@ -46,6 +49,7 @@ where match self { Self::Spi(e) => e.kind(), Self::Cs(_) => spi::ErrorKind::Other, + Self::DelayUsNotSupported => spi::ErrorKind::Other, } } } -- cgit