From e282662f2408455d5f7e53c010c3bf0d8eeb99aa Mon Sep 17 00:00:00 2001 From: xoviat Date: Mon, 27 Oct 2025 21:10:19 -0500 Subject: timer: add output compare values --- embassy-stm32/src/timer/low_level.rs | 69 ++++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 10 deletions(-) (limited to 'embassy-stm32/src/timer') diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs index ac039bb0d..7c02e7e62 100644 --- a/embassy-stm32/src/timer/low_level.rs +++ b/embassy-stm32/src/timer/low_level.rs @@ -143,20 +143,69 @@ pub enum OutputCompareMode { /// TIMx_CNTTIMx_CCRx else inactive. PwmMode2, - // TODO: there's more modes here depending on the chip family. + + #[cfg(timer_v2)] + /// In up-counting mode, the channel is active until a trigger + /// event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM + /// mode 1 and the channels becomes active again at the next update. In down-counting + /// mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). + /// Then, a comparison is performed as in PWM mode 1 and the channels becomes + /// inactive again at the next update. + OnePulseMode1, + + #[cfg(timer_v2)] + /// In up-counting mode, the channel is inactive until a + /// trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in + /// PWM mode 2 and the channels becomes inactive again at the next update. In down + /// counting mode, the channel is active until a trigger event is detected (on tim_trgi + /// signal). Then, a comparison is performed as in PWM mode 1 and the channels + /// becomes active again at the next update. + OnePulseMode2, + + #[cfg(timer_v2)] + /// Combined PWM mode 1 - tim_oc1ref has the same behavior as in PWM mode 1. + /// tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref. + CombinedPwmMode1, + + #[cfg(timer_v2)] + /// Combined PWM mode 2 - tim_oc1ref has the same behavior as in PWM mode 2. + /// tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref. + CombinedPwmMode2, + + #[cfg(timer_v2)] + /// tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc outputs tim_oc1ref + /// when the counter is counting up, tim_oc2ref when it is counting down. + AsymmetricPwmMode1, + + #[cfg(timer_v2)] + /// tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc outputs tim_oc1ref + /// when the counter is counting up, tim_oc2ref when it is counting down. + AsymmetricPwmMode2, } -impl From for stm32_metapac::timer::vals::Ocm { +impl From for crate::pac::timer::vals::Ocm { fn from(mode: OutputCompareMode) -> Self { match mode { - OutputCompareMode::Frozen => stm32_metapac::timer::vals::Ocm::FROZEN, - OutputCompareMode::ActiveOnMatch => stm32_metapac::timer::vals::Ocm::ACTIVE_ON_MATCH, - OutputCompareMode::InactiveOnMatch => stm32_metapac::timer::vals::Ocm::INACTIVE_ON_MATCH, - OutputCompareMode::Toggle => stm32_metapac::timer::vals::Ocm::TOGGLE, - OutputCompareMode::ForceInactive => stm32_metapac::timer::vals::Ocm::FORCE_INACTIVE, - OutputCompareMode::ForceActive => stm32_metapac::timer::vals::Ocm::FORCE_ACTIVE, - OutputCompareMode::PwmMode1 => stm32_metapac::timer::vals::Ocm::PWM_MODE1, - OutputCompareMode::PwmMode2 => stm32_metapac::timer::vals::Ocm::PWM_MODE2, + OutputCompareMode::Frozen => crate::pac::timer::vals::Ocm::FROZEN, + OutputCompareMode::ActiveOnMatch => crate::pac::timer::vals::Ocm::ACTIVE_ON_MATCH, + OutputCompareMode::InactiveOnMatch => crate::pac::timer::vals::Ocm::INACTIVE_ON_MATCH, + OutputCompareMode::Toggle => crate::pac::timer::vals::Ocm::TOGGLE, + OutputCompareMode::ForceInactive => crate::pac::timer::vals::Ocm::FORCE_INACTIVE, + OutputCompareMode::ForceActive => crate::pac::timer::vals::Ocm::FORCE_ACTIVE, + OutputCompareMode::PwmMode1 => crate::pac::timer::vals::Ocm::PWM_MODE1, + OutputCompareMode::PwmMode2 => crate::pac::timer::vals::Ocm::PWM_MODE2, + #[cfg(timer_v2)] + OutputCompareMode::OnePulseMode1 => crate::pac::timer::vals::Ocm::RETRIGERRABLE_OPM_MODE_1, + #[cfg(timer_v2)] + OutputCompareMode::OnePulseMode2 => crate::pac::timer::vals::Ocm::RETRIGERRABLE_OPM_MODE_2, + #[cfg(timer_v2)] + OutputCompareMode::CombinedPwmMode1 => crate::pac::timer::vals::Ocm::COMBINED_PWM_MODE_1, + #[cfg(timer_v2)] + OutputCompareMode::CombinedPwmMode2 => crate::pac::timer::vals::Ocm::COMBINED_PWM_MODE_2, + #[cfg(timer_v2)] + OutputCompareMode::AsymmetricPwmMode1 => crate::pac::timer::vals::Ocm::ASYMMETRIC_PWM_MODE_1, + #[cfg(timer_v2)] + OutputCompareMode::AsymmetricPwmMode2 => crate::pac::timer::vals::Ocm::ASYMMETRIC_PWM_MODE_2, } } } -- cgit From a3ca44b2b4a41ef872f72477dd1f90aeb855a30d Mon Sep 17 00:00:00 2001 From: xoviat Date: Tue, 28 Oct 2025 12:54:33 -0500 Subject: timer/low_level: add ability to set master mode --- embassy-stm32/src/timer/low_level.rs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'embassy-stm32/src/timer') diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs index 7c02e7e62..82645887e 100644 --- a/embassy-stm32/src/timer/low_level.rs +++ b/embassy-stm32/src/timer/low_level.rs @@ -10,7 +10,7 @@ use core::mem::ManuallyDrop; use embassy_hal_internal::Peri; // Re-export useful enums -pub use stm32_metapac::timer::vals::{FilterValue, Sms as SlaveMode, Ts as TriggerSource}; +pub use stm32_metapac::timer::vals::{FilterValue, Mms as MasterMode, Sms as SlaveMode, Ts as TriggerSource}; use super::*; use crate::pac::timer::vals; @@ -689,6 +689,11 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> { self.regs_gp16().dier().modify(|w| w.set_ccde(channel.index(), ccde)) } + /// Set Timer Master Mode + pub fn set_master_mode(&self, mms: MasterMode) { + self.regs_gp16().cr2().modify(|w| w.set_mms(mms)); + } + /// Set Timer Slave Mode pub fn set_slave_mode(&self, sms: SlaveMode) { self.regs_gp16().smcr().modify(|r| r.set_sms(sms)); -- cgit From 488d06c0e9da673f770b41d8f79bf26227dc6d53 Mon Sep 17 00:00:00 2001 From: xoviat Date: Tue, 4 Nov 2025 12:26:37 -0600 Subject: stm32/stop: move stop_with_rtc into init --- embassy-stm32/src/timer/mod.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'embassy-stm32/src/timer') diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs index b09bc7166..804d1ef37 100644 --- a/embassy-stm32/src/timer/mod.rs +++ b/embassy-stm32/src/timer/mod.rs @@ -399,7 +399,7 @@ pub struct UpdateInterruptHandler { impl interrupt::typelevel::Handler for UpdateInterruptHandler { unsafe fn on_interrupt() { #[cfg(feature = "low-power")] - crate::low_power::on_wakeup_irq(); + crate::low_power::Executor::on_wakeup_irq(); let regs = crate::pac::timer::TimCore::from_ptr(T::regs()); @@ -429,7 +429,7 @@ impl interrupt::typelevel::Handler Date: Tue, 4 Nov 2025 19:55:09 +0100 Subject: Implement into_ring_buffered for g4. Add methods for configuring injected sampling for g4. --- embassy-stm32/src/timer/complementary_pwm.rs | 12 +++++++++++- embassy-stm32/src/timer/low_level.rs | 10 ++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) (limited to 'embassy-stm32/src/timer') diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs index 75a83629c..9a56a41fb 100644 --- a/embassy-stm32/src/timer/complementary_pwm.rs +++ b/embassy-stm32/src/timer/complementary_pwm.rs @@ -2,7 +2,7 @@ use core::marker::PhantomData; -pub use stm32_metapac::timer::vals::{Ckd, Ossi, Ossr}; +pub use stm32_metapac::timer::vals::{Ckd, Mms2, Ossi, Ossr}; use super::low_level::{CountingMode, OutputPolarity, Timer}; use super::simple_pwm::PwmPin; @@ -136,6 +136,16 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> { self.inner.get_moe() } + /// Set Master Slave Mode 2 + pub fn set_mms2(&mut self, mms2: Mms2) { + self.inner.set_mms2_selection(mms2); + } + + /// Set Repetition Counter + pub fn set_repetition_counter(&mut self, val: u16) { + self.inner.set_repetition_counter(val); + } + /// Enable the given channel. pub fn enable(&mut self, channel: Channel) { self.inner.enable_channel(channel, true); diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs index 82645887e..0122fe4f7 100644 --- a/embassy-stm32/src/timer/low_level.rs +++ b/embassy-stm32/src/timer/low_level.rs @@ -814,6 +814,16 @@ impl<'d, T: AdvancedInstance4Channel> Timer<'d, T> { self.regs_advanced().cr2().modify(|w| w.set_oisn(channel.index(), val)); } + /// Set master mode selection 2 + pub fn set_mms2_selection(&self, mms2: vals::Mms2) { + self.regs_advanced().cr2().modify(|w| w.set_mms2(mms2)); + } + + /// Set repetition counter + pub fn set_repetition_counter(&self, val: u16) { + self.regs_advanced().rcr().modify(|w| w.set_rep(val)); + } + /// Trigger software break 1 or 2 /// Setting this bit generates a break event. This bit is automatically cleared by the hardware. pub fn trigger_software_break(&self, n: usize) { -- cgit