From e282662f2408455d5f7e53c010c3bf0d8eeb99aa Mon Sep 17 00:00:00 2001
From: xoviat <xoviat@users.noreply.github.com>
Date: Mon, 27 Oct 2025 21:10:19 -0500
Subject: timer: add output compare values

---
 embassy-stm32/src/timer/low_level.rs | 69 ++++++++++++++++++++++++++++++------
 1 file changed, 59 insertions(+), 10 deletions(-)

(limited to 'embassy-stm32/src/timer')

diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index ac039bb0d..7c02e7e62 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -143,20 +143,69 @@ pub enum OutputCompareMode {
     /// TIMx_CNT<TIMx_CCRx else active. In downcounting, channel is active as long as
     /// TIMx_CNT>TIMx_CCRx else inactive.
     PwmMode2,
-    // TODO: there's more modes here depending on the chip family.
+
+    #[cfg(timer_v2)]
+    /// In up-counting mode, the channel is active until a trigger
+    /// event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM
+    /// mode 1 and the channels becomes active again at the next update. In down-counting
+    /// mode, the channel is inactive until a trigger event is detected (on tim_trgi signal).
+    /// Then, a comparison is performed as in PWM mode 1 and the channels becomes
+    /// inactive again at the next update.
+    OnePulseMode1,
+
+    #[cfg(timer_v2)]
+    /// In up-counting mode, the channel is inactive until a
+    /// trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in
+    /// PWM mode 2 and the channels becomes inactive again at the next update. In down
+    /// counting mode, the channel is active until a trigger event is detected (on tim_trgi
+    /// signal). Then, a comparison is performed as in PWM mode 1 and the channels
+    /// becomes active again at the next update.
+    OnePulseMode2,
+
+    #[cfg(timer_v2)]
+    /// Combined PWM mode 1 - tim_oc1ref has the same behavior as in PWM mode 1.
+    /// tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.
+    CombinedPwmMode1,
+
+    #[cfg(timer_v2)]
+    /// Combined PWM mode 2 - tim_oc1ref has the same behavior as in PWM mode 2.
+    /// tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.
+    CombinedPwmMode2,
+
+    #[cfg(timer_v2)]
+    /// tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc outputs tim_oc1ref
+    /// when the counter is counting up, tim_oc2ref when it is counting down.
+    AsymmetricPwmMode1,
+
+    #[cfg(timer_v2)]
+    /// tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc outputs tim_oc1ref
+    /// when the counter is counting up, tim_oc2ref when it is counting down.
+    AsymmetricPwmMode2,
 }
 
-impl From<OutputCompareMode> for stm32_metapac::timer::vals::Ocm {
+impl From<OutputCompareMode> for crate::pac::timer::vals::Ocm {
     fn from(mode: OutputCompareMode) -> Self {
         match mode {
-            OutputCompareMode::Frozen => stm32_metapac::timer::vals::Ocm::FROZEN,
-            OutputCompareMode::ActiveOnMatch => stm32_metapac::timer::vals::Ocm::ACTIVE_ON_MATCH,
-            OutputCompareMode::InactiveOnMatch => stm32_metapac::timer::vals::Ocm::INACTIVE_ON_MATCH,
-            OutputCompareMode::Toggle => stm32_metapac::timer::vals::Ocm::TOGGLE,
-            OutputCompareMode::ForceInactive => stm32_metapac::timer::vals::Ocm::FORCE_INACTIVE,
-            OutputCompareMode::ForceActive => stm32_metapac::timer::vals::Ocm::FORCE_ACTIVE,
-            OutputCompareMode::PwmMode1 => stm32_metapac::timer::vals::Ocm::PWM_MODE1,
-            OutputCompareMode::PwmMode2 => stm32_metapac::timer::vals::Ocm::PWM_MODE2,
+            OutputCompareMode::Frozen => crate::pac::timer::vals::Ocm::FROZEN,
+            OutputCompareMode::ActiveOnMatch => crate::pac::timer::vals::Ocm::ACTIVE_ON_MATCH,
+            OutputCompareMode::InactiveOnMatch => crate::pac::timer::vals::Ocm::INACTIVE_ON_MATCH,
+            OutputCompareMode::Toggle => crate::pac::timer::vals::Ocm::TOGGLE,
+            OutputCompareMode::ForceInactive => crate::pac::timer::vals::Ocm::FORCE_INACTIVE,
+            OutputCompareMode::ForceActive => crate::pac::timer::vals::Ocm::FORCE_ACTIVE,
+            OutputCompareMode::PwmMode1 => crate::pac::timer::vals::Ocm::PWM_MODE1,
+            OutputCompareMode::PwmMode2 => crate::pac::timer::vals::Ocm::PWM_MODE2,
+            #[cfg(timer_v2)]
+            OutputCompareMode::OnePulseMode1 => crate::pac::timer::vals::Ocm::RETRIGERRABLE_OPM_MODE_1,
+            #[cfg(timer_v2)]
+            OutputCompareMode::OnePulseMode2 => crate::pac::timer::vals::Ocm::RETRIGERRABLE_OPM_MODE_2,
+            #[cfg(timer_v2)]
+            OutputCompareMode::CombinedPwmMode1 => crate::pac::timer::vals::Ocm::COMBINED_PWM_MODE_1,
+            #[cfg(timer_v2)]
+            OutputCompareMode::CombinedPwmMode2 => crate::pac::timer::vals::Ocm::COMBINED_PWM_MODE_2,
+            #[cfg(timer_v2)]
+            OutputCompareMode::AsymmetricPwmMode1 => crate::pac::timer::vals::Ocm::ASYMMETRIC_PWM_MODE_1,
+            #[cfg(timer_v2)]
+            OutputCompareMode::AsymmetricPwmMode2 => crate::pac::timer::vals::Ocm::ASYMMETRIC_PWM_MODE_2,
         }
     }
 }
-- 
cgit