From e9783ee28e9bdd89ffaeffb24bbff207c1ceb837 Mon Sep 17 00:00:00 2001
From: elagil <elagil@takanome.de>
Date: Mon, 25 Aug 2025 21:10:59 +0200
Subject: fix: build

---
 embassy-stm32/src/usart/ringbuffered.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'embassy-stm32/src/usart')

diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index 8a607a31a..5f4e87834 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -83,7 +83,7 @@ pub struct RingBufferedUartRx<'d> {
     kernel_clock: Hertz,
     rx: Option<Peri<'d, AnyPin>>,
     rts: Option<Peri<'d, AnyPin>>,
-    ring_buf: ReadableRingBuffer<'d, u8, 2>,
+    ring_buf: ReadableRingBuffer<'d, u8>,
 }
 
 impl<'d> SetConfig for RingBufferedUartRx<'d> {
@@ -165,7 +165,7 @@ impl<'d> RingBufferedUartRx<'d> {
 
     /// Stop DMA backed UART receiver
     fn stop_uart(&mut self) {
-        self.ring_buf.request_suspend();
+        self.ring_buf.request_pause();
 
         let r = self.info.regs;
         // clear all interrupts and DMA Rx Request
-- 
cgit