From 73b1d46e2b7eacda184f1d63cd0fcedf990e5fda Mon Sep 17 00:00:00 2001 From: RaulIQ Date: Thu, 2 Oct 2025 16:13:03 +0300 Subject: fix: correct DMA configuration and registers in receive_waveform --- embassy-stm32/src/timer/input_capture.rs | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'embassy-stm32/src') diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs index cbb4bb1d4..d8dbdee66 100644 --- a/embassy-stm32/src/timer/input_capture.rs +++ b/embassy-stm32/src/timer/input_capture.rs @@ -165,10 +165,13 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> { let req = dma.request(); let original_enable_state = self.is_enabled(M::CHANNEL); - let original_update_dma_state = self.inner.get_update_dma_state(); + let original_cc_dma_enable_state = self.inner.get_cc_dma_enable_state(M::CHANNEL); - if !original_update_dma_state { - self.inner.enable_update_dma(true); + self.inner.set_input_ti_selection(M::CHANNEL, InputTISelection::Normal); + self.inner.set_input_capture_mode(M::CHANNEL, InputCaptureMode::BothEdges); + + if !original_cc_dma_enable_state { + self.inner.set_cc_dma_enable_state(M::CHANNEL, true); } if !original_enable_state { @@ -181,7 +184,7 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> { Transfer::new_read( dma, req, - self.inner.regs_1ch().ccr(M::CHANNEL.index()).as_ptr() as *mut u16, + self.inner.regs_gp16().ccr(M::CHANNEL.index()).as_ptr() as *mut u16, buf, TransferOptions::default(), ) -- cgit