From 120911fd7112196e37806b9abfd38c50f637917c Mon Sep 17 00:00:00 2001 From: goodhoko Date: Mon, 15 Dec 2025 16:59:28 +0100 Subject: Source system clock from MSIS before (de)configuring PLLs Fixes https://github.com/embassy-rs/embassy/issues/5072 --- embassy-stm32/CHANGELOG.md | 1 + embassy-stm32/src/rcc/u5.rs | 10 ++++++++++ 2 files changed, 11 insertions(+) (limited to 'embassy-stm32') diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md index 38f22b1c3..d26f1acdd 100644 --- a/embassy-stm32/CHANGELOG.md +++ b/embassy-stm32/CHANGELOG.md @@ -93,6 +93,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - stm32: Add blocking_listen for blocking I2C driver - fix: stm32l47*/stm32l48* adc analog pin setup - fix: keep stm32/sai: make NODIV independent of MCKDIV +- fix: Source system clock from MSIS before (de)configuring PLLs on STM32U5 ## 0.4.0 - 2025-08-26 diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs index 7b0dcb63f..47cc29c6f 100644 --- a/embassy-stm32/src/rcc/u5.rs +++ b/embassy-stm32/src/rcc/u5.rs @@ -343,6 +343,16 @@ pub(crate) unsafe fn init(config: Config) { let hsi48 = config.hsi48.map(super::init_hsi48); + // There's a possibility that a bootloader that ran before us has configured the system clock + // source to be PLL1_R. In that case we'd get forever stuck on (de)configuring PLL1 as the chip + // prohibits disabling PLL1 when it's used as a source for system clock. Change the system + // clock source to MSIS which doesn't suffer from this conflict. The correct source per the + // provided config is then set further down. + // See https://github.com/embassy-rs/embassy/issues/5072 + let default_system_clock_source = Config::default().sys; + RCC.cfgr1().modify(|w| w.set_sw(default_system_clock_source)); + while RCC.cfgr1().read().sws() != default_system_clock_source {} + let pll_input = PllInput { hse, hsi, msi: msis }; let pll1 = init_pll(PllInstance::Pll1, config.pll1, &pll_input, config.voltage_range); let pll2 = init_pll(PllInstance::Pll2, config.pll2, &pll_input, config.voltage_range); -- cgit