From 489d0be2a2971cfae7d6413b601bbd044d42e351 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 26 Feb 2024 00:00:17 +0100 Subject: stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`. --- embassy-stm32/src/rcc/c0.rs | 14 +++++++------- embassy-stm32/src/rcc/g0.rs | 16 ++++++++-------- embassy-stm32/src/rcc/l.rs | 26 +++++++++++++------------- embassy-stm32/src/rcc/u5.rs | 20 ++++++++++---------- embassy-stm32/src/rcc/wba.rs | 24 ++++++++++++------------ 5 files changed, 50 insertions(+), 50 deletions(-) (limited to 'embassy-stm32') diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs index ca1222185..ec6ec34e8 100644 --- a/embassy-stm32/src/rcc/c0.rs +++ b/embassy-stm32/src/rcc/c0.rs @@ -9,7 +9,7 @@ pub const HSI_FREQ: Hertz = Hertz(48_000_000); /// System clock mux source #[derive(Clone, Copy)] -pub enum ClockSrc { +pub enum Sysclk { HSE(Hertz), HSI(HSIPrescaler), LSI, @@ -17,7 +17,7 @@ pub enum ClockSrc { /// Clocks configutation pub struct Config { - pub mux: ClockSrc, + pub sys: Sysclk, pub ahb_pre: AHBPrescaler, pub apb_pre: APBPrescaler, pub ls: super::LsConfig, @@ -27,7 +27,7 @@ impl Default for Config { #[inline] fn default() -> Config { Config { - mux: ClockSrc::HSI(HSIPrescaler::DIV1), + sys: Sysclk::HSI(HSIPrescaler::DIV1), ahb_pre: AHBPrescaler::DIV1, apb_pre: APBPrescaler::DIV1, ls: Default::default(), @@ -36,8 +36,8 @@ impl Default for Config { } pub(crate) unsafe fn init(config: Config) { - let (sys_clk, sw) = match config.mux { - ClockSrc::HSI(div) => { + let (sys_clk, sw) = match config.sys { + Sysclk::HSI(div) => { // Enable HSI RCC.cr().write(|w| { w.set_hsidiv(div); @@ -47,14 +47,14 @@ pub(crate) unsafe fn init(config: Config) { (HSI_FREQ / div, Sw::HSI) } - ClockSrc::HSE(freq) => { + Sysclk::HSE(freq) => { // Enable HSE RCC.cr().write(|w| w.set_hseon(true)); while !RCC.cr().read().hserdy() {} (freq, Sw::HSE) } - ClockSrc::LSI => { + Sysclk::LSI => { // Enable LSI RCC.csr2().write(|w| w.set_lsion(true)); while !RCC.csr2().read().lsirdy() {} diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs index e3cd46fb9..0b1f34a20 100644 --- a/embassy-stm32/src/rcc/g0.rs +++ b/embassy-stm32/src/rcc/g0.rs @@ -19,7 +19,7 @@ pub enum HseMode { /// System clock mux source #[derive(Clone, Copy)] -pub enum ClockSrc { +pub enum Sysclk { HSE(Hertz, HseMode), HSI(HSIPrescaler), PLL(PllConfig), @@ -89,7 +89,7 @@ pub enum UsbSrc { /// Clocks configutation pub struct Config { - pub mux: ClockSrc, + pub sys: Sysclk, pub ahb_pre: AHBPrescaler, pub apb_pre: APBPrescaler, pub low_power_run: bool, @@ -102,7 +102,7 @@ impl Default for Config { #[inline] fn default() -> Config { Config { - mux: ClockSrc::HSI(HSIPrescaler::DIV1), + sys: Sysclk::HSI(HSIPrescaler::DIV1), ahb_pre: AHBPrescaler::DIV1, apb_pre: APBPrescaler::DIV1, low_power_run: false, @@ -202,8 +202,8 @@ pub(crate) unsafe fn init(config: Config) { let mut pll1_q_freq = None; let mut pll1_p_freq = None; - let (sys_clk, sw) = match config.mux { - ClockSrc::HSI(div) => { + let (sys_clk, sw) = match config.sys { + Sysclk::HSI(div) => { // Enable HSI RCC.cr().write(|w| { w.set_hsidiv(div); @@ -213,7 +213,7 @@ pub(crate) unsafe fn init(config: Config) { (HSI_FREQ / div, Sw::HSI) } - ClockSrc::HSE(freq, mode) => { + Sysclk::HSE(freq, mode) => { // Enable HSE RCC.cr().write(|w| { w.set_hseon(true); @@ -223,7 +223,7 @@ pub(crate) unsafe fn init(config: Config) { (freq, Sw::HSE) } - ClockSrc::PLL(pll) => { + Sysclk::PLL(pll) => { let (r_freq, q_freq, p_freq) = pll.init(); pll1_q_freq = q_freq; @@ -231,7 +231,7 @@ pub(crate) unsafe fn init(config: Config) { (r_freq, Sw::PLL1_R) } - ClockSrc::LSI => { + Sysclk::LSI => { // Enable LSI RCC.csr().write(|w| w.set_lsion(true)); while !RCC.csr().read().lsirdy() {} diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs index 04ea81ec4..aa4245d4e 100644 --- a/embassy-stm32/src/rcc/l.rs +++ b/embassy-stm32/src/rcc/l.rs @@ -7,7 +7,7 @@ pub use crate::pac::rcc::vals::Adcsel as AdcClockSource; pub use crate::pac::rcc::vals::Clk48sel as Clk48Src; #[cfg(any(stm32wb, stm32wl))] pub use crate::pac::rcc::vals::Hsepre as HsePrescaler; -pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as ClockSrc}; +pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as Sysclk}; use crate::pac::{FLASH, RCC}; use crate::time::Hertz; @@ -50,7 +50,7 @@ pub struct Config { pub pllsai2: Option, // sysclk, buses. - pub mux: ClockSrc, + pub sys: Sysclk, pub ahb_pre: AHBPrescaler, pub apb1_pre: APBPrescaler, pub apb2_pre: APBPrescaler, @@ -80,7 +80,7 @@ impl Default for Config { hse: None, hsi: false, msi: Some(MSIRange::RANGE4M), - mux: ClockSrc::MSI, + sys: Sysclk::MSI, ahb_pre: AHBPrescaler::DIV1, apb1_pre: APBPrescaler::DIV1, apb2_pre: APBPrescaler::DIV1, @@ -113,7 +113,7 @@ pub const WPAN_DEFAULT: Config = Config { mode: HseMode::Oscillator, prescaler: HsePrescaler::DIV1, }), - mux: ClockSrc::PLL1_R, + sys: Sysclk::PLL1_R, #[cfg(crs)] hsi48: Some(super::Hsi48Config { sync_from_usb: false }), msi: None, @@ -161,11 +161,11 @@ pub(crate) unsafe fn init(config: Config) { // Turn on MSI and configure it to 4MHz. msi_enable(MSIRange::RANGE4M) } - if RCC.cfgr().read().sws() != ClockSrc::MSI { + if RCC.cfgr().read().sws() != Sysclk::MSI { // Set MSI as a clock source, reset prescalers. RCC.cfgr().write_value(Cfgr::default()); // Wait for clock switch status bits to change. - while RCC.cfgr().read().sws() != ClockSrc::MSI {} + while RCC.cfgr().read().sws() != Sysclk::MSI {} } // Set voltage scale @@ -260,11 +260,11 @@ pub(crate) unsafe fn init(config: Config) { #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))] let pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input); - let sys_clk = match config.mux { - ClockSrc::HSE => hse.unwrap(), - ClockSrc::HSI => hsi.unwrap(), - ClockSrc::MSI => msi.unwrap(), - ClockSrc::PLL1_R => pll.r.unwrap(), + let sys_clk = match config.sys { + Sysclk::HSE => hse.unwrap(), + Sysclk::HSI => hsi.unwrap(), + Sysclk::MSI => msi.unwrap(), + Sysclk::PLL1_R => pll.r.unwrap(), }; #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))] @@ -350,12 +350,12 @@ pub(crate) unsafe fn init(config: Config) { while FLASH.acr().read().latency() != latency {} RCC.cfgr().modify(|w| { - w.set_sw(config.mux); + w.set_sw(config.sys); w.set_hpre(config.ahb_pre); w.set_ppre1(config.apb1_pre); w.set_ppre2(config.apb2_pre); }); - while RCC.cfgr().read().sws() != config.mux {} + while RCC.cfgr().read().sws() != config.sys {} #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))] RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source)); diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs index 72613f0f3..43138f05c 100644 --- a/embassy-stm32/src/rcc/u5.rs +++ b/embassy-stm32/src/rcc/u5.rs @@ -1,7 +1,7 @@ pub use crate::pac::pwr::vals::Vos as VoltageScale; pub use crate::pac::rcc::vals::{ Hpre as AHBPrescaler, Msirange, Msirange as MSIRange, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul, - Pllsrc as PllSource, Ppre as APBPrescaler, Sw as ClockSrc, + Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk, }; use crate::pac::rcc::vals::{Hseext, Msirgsel, Pllmboost, Pllrge}; use crate::pac::{FLASH, PWR, RCC}; @@ -72,7 +72,7 @@ pub struct Config { pub pll3: Option, // sysclk, buses. - pub mux: ClockSrc, + pub sys: Sysclk, pub ahb_pre: AHBPrescaler, pub apb1_pre: APBPrescaler, pub apb2_pre: APBPrescaler, @@ -97,7 +97,7 @@ impl Default for Config { pll1: None, pll2: None, pll3: None, - mux: ClockSrc::MSIS, + sys: Sysclk::MSIS, ahb_pre: AHBPrescaler::DIV1, apb1_pre: APBPrescaler::DIV1, apb2_pre: APBPrescaler::DIV1, @@ -181,11 +181,11 @@ pub(crate) unsafe fn init(config: Config) { let pll2 = init_pll(PllInstance::Pll2, config.pll2, &pll_input, config.voltage_range); let pll3 = init_pll(PllInstance::Pll3, config.pll3, &pll_input, config.voltage_range); - let sys_clk = match config.mux { - ClockSrc::HSE => hse.unwrap(), - ClockSrc::HSI => hsi.unwrap(), - ClockSrc::MSIS => msi.unwrap(), - ClockSrc::PLL1_R => pll1.r.unwrap(), + let sys_clk = match config.sys { + Sysclk::HSE => hse.unwrap(), + Sysclk::HSI => hsi.unwrap(), + Sysclk::MSIS => msi.unwrap(), + Sysclk::PLL1_R => pll1.r.unwrap(), }; // Do we need the EPOD booster to reach the target clock speed per ยง 10.5.4? @@ -230,8 +230,8 @@ pub(crate) unsafe fn init(config: Config) { }); // Switch the system clock source - RCC.cfgr1().modify(|w| w.set_sw(config.mux)); - while RCC.cfgr1().read().sws() != config.mux {} + RCC.cfgr1().modify(|w| w.set_sw(config.sys)); + while RCC.cfgr1().read().sws() != config.sys {} // Configure the bus prescalers RCC.cfgr2().modify(|w| { diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs index fbf2d1cf9..9d5dcfc4b 100644 --- a/embassy-stm32/src/rcc/wba.rs +++ b/embassy-stm32/src/rcc/wba.rs @@ -1,7 +1,7 @@ pub use crate::pac::pwr::vals::Vos as VoltageScale; use crate::pac::rcc::regs::Cfgr1; pub use crate::pac::rcc::vals::{ - Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as ClockSrc, + Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as Sysclk, }; use crate::pac::{FLASH, RCC}; use crate::time::Hertz; @@ -23,7 +23,7 @@ pub struct Config { pub hse: Option, // sysclk, buses. - pub mux: ClockSrc, + pub sys: Sysclk, pub ahb_pre: AHBPrescaler, pub apb1_pre: APBPrescaler, pub apb2_pre: APBPrescaler, @@ -43,7 +43,7 @@ impl Default for Config { Config { hse: None, hsi: true, - mux: ClockSrc::HSI, + sys: Sysclk::HSI, ahb_pre: AHBPrescaler::DIV1, apb1_pre: APBPrescaler::DIV1, apb2_pre: APBPrescaler::DIV1, @@ -65,11 +65,11 @@ pub(crate) unsafe fn init(config: Config) { if !RCC.cr().read().hsion() { hsi_enable() } - if RCC.cfgr1().read().sws() != ClockSrc::HSI { + if RCC.cfgr1().read().sws() != Sysclk::HSI { // Set HSI as a clock source, reset prescalers. RCC.cfgr1().write_value(Cfgr1::default()); // Wait for clock switch status bits to change. - while RCC.cfgr1().read().sws() != ClockSrc::HSI {} + while RCC.cfgr1().read().sws() != Sysclk::HSI {} } // Set voltage scale @@ -94,11 +94,11 @@ pub(crate) unsafe fn init(config: Config) { HSE_FREQ }); - let sys_clk = match config.mux { - ClockSrc::HSE => hse.unwrap(), - ClockSrc::HSI => hsi.unwrap(), - ClockSrc::_RESERVED_1 => unreachable!(), - ClockSrc::PLL1_R => todo!(), + let sys_clk = match config.sys { + Sysclk::HSE => hse.unwrap(), + Sysclk::HSI => hsi.unwrap(), + Sysclk::_RESERVED_1 => unreachable!(), + Sysclk::PLL1_R => todo!(), }; assert!(sys_clk.0 <= 100_000_000); @@ -142,9 +142,9 @@ pub(crate) unsafe fn init(config: Config) { // TODO: Set the SRAM wait states RCC.cfgr1().modify(|w| { - w.set_sw(config.mux); + w.set_sw(config.sys); }); - while RCC.cfgr1().read().sws() != config.mux {} + while RCC.cfgr1().read().sws() != config.sys {} RCC.cfgr2().modify(|w| { w.set_hpre(config.ahb_pre); -- cgit