From a8de273d61f7bfa6f521dc53f41ed419f8cdc463 Mon Sep 17 00:00:00 2001 From: xoviat Date: Sat, 13 Dec 2025 08:57:08 -0600 Subject: impl. scoped block_stop for ipcc --- embassy-stm32/src/hsem/mod.rs | 3 ++- embassy-stm32/src/ipcc.rs | 5 ++++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'embassy-stm32') diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs index e62de0454..b5fa3c897 100644 --- a/embassy-stm32/src/hsem/mod.rs +++ b/embassy-stm32/src/hsem/mod.rs @@ -148,6 +148,7 @@ impl<'a, T: Instance> HardwareSemaphoreChannel<'a, T> { /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to /// check if the lock has been successful, carried out from the HSEM_Rx register. pub async fn lock(&mut self, process_id: u8) -> HardwareSemaphoreMutex<'a, T> { + let _scoped_block_stop = T::RCC_INFO.block_stop(); let core_id = CoreId::current(); poll_fn(|cx| { @@ -241,7 +242,7 @@ impl HardwareSemaphore { _peripheral: Peri<'d, T>, _irq: impl interrupt::typelevel::Binding> + 'd, ) -> Self { - rcc::enable_and_reset::(); + rcc::enable_and_reset_without_stop::(); HardwareSemaphore { _type: PhantomData } } diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs index fc0f3491e..74ce0b29e 100644 --- a/embassy-stm32/src/ipcc.rs +++ b/embassy-stm32/src/ipcc.rs @@ -85,6 +85,7 @@ impl<'a> IpccTxChannel<'a> { /// Send data to an IPCC channel. The closure is called to write the data when appropriate. pub async fn send(&mut self, f: impl FnOnce()) { + let _scoped_block_stop = IPCC::RCC_INFO.block_stop(); let regs = IPCC::regs(); self.flush().await; @@ -99,6 +100,7 @@ impl<'a> IpccTxChannel<'a> { /// Wait for the tx channel to become clear pub async fn flush(&mut self) { + let _scoped_block_stop = IPCC::RCC_INFO.block_stop(); let regs = IPCC::regs(); // This is a race, but is nice for debugging @@ -144,6 +146,7 @@ impl<'a> IpccRxChannel<'a> { /// Receive data from an IPCC channel. The closure is called to read the data when appropriate. pub async fn receive(&mut self, mut f: impl FnMut() -> Option) -> R { + let _scoped_block_stop = IPCC::RCC_INFO.block_stop(); let regs = IPCC::regs(); loop { @@ -221,7 +224,7 @@ impl Ipcc { + 'd, _config: Config, ) -> Self { - rcc::enable_and_reset::(); + rcc::enable_and_reset_without_stop::(); IPCC::set_cpu2(true); // Verify rfwkpsel is set -- cgit