From 230237b73cbe6f31780ea407ed13bee1adf8eaa2 Mon Sep 17 00:00:00 2001 From: Bogdan Petru Chircu Mare Date: Mon, 1 Dec 2025 09:08:03 -0800 Subject: Apply rustfmt formatting fixes --- examples/src/bin/dma_interleave_transfer.rs | 38 +++++++++++++++++------------ 1 file changed, 23 insertions(+), 15 deletions(-) (limited to 'examples/src/bin/dma_interleave_transfer.rs') diff --git a/examples/src/bin/dma_interleave_transfer.rs b/examples/src/bin/dma_interleave_transfer.rs index 949ea0605..c0ebb0a46 100644 --- a/examples/src/bin/dma_interleave_transfer.rs +++ b/examples/src/bin/dma_interleave_transfer.rs @@ -12,10 +12,9 @@ use embassy_executor::Spawner; use embassy_mcxa::clocks::config::Div8; -use embassy_mcxa::dma::{DmaChannel, DmaCh0InterruptHandler}; -use embassy_mcxa::bind_interrupts; +use embassy_mcxa::dma::{DmaCh0InterruptHandler, DmaChannel}; use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx}; -use embassy_mcxa::pac; +use embassy_mcxa::{bind_interrupts, pac}; use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _}; // Bind DMA channel 0 interrupt using Embassy-style macro @@ -125,22 +124,29 @@ async fn main(_spawner: Spawner) { // Reset channel state t.ch_csr().write(|w| { - w.erq().disable() - .earq().disable() - .eei().no_error() - .ebw().disable() - .done().clear_bit_by_one() + w.erq() + .disable() + .earq() + .disable() + .eei() + .no_error() + .ebw() + .disable() + .done() + .clear_bit_by_one() }); t.ch_es().write(|w| w.bits(0)); t.ch_int().write(|w| w.int().clear_bit_by_one()); // Source/destination addresses - t.tcd_saddr().write(|w| w.saddr().bits(core::ptr::addr_of_mut!(SRC_BUFFER) as u32)); - t.tcd_daddr().write(|w| w.daddr().bits(core::ptr::addr_of_mut!(DEST_BUFFER) as u32)); + t.tcd_saddr() + .write(|w| w.saddr().bits(core::ptr::addr_of_mut!(SRC_BUFFER) as u32)); + t.tcd_daddr() + .write(|w| w.daddr().bits(core::ptr::addr_of_mut!(DEST_BUFFER) as u32)); // Custom offsets for interleaving - t.tcd_soff().write(|w| w.soff().bits(4)); // src: +4 bytes per read - t.tcd_doff().write(|w| w.doff().bits(8)); // dst: +8 bytes per write + t.tcd_soff().write(|w| w.soff().bits(4)); // src: +4 bytes per read + t.tcd_doff().write(|w| w.doff().bits(8)); // dst: +8 bytes per write // Attributes: 32-bit transfers (size = 2) t.tcd_attr().write(|w| w.ssize().bits(2).dsize().bits(2)); @@ -153,7 +159,8 @@ async fn main(_spawner: Spawner) { t.tcd_slast_sda().write(|w| w.slast_sda().bits(-(nbytes as i32) as u32)); // Destination uses 2x offset, so adjust accordingly let dst_total = (HALF_BUFF_LENGTH * 8) as u32; - t.tcd_dlast_sga().write(|w| w.dlast_sga().bits(-(dst_total as i32) as u32)); + t.tcd_dlast_sga() + .write(|w| w.dlast_sga().bits(-(dst_total as i32) as u32)); // Major loop count = 1 t.tcd_biter_elinkno().write(|w| w.biter().bits(1)); @@ -172,7 +179,9 @@ async fn main(_spawner: Spawner) { while !dma_ch0.is_done() { cortex_m::asm::nop(); } - unsafe { dma_ch0.clear_done(); } + unsafe { + dma_ch0.clear_done(); + } tx.blocking_write(b"\r\nEDMA interleave transfer example finish.\r\n\r\n") .unwrap(); @@ -206,4 +215,3 @@ async fn main(_spawner: Spawner) { cortex_m::asm::wfe(); } } - -- cgit