From e7161aa085bb145df6607eff5b2c2d0ed06acda1 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Wed, 22 May 2024 00:23:14 +0200 Subject: stm32/qspi: remove DMA generic param. --- examples/stm32f7/src/bin/qspi.rs | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'examples/stm32f7') diff --git a/examples/stm32f7/src/bin/qspi.rs b/examples/stm32f7/src/bin/qspi.rs index 005694db3..90d319b7a 100644 --- a/examples/stm32f7/src/bin/qspi.rs +++ b/examples/stm32f7/src/bin/qspi.rs @@ -4,8 +4,9 @@ use defmt::info; use embassy_executor::Spawner; +use embassy_stm32::mode::Async; use embassy_stm32::qspi::enums::{AddressSize, ChipSelectHighTime, FIFOThresholdLevel, MemorySize, *}; -use embassy_stm32::qspi::{Config as QspiCfg, Instance, Qspi, QuadDma, TransferConfig}; +use embassy_stm32::qspi::{Config as QspiCfg, Instance, Qspi, TransferConfig}; use embassy_stm32::time::mhz; use embassy_stm32::Config as StmCfg; use {defmt_rtt as _, panic_probe as _}; @@ -43,12 +44,12 @@ const MEMORY_ADDR: u32 = 0x00000000u32; /// Implementation of access to flash chip. /// Chip commands are hardcoded as it depends on used chip. /// This implementation is using chip GD25Q64C from Giga Device -pub struct FlashMemory> { - qspi: Qspi<'static, I, D>, +pub struct FlashMemory { + qspi: Qspi<'static, I, Async>, } -impl> FlashMemory { - pub fn new(qspi: Qspi<'static, I, D>) -> Self { +impl FlashMemory { + pub fn new(qspi: Qspi<'static, I, Async>) -> Self { let mut memory = Self { qspi }; memory.reset_memory(); @@ -279,7 +280,7 @@ async fn main(_spawner: Spawner) -> ! { cs_high_time: ChipSelectHighTime::_1Cycle, fifo_threshold: FIFOThresholdLevel::_16Bytes, }; - let driver = Qspi::new_bk1( + let driver = Qspi::new_bank1( p.QUADSPI, p.PF8, p.PF9, p.PE2, p.PF6, p.PF10, p.PB10, p.DMA2_CH7, config, ); let mut flash = FlashMemory::new(driver); -- cgit