From a39ae12edcf23935df82d547fb2d997ca6b7c8d5 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 23 Oct 2023 01:48:09 +0200 Subject: stm32/rcc: misc cleanups. --- examples/stm32h7/src/bin/low_level_timer_api.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'examples/stm32h7/src/bin/low_level_timer_api.rs') diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs index 0355ac073..e4bac8a5a 100644 --- a/examples/stm32h7/src/bin/low_level_timer_api.rs +++ b/examples/stm32h7/src/bin/low_level_timer_api.rs @@ -17,18 +17,18 @@ async fn main(_spawner: Spawner) { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; config.rcc.hsi48 = true; // needed for RNG - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: Some(PllDiv::DIV8), // 100mhz divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz -- cgit