From ecdd7c0e2f9dcc07e53e136557140d3ccc6a5ee1 Mon Sep 17 00:00:00 2001 From: pbert Date: Wed, 11 Oct 2023 21:38:41 +0200 Subject: enable clock first --- examples/stm32l4/src/bin/dac_dma.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'examples/stm32l4/src') diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs index 83d48f221..98f37f906 100644 --- a/examples/stm32l4/src/bin/dac_dma.rs +++ b/examples/stm32l4/src/bin/dac_dma.rs @@ -51,7 +51,7 @@ async fn dac_task1(mut dac: Dac1Type) { dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap(); dac.enable_channel().unwrap(); - TIM6::reset_and_enable(); + TIM6::enable_and_reset(); TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); TIM6::regs().cr1().modify(|w| { @@ -90,7 +90,7 @@ async fn dac_task2(mut dac: Dac2Type) { error!("Reload value {} below threshold!", reload); } - TIM7::reset_and_enable(); + TIM7::enable_and_reset(); TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); TIM7::regs().cr1().modify(|w| { -- cgit