From 04c0bd84e6043ac35d2a20f1f4a789ccf79bb316 Mon Sep 17 00:00:00 2001
From: ragarnoy <tiagolernould@gmail.com>
Date: Sat, 10 May 2025 10:04:34 +0200
Subject: fix release mode that was broken by lto and codegen units (there are
 probably things that can be done to be able to keep lto, I haven't found yet)

---
 examples/stm32h755cm4/Cargo.toml           |  5 ++---
 examples/stm32h755cm4/src/bin/intercore.rs |  8 ++++----
 examples/stm32h755cm7/Cargo.toml           |  3 +--
 examples/stm32h755cm7/src/bin/intercore.rs | 18 +++++++++++++-----
 4 files changed, 20 insertions(+), 14 deletions(-)

(limited to 'examples')

diff --git a/examples/stm32h755cm4/Cargo.toml b/examples/stm32h755cm4/Cargo.toml
index c6d4996f1..d2b9b1f0e 100644
--- a/examples/stm32h755cm4/Cargo.toml
+++ b/examples/stm32h755cm4/Cargo.toml
@@ -49,12 +49,11 @@ overflow-checks = true # <-
 
 # cargo build/run --release
 [profile.release]
-codegen-units = 1
+codegen-units = 16
 debug = 2
 debug-assertions = false # <-
 incremental = false
-#lto = 'fat'
-#opt-level = 3 # <-
+opt-level = 3 # <-
 overflow-checks = false # <-
 
 # cargo test --release
diff --git a/examples/stm32h755cm4/src/bin/intercore.rs b/examples/stm32h755cm4/src/bin/intercore.rs
index 8f61c3eb2..3a66a1ecd 100644
--- a/examples/stm32h755cm4/src/bin/intercore.rs
+++ b/examples/stm32h755cm4/src/bin/intercore.rs
@@ -45,7 +45,7 @@ mod shared {
             };
 
             self.led_states.store(new_value, Ordering::SeqCst);
-            core::sync::atomic::compiler_fence(Ordering::SeqCst);
+            core::sync::atomic::fence(Ordering::SeqCst);
         }
 
         /// Get LED state using safe bit operations
@@ -54,7 +54,7 @@ mod shared {
             let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT };
 
             let value = self.led_states.load(Ordering::SeqCst);
-            core::sync::atomic::compiler_fence(Ordering::SeqCst);
+            core::sync::atomic::fence(Ordering::SeqCst);
 
             (value & (1 << bit)) != 0
         }
@@ -66,7 +66,7 @@ mod shared {
             let current = self.counter.load(Ordering::SeqCst);
             let new_value = current.wrapping_add(1);
             self.counter.store(new_value, Ordering::SeqCst);
-            core::sync::atomic::compiler_fence(Ordering::SeqCst);
+            core::sync::atomic::fence(Ordering::SeqCst);
             new_value
         }
 
@@ -74,7 +74,7 @@ mod shared {
         #[inline(never)]
         pub fn get_counter(&self) -> u32 {
             let value = self.counter.load(Ordering::SeqCst);
-            core::sync::atomic::compiler_fence(Ordering::SeqCst);
+            core::sync::atomic::fence(Ordering::SeqCst);
             value
         }
     }
diff --git a/examples/stm32h755cm7/Cargo.toml b/examples/stm32h755cm7/Cargo.toml
index 06a3b06af..2e34f0928 100644
--- a/examples/stm32h755cm7/Cargo.toml
+++ b/examples/stm32h755cm7/Cargo.toml
@@ -47,11 +47,10 @@ overflow-checks = true # <-
 
 # cargo build/run --release
 [profile.release]
-codegen-units = 1
+codegen-units = 16
 debug = 2
 debug-assertions = false # <-
 incremental = false
-lto = 'fat'
 opt-level = 3 # <-
 overflow-checks = false # <-
 
diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs
index f01d6a6b7..f1fbd29bc 100644
--- a/examples/stm32h755cm7/src/bin/intercore.rs
+++ b/examples/stm32h755cm7/src/bin/intercore.rs
@@ -4,7 +4,7 @@
 use core::mem::MaybeUninit;
 
 use cortex_m::asm;
-use cortex_m::peripheral::{MPU, SCB};
+use cortex_m::peripheral::MPU;
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::{Config, SharedData};
@@ -102,7 +102,7 @@ mod shared {
 static SHARED_DATA: MaybeUninit<SharedData> = MaybeUninit::uninit();
 
 // Function to configure MPU with your provided settings
-fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) {
+fn configure_mpu_non_cacheable(mpu: &mut MPU) {
     // Ensure all operations complete before reconfiguring MPU/caches
     asm::dmb();
     unsafe {
@@ -147,11 +147,19 @@ async fn main(_spawner: Spawner) -> ! {
     // Configure MPU to make SRAM4 non-cacheable
     {
         let mut cp = cortex_m::Peripherals::take().unwrap();
-        let mpu = &mut cp.MPU;
         let scb = &mut cp.SCB;
 
-        // Configure MPU without disabling caches
-        configure_mpu_non_cacheable(mpu, scb);
+        scb.disable_icache();
+        scb.disable_dcache(&mut cp.CPUID);
+
+        // 2. MPU setup
+        configure_mpu_non_cacheable(&mut cp.MPU);
+
+        // 3. re-enable caches
+        scb.enable_icache();
+        scb.enable_dcache(&mut cp.CPUID);
+        asm::dsb();
+        asm::isb();
     }
 
     // Configure the clocks
-- 
cgit