From 09982214788def209316ef70cae08eead964e206 Mon Sep 17 00:00:00 2001
From: xoviat <xoviat@users.noreply.github.com>
Date: Mon, 19 Jun 2023 16:05:59 -0500
Subject: stm32/can: update interrupts

---
 examples/stm32f4/src/bin/can.rs | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

(limited to 'examples')

diff --git a/examples/stm32f4/src/bin/can.rs b/examples/stm32f4/src/bin/can.rs
index e8377b9a1..da8955053 100644
--- a/examples/stm32f4/src/bin/can.rs
+++ b/examples/stm32f4/src/bin/can.rs
@@ -4,12 +4,21 @@
 
 use cortex_m_rt::entry;
 use defmt::*;
+use embassy_stm32::bind_interrupts;
 use embassy_stm32::can::bxcan::filter::Mask32;
 use embassy_stm32::can::bxcan::{Fifo, Frame, StandardId};
-use embassy_stm32::can::Can;
+use embassy_stm32::can::{Can, Rx0InterruptHandler, Rx1InterruptHandler, SceInterruptHandler, TxInterruptHandler};
 use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::peripherals::CAN1;
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(struct Irqs {
+    CAN1_RX0 => Rx0InterruptHandler<CAN1>;
+    CAN1_RX1 => Rx1InterruptHandler<CAN1>;
+    CAN1_SCE => SceInterruptHandler<CAN1>;
+    CAN1_TX => TxInterruptHandler<CAN1>;
+});
+
 #[entry]
 fn main() -> ! {
     info!("Hello World!");
@@ -23,7 +32,7 @@ fn main() -> ! {
     let rx_pin = Input::new(&mut p.PA11, Pull::Up);
     core::mem::forget(rx_pin);
 
-    let mut can = Can::new(p.CAN1, p.PA11, p.PA12);
+    let mut can = Can::new(p.CAN1, p.PA11, p.PA12, Irqs);
 
     can.modify_filters().enable_bank(0, Fifo::Fifo0, Mask32::accept_all());
 
-- 
cgit