From 1b3674b30ac2b7deb8e19b132d5ba15351cb8ebd Mon Sep 17 00:00:00 2001 From: Gerzain Mata Date: Sun, 27 Jul 2025 09:35:13 -0700 Subject: Added changes based on PR review --- examples/stm32wba/src/bin/pwm.rs | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'examples') diff --git a/examples/stm32wba/src/bin/pwm.rs b/examples/stm32wba/src/bin/pwm.rs index 54d223d34..611d7c097 100644 --- a/examples/stm32wba/src/bin/pwm.rs +++ b/examples/stm32wba/src/bin/pwm.rs @@ -5,7 +5,7 @@ use defmt::*; use defmt_rtt as _; // global logger use embassy_executor::Spawner; use embassy_stm32::gpio::OutputType; -use embassy_stm32::rcc::{mux, AHB5Prescaler, AHBPrescaler, APBPrescaler, Sysclk, VoltageScale}; +use embassy_stm32::rcc::{AHB5Prescaler, AHBPrescaler, APBPrescaler, Sysclk, VoltageScale}; use embassy_stm32::rcc::{PllDiv, PllMul, PllPreDiv, PllSource}; use embassy_stm32::time::khz; use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm}; @@ -39,7 +39,6 @@ async fn main(_spawner: Spawner) { // voltage scale for max performance config.rcc.voltage_scale = VoltageScale::RANGE1; // route PLL1_P into the USB‐OTG‐HS block - config.rcc.mux.otghssel = mux::Otghssel::PLL1_P; config.rcc.sys = Sysclk::PLL1_R; let p = embassy_stm32::init(config); -- cgit