From 60b640bd977ac2d056061e0c0b7a497f815417f4 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 25 Aug 2025 17:31:38 +0200
Subject: stm32/sai: update for new metapac, simplify cfgs.

---
 examples/stm32h7/src/bin/sai.rs       | 72 ++---------------------------------
 examples/stm32h723/src/bin/spdifrx.rs |  2 +-
 2 files changed, 5 insertions(+), 69 deletions(-)

(limited to 'examples')

diff --git a/examples/stm32h7/src/bin/sai.rs b/examples/stm32h7/src/bin/sai.rs
index 01937593a..847b70c85 100644
--- a/examples/stm32h7/src/bin/sai.rs
+++ b/examples/stm32h7/src/bin/sai.rs
@@ -63,7 +63,7 @@ async fn main(_spawner: Spawner) {
     tx_config.tx_rx = TxRx::Transmitter;
     tx_config.sync_output = true;
     tx_config.clock_strobe = ClockStrobe::Falling;
-    tx_config.master_clock_divider = mclk_div;
+    tx_config.master_clock_divider = Some(mclk_div);
     tx_config.stereo_mono = StereoMono::Stereo;
     tx_config.data_size = DataSize::Data24;
     tx_config.bit_order = BitOrder::MsbFirst;
@@ -119,71 +119,7 @@ async fn main(_spawner: Spawner) {
     }
 }
 
-const fn mclk_div_from_u8(v: u8) -> MasterClockDivider {
-    match v {
-        1 => MasterClockDivider::Div1,
-        2 => MasterClockDivider::Div2,
-        3 => MasterClockDivider::Div3,
-        4 => MasterClockDivider::Div4,
-        5 => MasterClockDivider::Div5,
-        6 => MasterClockDivider::Div6,
-        7 => MasterClockDivider::Div7,
-        8 => MasterClockDivider::Div8,
-        9 => MasterClockDivider::Div9,
-        10 => MasterClockDivider::Div10,
-        11 => MasterClockDivider::Div11,
-        12 => MasterClockDivider::Div12,
-        13 => MasterClockDivider::Div13,
-        14 => MasterClockDivider::Div14,
-        15 => MasterClockDivider::Div15,
-        16 => MasterClockDivider::Div16,
-        17 => MasterClockDivider::Div17,
-        18 => MasterClockDivider::Div18,
-        19 => MasterClockDivider::Div19,
-        20 => MasterClockDivider::Div20,
-        21 => MasterClockDivider::Div21,
-        22 => MasterClockDivider::Div22,
-        23 => MasterClockDivider::Div23,
-        24 => MasterClockDivider::Div24,
-        25 => MasterClockDivider::Div25,
-        26 => MasterClockDivider::Div26,
-        27 => MasterClockDivider::Div27,
-        28 => MasterClockDivider::Div28,
-        29 => MasterClockDivider::Div29,
-        30 => MasterClockDivider::Div30,
-        31 => MasterClockDivider::Div31,
-        32 => MasterClockDivider::Div32,
-        33 => MasterClockDivider::Div33,
-        34 => MasterClockDivider::Div34,
-        35 => MasterClockDivider::Div35,
-        36 => MasterClockDivider::Div36,
-        37 => MasterClockDivider::Div37,
-        38 => MasterClockDivider::Div38,
-        39 => MasterClockDivider::Div39,
-        40 => MasterClockDivider::Div40,
-        41 => MasterClockDivider::Div41,
-        42 => MasterClockDivider::Div42,
-        43 => MasterClockDivider::Div43,
-        44 => MasterClockDivider::Div44,
-        45 => MasterClockDivider::Div45,
-        46 => MasterClockDivider::Div46,
-        47 => MasterClockDivider::Div47,
-        48 => MasterClockDivider::Div48,
-        49 => MasterClockDivider::Div49,
-        50 => MasterClockDivider::Div50,
-        51 => MasterClockDivider::Div51,
-        52 => MasterClockDivider::Div52,
-        53 => MasterClockDivider::Div53,
-        54 => MasterClockDivider::Div54,
-        55 => MasterClockDivider::Div55,
-        56 => MasterClockDivider::Div56,
-        57 => MasterClockDivider::Div57,
-        58 => MasterClockDivider::Div58,
-        59 => MasterClockDivider::Div59,
-        60 => MasterClockDivider::Div60,
-        61 => MasterClockDivider::Div61,
-        62 => MasterClockDivider::Div62,
-        63 => MasterClockDivider::Div63,
-        _ => panic!(),
-    }
+fn mclk_div_from_u8(v: u8) -> MasterClockDivider {
+    assert!((1..=63).contains(&v));
+    MasterClockDivider::from_bits(v)
 }
diff --git a/examples/stm32h723/src/bin/spdifrx.rs b/examples/stm32h723/src/bin/spdifrx.rs
index 6d29e8a4d..b75a03ae8 100644
--- a/examples/stm32h723/src/bin/spdifrx.rs
+++ b/examples/stm32h723/src/bin/spdifrx.rs
@@ -168,7 +168,7 @@ fn new_sai_transmitter<'d>(
     sai_config.slot_enable = 0xFFFF; // All slots
     sai_config.data_size = sai::DataSize::Data32;
     sai_config.frame_length = (CHANNEL_COUNT * 32) as u8;
-    sai_config.master_clock_divider = hal::sai::MasterClockDivider::MasterClockDisabled;
+    sai_config.master_clock_divider = None;
 
     let (sub_block_tx, _) = hal::sai::split_subblocks(sai);
     Sai::new_asynchronous(sub_block_tx, sck, sd, fs, dma, buf, sai_config)
-- 
cgit