From a5e8891fe315e2ee84992d94bd7f7d5b7710cce6 Mon Sep 17 00:00:00 2001
From: Gerzain Mata <gmata@axon.com>
Date: Fri, 25 Jul 2025 18:57:27 -0700
Subject: Added support for PLL as a clock source on STM32WBA

- PLL multiplier and dividers work
- Added timer example
---
 examples/stm32wba/src/bin/pwm.rs | 65 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 examples/stm32wba/src/bin/pwm.rs

(limited to 'examples')

diff --git a/examples/stm32wba/src/bin/pwm.rs b/examples/stm32wba/src/bin/pwm.rs
new file mode 100644
index 000000000..54d223d34
--- /dev/null
+++ b/examples/stm32wba/src/bin/pwm.rs
@@ -0,0 +1,65 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use defmt_rtt as _; // global logger
+use embassy_executor::Spawner;
+use embassy_stm32::gpio::OutputType;
+use embassy_stm32::rcc::{mux, AHB5Prescaler, AHBPrescaler, APBPrescaler, Sysclk, VoltageScale};
+use embassy_stm32::rcc::{PllDiv, PllMul, PllPreDiv, PllSource};
+use embassy_stm32::time::khz;
+use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm};
+use embassy_stm32::Config;
+use embassy_time::Timer;
+use panic_probe as _;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    info!("Hello World!");
+
+    let mut config = Config::default();
+    // Fine-tune PLL1 dividers/multipliers
+    config.rcc.pll1 = Some(embassy_stm32::rcc::Pll {
+        source: PllSource::HSI,
+        prediv: PllPreDiv::DIV1,  // PLLM = 1 → HSI / 1 = 16 MHz
+        mul: PllMul::MUL30,       // PLLN = 30 → 16 MHz * 30 = 480 MHz VCO
+        divr: Some(PllDiv::DIV5), // PLLR = 5 → 96 MHz (Sysclk)
+        // divq: Some(PllDiv::DIV10), // PLLQ = 10 → 48 MHz (NOT USED)
+        divq: None,
+        divp: Some(PllDiv::DIV30), // PLLP = 30 → 16 MHz (USBOTG)
+        frac: Some(0),             // Fractional part (enabled)
+    });
+
+    config.rcc.ahb_pre = AHBPrescaler::DIV1;
+    config.rcc.apb1_pre = APBPrescaler::DIV1;
+    config.rcc.apb2_pre = APBPrescaler::DIV1;
+    config.rcc.apb7_pre = APBPrescaler::DIV1;
+    config.rcc.ahb5_pre = AHB5Prescaler::DIV4;
+
+    // voltage scale for max performance
+    config.rcc.voltage_scale = VoltageScale::RANGE1;
+    // route PLL1_P into the USB‐OTG‐HS block
+    config.rcc.mux.otghssel = mux::Otghssel::PLL1_P;
+    config.rcc.sys = Sysclk::PLL1_R;
+
+    let p = embassy_stm32::init(config);
+
+    let ch1_pin = PwmPin::new(p.PA2, OutputType::PushPull);
+    let mut pwm = SimplePwm::new(p.TIM3, Some(ch1_pin), None, None, None, khz(10), Default::default());
+    let mut ch1 = pwm.ch1();
+    ch1.enable();
+
+    info!("PWM initialized");
+    info!("PWM max duty {}", ch1.max_duty_cycle());
+
+    loop {
+        ch1.set_duty_cycle_fully_off();
+        Timer::after_millis(300).await;
+        ch1.set_duty_cycle_fraction(1, 4);
+        Timer::after_millis(300).await;
+        ch1.set_duty_cycle_fraction(1, 2);
+        Timer::after_millis(300).await;
+        ch1.set_duty_cycle(ch1.max_duty_cycle() - 1);
+        Timer::after_millis(300).await;
+    }
+}
-- 
cgit