From c8c4b0b701ecfbb146c6f651bebd43f053f55ac2 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sun, 3 Mar 2024 23:19:54 +0100 Subject: stm32/rcc: port g0 to new api. --- examples/stm32g0/src/bin/hf_timer.rs | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'examples') diff --git a/examples/stm32g0/src/bin/hf_timer.rs b/examples/stm32g0/src/bin/hf_timer.rs index 647ff0419..3ea06cdee 100644 --- a/examples/stm32g0/src/bin/hf_timer.rs +++ b/examples/stm32g0/src/bin/hf_timer.rs @@ -16,15 +16,16 @@ async fn main(_spawner: Spawner) { let mut config = PeripheralConfig::default(); { use embassy_stm32::rcc::*; - - config.rcc.sys = Sysclk::PLL(PllConfig { + config.rcc.hsi = true; + config.rcc.pll = Some(Pll { source: PllSource::HSI, - m: Pllm::DIV1, - n: Plln::MUL16, - r: Pllr::DIV4, // CPU clock comes from PLLR (HSI (16MHz) / 1 * 16 / 4 = 64MHz) - q: Some(Pllq::DIV2), // TIM1 or TIM15 can be sourced from PLLQ (HSI (16MHz) / 1 * 16 / 2 = 128MHz) - p: None, + prediv: PllPreDiv::DIV1, + mul: PllMul::MUL16, + divp: None, + divq: Some(PllQDiv::DIV2), // 16 / 1 * 16 / 2 = 128 Mhz + divr: Some(PllRDiv::DIV4), // 16 / 1 * 16 / 4 = 64 Mhz }); + config.rcc.sys = Sysclk::PLL1_R; // configure TIM1 mux to select PLLQ as clock source // https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf -- cgit